JPH04116861A - Hybrid semiconductor device - Google Patents

Abstract

PURPOSE:To three-dimensionally build-in a compound semiconductor chip and a silicon semiconductor chip, by a method wherein the difference of thermal expansion coefficients is relieved by connecting only the respective wiring layers without bonding the respective semiconductor substrates. CONSTITUTION:After an ECL circuit is formed on a p-type silicon substrate 11, a silicide electrode 5 is formed, and a multilayer wiring is formed by using Al. After bonding pads 16 for mounting the ECL circuit chip and bonding pads 2 for connecting a compound semiconductor chip are formed, the chips are scribed from the wafer. GaAs is used for the compound semiconductor; Schottky electrodes 6 are formed on an n-type operating layer 13 on a GaAs substrate 15, thereby forming an MESFET; a compound semiconductor circuit is constituted by combining the elements and wiring them. After bonding pads 2 are formed, the scribing from the wafer is performed. The bonding pads 2 of the compound semiconductor circuit chip 17 and the ECL circuit chip 18 are connected by Au bumps and adhesive agent, and the elements are mounted on a package or a film, thereby completing a device.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to structures of ultra-high speed semiconductor integrated circuits and optical integrated circuits.

[Conventional technology]

High-speed silicon ECL (Emitter Couple) is a compound semiconductor circuit featuring low power consumption and low noise.
If it can be incorporated into an ECL circuit (ED Logic), it will be possible to realize a high-speed circuit that compensates for the drawback of ECL circuits, such as high power consumption. However, the method of growing compound semiconductor crystals on a silicon substrate requires complicated process steps, and it is difficult to set optimal process conditions for both devices. Therefore, a method of combining separately formed silicon semiconductor and compound semiconductor chips may be considered. As a conventional example of combining chips with each other, IDM84 Technical Digest, pages 816 to 819 (IEDM84 Technical Digest)
igests p816-819 (1984)), p-channel MOSFET formed on an n-type substrate
T (Metal Oxide 5ilicon Fi)
eldEffect Transistor) circuit;
A method of bonding an n-channel MO8FET circuit formed on an n-type substrate with polyimide resin (organic adhesive) has been proposed, and a method has also been proposed in Proceedings of the 38th Electronic Components Conference, pp. 267 to 275.
Page (38th Electronic Component
nts Conference P-roceedin
gs p267-275 (1988)),
A method of embedding a plurality of IC chips in a silicon substrate has been proposed.

[Problems to be Solved by the Invention] Although the method of bonding two IC chips with adhesive has the advantage of allowing multiple chips to be connected three-dimensionally, it is difficult to connect two IC chips with each other with different coefficients of thermal expansion, such as silicon semiconductor chips. There is a drawback that it cannot be used for connection with compound semiconductor chips such as GaAs. Furthermore, since no consideration is given to heat dissipation from the chip surface, there is also the drawback that reliability is reduced in circuits that include bipolar elements that generate a large amount of heat. On the other hand, the method of embedding IC chips in a silicon substrate has the advantage of being able to combine IC chips with different coefficients of thermal expansion, but has the disadvantage of requiring a large area because all the chips are two-dimensionally combined. Therefore, an object of the present invention is to provide a method for three-dimensionally assembling a compound semiconductor chip and a silicon semiconductor chip.

[Means to solve the problem]

In order to achieve the above object, instead of bonding the semiconductor substrates together, only their wiring layers are connected, and by not bonding the semiconductor substrates together, the difference in thermal expansion coefficients can be alleviated. As a means of connecting mutual wiring layers,
This uses an Au bump method that allows bonding from any position on the chip. In order to employ the Au bump method, which has conventionally been used as a method for mounting IC chips on a printed circuit board, for inter-chip connections, bonding pads are formed not on the substrate but on the wiring layer. 1 Effect] Compound semiconductor circuits with low power consumption are used for logic operation sections, storage sections, etc., and Si ECL circuits with high load driving capacity are used for input/output sections, A/D, D/A conversion sections, etc. By doing so, it is possible to realize a semiconductor device that takes advantage of each other's strengths. Since compound semiconductor devices and silicon semiconductor devices connect chips to each other, it is possible to design an optimal process for each. Since the connections are made in each wiring layer, differences in the thermal expansion coefficients of the substrates do not pose a problem. Also, since the substrates are separated from each other, heat transfer from the ECL circuit to the compound semiconductor circuit is reduced. Since the compound semiconductor device and the silicon semiconductor device are directly connected by wiring, impedance mismatch is small and high-speed signal transmission is possible.

【Example】

(Example 1) Hereinafter, one example of the present invention will be described with reference to FIG. After forming an ECL circuit on a p-type silicon substrate 11, a polycide electrode 5 is formed and multilayer wiring using Al is performed. At this time, in addition to the normal power supply line and ground line, the top layer of the chip surface has a bonding pad 16 for mounting the ECL circuit chip, which draws out wiring for connecting to the compound semiconductor device, and the compound semiconductor. After providing a bonding pad 2 for connection to the chip, the chip is scribed from the wafer. The chip size is 15 x 15 mm, and the size of the bonding pad 2 is 120 x 120 μm2.
, the bonding pad 16 is 200×200 μm2. GaAs is used as the compound semiconductor, and semi-insulating G
A Schottky electrode 6 is formed on the n-type active layer 13 on the aAs substrate 15, and M E S F E T (M
etal S emieonductor F 1
effect transistor)
is fabricated, combined with other elements (resistors, capacitors, diodes, etc.), and wired to form a compound semiconductor circuit. After providing a bonding pad 2 on the surface of the chip from which wiring for connecting to a silicon semiconductor is drawn out, the chip is scribed from a wafer. Chip size is 4X4
The present invention is completed by connecting the bonding pads 2 of the compound semiconductor circuit chip 17 and the ECL circuit chip 18 with Au bumps and an adhesive (conductive paste), and mounting them on a package or film. The completed composite semiconductor device is shown in Fig. 2. In this example, a circuit consisting of GaAs MESFET was formed on the semi-insulating GaAs substrate 15, but GaAs, AlGaAs, InAs, InGa
As. It is also possible to use a compound semiconductor device manufactured by growing a compound semiconductor such as InP or InSb on a GaAs or other compound semiconductor substrate, silicon substrate, glass substrate, or ceramic substrate. Regarding the device structure, HEMT (High ElectronMob
ity Transistor), MISF
E T (Metal In5lator Se
m1conductor FET), DMT (
Doped-channel hetero MISF
ET), IGFET (Insulated
GateFET), HB T (Hetero B
IPolar Transistor), etc. can be used. Silicon ECL circuit is MOS FET (M
etalOxide Sem1conductor F
It is also possible to mix ET) circuits to form a PI-CMO5 circuit. As the Au bump 1, it is also possible to use an In alloy (Au) bump or Sn alloy having a lower melting point. (Embodiment 2) In addition to bonding chips to each other, the present invention is also capable of bonding chips to wafers, and an embodiment of the present invention is shown in FIG. 3, in which a plurality of integrated circuits are formed on a silicon wafer. Wafer scale circuit 1 is created by wiring between circuits using multilayer wiring.
9 and provide a bonding pad 2 on the wafer surface for connection with the GaAs
After scribing the IC as a chip, Au bump 1
connected to the silicon wafer scale circuit 19 by
Attach it on the printed circuit board 2o*GaAs I
It is also possible to use a device made of another compound semiconductor instead of C, and it is also possible to connect multiple types of compound semiconductor devices. (Example 3) In Example 1.2, multilayer wiring was performed on the compound semiconductor side,
Although it is connected to the silicon circuit, it is also possible to form the wiring on the compound semiconductor side on the silicon circuit side, and one embodiment in this case is shown in FIG. GaAs MESFET for compound semiconductor IC
The gate electrode is formed by a pattern inversion method, and the gate material has A u / P t / T
i (200150150n Peng) is used. Au/Pt/T i (200150150n
m) and formed at the same time as the gate electrode. In addition to these, Ti, AI/Ti, Al/Mo, etc. can be used as the electrode material, and it is also possible to use different materials for the gate electrode and the ohmic electrode. Mo/ A u/ Mo(100/800/10100
A first layer of wiring and a bonding pad 2 are formed by vapor depositing n by a lift-off method, and connected to a silicon Pi-0M08 circuit using an In alloy (Au) bump 1. The second and subsequent layers of the GaAs circuit are provided in the multilayer wiring region on the silicon circuit side. In the case of this example, the compound semiconductor device is monolithic,
On the other hand, it has the disadvantage that only low-integration circuits can be used, but the heat C
There is no need for a step of forming an interlayer insulating film using a VD (chemical vapor deposition) method or a step of depositing metal wiring using a bias sputtering method, and there is an advantage that the process steps on the compound semiconductor device side can be made at a lower temperature. Although this example is explained using GaAs MESFET, it is possible to use other compound semiconductors such as InAs, InGaAs, GaSb, and InP.
It is also possible to use devices such as T. (Embodiment 4) FIG. 5 shows an embodiment in which an optical integrated circuit is used as a compound semiconductor. Buried Heterostructure Laser Diode in InP Substrate
La5sr Diode) and photodetector (Photo
The case where M
Q W (Multi-quantum vell)
Lasers and APD (Avalanche Ph-o)
It is possible to incorporate FETs, FETs, etc. (b) shows the structure of the laser diode, and (C) shows the structure of the photodetector. The laser diode integrates a Schottky junction FET as a preamplifier. The photodetector consists of a p-1-n type photodiode structure. InxGa1-xA5yP, -y on the n-type InP substrate 24
Active layer 25, p-type rat layer 26, n-type rat layer 27
was formed by LPE ('Liquid Phase Epitaxy) method, processed by reverse mesa etch, and then p-InP and n were formed by LPE method.
- Grow InP to form a buried active layer. After depositing 200 nm of Si, N, and film 30 as an insulating film, the Si, N, and film 30 are removed in the electrode region, and 400 nm of titanium is deposited by lift-off method as a Schottky electrode. After forming the Schottky electrode, a P-type electrode made of Au/Zn/Au is formed by lift-off method, and Au/Sn/Au is formed on the back side.
After depositing an n-type electrode made of Au, a bonding pad 2 is formed and the chip is scribed. The optical integrated circuit thus completed is made of silicon ECL or PI-C.
Connect to MO8 circuit using Au bump method. In this example, an optical integrated circuit made of InP was used, but GaP-GaAs, GaSb, AlGaAs, In
Other ■-V group compound semiconductors such as AlAs, or Zn5
It is also possible to form an optical integrated circuit using a ■-■ group compound semiconductor such as E, CdS, etc.

【Effect of the invention】

According to the present invention, a compound semiconductor circuit is formed using silicon ECL.
Since it can be incorporated into circuits, high-speed, low-power consumption composite circuits can be constructed. Since the compound semiconductor circuit and the ECL circuit are manufactured separately, the optimal process conditions can be selected for each. Compound semiconductor circuits and ECL circuits can significantly reduce delay time compared to packaging individual chips or mounting chips in modules. Since compound semiconductors can also be used as light-emitting and light-receiving elements, according to the present invention, an optical integrated circuit can be incorporated into an ECL circuit. A silicon ECL circuit can also be used as a pie CMO8 circuit by mixing a CMO8 circuit. Furthermore, it can be used not only as an IC chip but also as a wafer scale IC.

[Brief explanation of drawings]

Figure 1 shows a pre-wired GaAs film as an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a MESFET integrated circuit connected to a wired ECL integrated circuit using a solder bump method. Figure 2 is an overall diagram of the semiconductor device in Figure 1, in which a 4 x 4 mvs'' GaAs circuit is
FIG. 3, which shows a case in which an ECL circuit of 1.5 ugliness II2 is incorporated, is a detailed diagram of a case in which a GaAs IC chip is connected to a wafer scale IC as another embodiment of the present invention. FIG. 4 is a cross-sectional view of an embodiment in which the GaAs circuit has one-layer wiring, and the second and higher layers are formed on the silicon IC side. FIG. 5 shows an ECL optical integrated circuit as another embodiment of the present invention.
FIG. 2 is a side view of a semiconductor device incorporated into a circuit device and a bird's-eye view of an element. Explanation of symbols 1...Solder bump (Au), 2...Ponding pad, 3...Wiring (Au or Al), 4...
Insulating film (SiO2), 5... polycide electrode, wiring,
6... Gate electrode (WSix), 7... Ohmic electrode, 8... n-8L, 9-n''-S i,
1O-p--3i, 11-p''-8i, 12...
・Back metal, 13-n-GaAs, 14-n
"-GaAs, 15-semi-insulating GaAs substrate or buffer layer, 16... bonding pad (Ni,
or Mo), 17-GaAsIC chip-ECL circuit, 19...Si wafer, 20...printed board, 2
1... Plug-in socket, 22... Electrode (Au/P
t/Ti), 23-In bump, 24-n-InP
Substrate, 25-InGaAsP (active layer), 26-p-1
nP, 27-n-I nP, 28-... electrode (Ti),
29- n -I naaAs (active layer), 3 (1...
si, N.

Claims (1)

[Claims] 1. A first semiconductor device having a bipolar element and a second semiconductor device having an active layer made of a compound semiconductor are arranged facing each other, and the wiring of the first semiconductor device and the A composite semiconductor device characterized in that it is constructed by connecting wiring of a second semiconductor device with a low melting point metal. 2. Constructed by connecting the wiring of the first semiconductor device and the electrode of the second semiconductor device, or the electrode of the first semiconductor device and the wiring of the second semiconductor device with a low melting point metal. A composite semiconductor device according to claim 1, characterized in that: 3. The composite semiconductor device according to claims 1 and 2, wherein the second semiconductor device is a plurality of semiconductor devices. 4. The composite semiconductor device according to claims 1, 2, and 3, wherein the second semiconductor device is a semiconductor device having an active layer made of a compound semiconductor. 5. The composite semiconductor device according to claims 1, 2, 3, and 4, wherein the first semiconductor device is a silicon wafer incorporating a plurality of semiconductor devices.