JPH04117005A - Bias circuit - Google Patents
Bias circuitInfo
- Publication number
- JPH04117005A JPH04117005A JP2232111A JP23211190A JPH04117005A JP H04117005 A JPH04117005 A JP H04117005A JP 2232111 A JP2232111 A JP 2232111A JP 23211190 A JP23211190 A JP 23211190A JP H04117005 A JPH04117005 A JP H04117005A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- input terminal
- transistor
- inverting
- pnp
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
- Optical Communication System (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はバイアス回路に係り、特に光通信に用いられる
増幅器において光検知素子の次段に接続する前置増幅器
（プリアンプ）の入力端子のバイアス回路に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a bias circuit, and in particular to a bias circuit for the input terminal of a preamplifier (preamplifier) connected to the next stage of a photodetector element in an amplifier used for optical communication. Regarding circuits.
第２図に示す従来のプリアンプにおいて、非反転（＋）
入力端と反転（−）入力端とを有する差動増幅器ｌの出
力端と、ＰＮＰ ）ランジスタＱｌのベースとを接続し
、このＰＮＰ）ランジスタＱ１のコレクタを接地（ＧＮ
Ｄ）に接続し、ＰＮＰ）ランジスタＱ１のエミッタを抵
抗Ｒ１に接続し、抵抗Ｒ１の他端を抵抗Ｒ２と差動増幅
器１０反転入力端と定電流源工、に接続し、抵抗Ｒ２の
他端からコンデンサＣ１を介してＧＮＤに接続し、一方
非反転入力端を入力端子２とし、光検知素子Ｄ２を介し
てＧＮＤに接続し、差動増幅器１の出力端を出力端子３
とする非反転増幅器において、非反転増幅器の入力端子
２にＰＮＰ ）ランジスタＱ２のコレクタと抵抗Ｒ１と
を接続し、ＰＮＰトランジスタＱ、のベースを差動増幅
器１の反転入力端に接続し、ＰＮＰトランジスタＱ２の
エミッタを抵抗Ｒ５とＲ４に接続し、抵抗Ｒ４の他端は
ダイオードＤ１０カソード端を接続し、ダイオードＤ１
のアノード端は抵抗Ｒ６の他端と抵抗Ｒ１の他端と基準
電圧源ｖ１とを接続し、バイアス回路を構成している。In the conventional preamplifier shown in Figure 2, the non-inverting (+)
The output terminal of a differential amplifier l having an input terminal and an inverting (-) input terminal is connected to the base of a PNP) transistor Q1, and the collector of this PNP) transistor Q1 is connected to ground (GN).
D), connect the emitter of PNP transistor Q1 to resistor R1, connect the other end of resistor R1 to resistor R2, the inverting input terminal of differential amplifier 10, and the constant current source, and connect the other end of resistor R2 to is connected to GND via a capacitor C1, while the non-inverting input terminal is connected to input terminal 2, connected to GND via a photodetecting element D2, and the output terminal of differential amplifier 1 is connected to output terminal 3.
In a non-inverting amplifier, the collector of a PNP transistor Q2 and a resistor R1 are connected to the input terminal 2 of the non-inverting amplifier, the base of the PNP transistor Q is connected to the inverting input terminal of the differential amplifier 1, and the PNP transistor The emitter of Q2 is connected to resistors R5 and R4, the other end of resistor R4 is connected to the cathode end of diode D10, and the other end of resistor R4 is connected to the cathode end of diode D10.
The anode end of is connected to the other end of the resistor R6, the other end of the resistor R1, and the reference voltage source v1 to form a bias circuit.
従来この種のプリアンプは高い入力インピーダンスと高
い利得を必要とする非反転増幅器１を構成している。入
力端子２は、赤外線で動作する光検知素子Ｄ２が設けら
れている。抵抗Ｒ１は、非反転増幅器１の入力インピー
ダンスを決める抵抗で、５０にΩ程度の値が要求される
。Conventionally, this type of preamplifier constitutes a non-inverting amplifier 1 that requires high input impedance and high gain. The input terminal 2 is provided with a photodetecting element D2 that operates with infrared rays. The resistor R1 is a resistor that determines the input impedance of the non-inverting amplifier 1, and is required to have a value of about 50Ω.
光検知素子Ｄ２は、高光度の光信号あるいは信号以外の
波長で強い光を受けると、入力端子より５００μＡ以上
の電流を引く。以後、この強入力時の電流を、光検知素
子電流と記す。When the photodetector element D2 receives a high-intensity optical signal or strong light at a wavelength other than the signal, it draws a current of 500 μA or more from its input terminal. Hereinafter, the current at the time of this strong input will be referred to as a photodetector element current.
強入力時の光検知素子電流を抵抗Ｒ１を通してひっばる
と、抵抗Ｒ１に大きな電位差を作り、非反転増幅器の入
力端子電圧が低下し、非反転増幅の入力段が飽和するた
め、動作しなくなる。When the photodetecting element current at the time of strong input is drawn through the resistor R1, a large potential difference is created across the resistor R1, the input terminal voltage of the non-inverting amplifier is reduced, and the input stage of the non-inverting amplifier is saturated, so that it becomes inoperable.
そこで、ＰＮＰ ）ランジスタＱ２．抵抗Ｒ４１Ｒ５１
ダイオードＤ１から構成されるバイアス回路が、入力端
子２に接続されており、強入力時に光検知素子Ｄ２が入
力端子２より電流をひき、強入力時の光検知素子電流が
抵抗Ｒ１を流れることで、入力端子２の電位が下がり、
こうして入力端子２の電位が基準電圧源ｖ１の電位に対
し、Ｖｉ＋□以上下がると、強入力時の光検知素子電流
はＰＮＰ ）ランジスタＱ２と抵抗Ｒ５を通して基準電
圧源ｖ１より供給され、また入力端子２の電位がさらに
基準電圧源■１の電位に対し２倍のＶＢ８以上下がると
、強入力時の光検知素子電流はＰＮＰ）ランジスタＱ２
と抵抗Ｒ４とダイオードＤ、とを通しても供給されるよ
うになり、抵抗Ｒ１を通る電流が軽減し、入力端子２の
電位降下を防いでいる。Therefore, PNP) transistor Q2. Resistor R41R51
A bias circuit consisting of a diode D1 is connected to the input terminal 2, and the photodetector element D2 draws current from the input terminal 2 during strong input, and the photodetector current flows through the resistor R1 during the strong input. , the potential of input terminal 2 decreases,
In this way, when the potential of the input terminal 2 falls by more than Vi+□ with respect to the potential of the reference voltage source v1, the photodetecting element current during strong input is supplied from the reference voltage source v1 through the transistor Q2 and the resistor R5, and the input terminal When the potential of the reference voltage source 2 further decreases by VB8 or more, which is twice the potential of the reference voltage source 1, the photodetecting element current during strong input becomes PNP) transistor Q2.
The current is also supplied through the resistor R4 and the diode D, reducing the current passing through the resistor R1 and preventing a potential drop at the input terminal 2.
第２図に示したような従来のＰＮＰ ）ランジスタＱ
２ 、抵抗Ｒ，，Ｒ５，ダイオードＤ１よりなるバイア
ス回路は５００μ八以上の強入力時の光検知素子電流を
トランジスタＱ２のｈＦＥ分の−だけ抵抗Ｒ３に流し込
み、抵抗Ｒ３０両端の電位差を大きくする。非反転増幅
器は、特性上出力端子３のＤＣ電位を下げ、抵抗Ｒ３の
両端に発生した電位を吸収し、非反転入力端と反転入力
端のＤＣ電圧を合わせるが、抵抗Ｒ１の抵抗値が５０に
Ω以上にすると、抵抗Ｒ１の両端にＩＶ以上の電位差が
発生し、出力端子のＤＣレベル変動だけでは吸収できな
くなり、非反転入力端と反転入力端とのＤＣオフセット
が大きくなり、非反転増幅器は動作しなくなる。Conventional PNP transistor Q as shown in Figure 2
2. A bias circuit consisting of resistors R, , R5, and diode D1 causes the photodetector current at a strong input of 500 μ8 or more to flow into resistor R3 by the amount of hFE of transistor Q2, thereby increasing the potential difference across resistor R30. A non-inverting amplifier characteristically lowers the DC potential at the output terminal 3, absorbs the potential generated across the resistor R3, and matches the DC voltages at the non-inverting input terminal and the inverting input terminal, but if the resistance value of the resistor R1 is 50 If it is set to Ω or more, a potential difference of more than IV occurs across the resistor R1, which cannot be absorbed by DC level fluctuations at the output terminal alone, and the DC offset between the non-inverting input terminal and the inverting input terminal becomes large, causing the non-inverting amplifier to will no longer work.
従来、この種のプリアンプは、負帰還増幅器を構成して
おり、その利得Ｇは、次式■で示される。Conventionally, this type of preamplifier constitutes a negative feedback amplifier, and its gain G is expressed by the following equation (2).
前述した理由により、抵抗Ｒ３を大きくできず、またコ
ンデンサＣ１をチップ部品などを使用した場合、その容
量値をコスト上０．０１μＦ以上大きくできず、抵抗Ｒ
２は負帰還増幅器の利得の調整用に数百Ω程度必要なた
め、４５ｄＢ以上の利得Ｇは得られなかった。For the reasons mentioned above, the resistor R3 cannot be made large, and if a chip component or the like is used for the capacitor C1, the capacitance value cannot be increased by more than 0.01 μF due to cost, so the resistor R3 cannot be made large.
2 is required for adjusting the gain of the negative feedback amplifier, so a gain G of 45 dB or more could not be obtained.
本発明の目的は、前記欠点が解決され、容易に高利得が
得られるようにしたバイアス回路を提供することにある
。SUMMARY OF THE INVENTION An object of the present invention is to provide a bias circuit in which the above drawbacks are solved and a high gain can be easily obtained.
本発明のバイアス回路の構成は、非反転入力端と反転入
力端とを有する差動増幅器の出力端と第１のトランジス
タのベースとを接続し、前記第１のトランジスタのコレ
クタを定電位に接続し、前記第１のトランジスタのエミ
ッタを第１の抵抗の一端に接続し、前記第１の抵抗の他
端を第２の抵抗の一端と前記差動増幅器の反転入力端と
第１の定電流源とに接続し、前記第２の抵抗の他端から
コンデンサを介し、て前記定電位に接続し、前記非反転
入力端を入力端子とし、前記差動増幅器の出刃端を出力
端子とする非反転増幅器を設け、前記非反転増幅器の入
力端子にダイオードの一端と第３の抵抗の一端とを接続
し、前記ダイオードの他端を第２のトランジスタのコレ
クタに接続し、前記第２のトランジスタのエミッタを第
２の定電流源に接続し、前記第２のトランジスタのベー
スと前記第３の抵抗の他端とを基準電圧源に接続したこ
とを特徴とする。The configuration of the bias circuit of the present invention is such that the output terminal of a differential amplifier having a non-inverting input terminal and an inverting input terminal is connected to the base of a first transistor, and the collector of the first transistor is connected to a constant potential. The emitter of the first transistor is connected to one end of a first resistor, and the other end of the first resistor is connected to one end of a second resistor, the inverting input terminal of the differential amplifier, and a first constant current. the other end of the second resistor is connected to the constant potential via a capacitor, the non-inverting input terminal is the input terminal, and the edge end of the differential amplifier is the output terminal. An inverting amplifier is provided, one end of a diode and one end of a third resistor are connected to the input terminal of the non-inverting amplifier, the other end of the diode is connected to the collector of a second transistor, and The emitter is connected to a second constant current source, and the base of the second transistor and the other end of the third resistor are connected to a reference voltage source.
次に図面を参照しながら本発明を説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例のバイアス回路を示す回路図
である。FIG. 1 is a circuit diagram showing a bias circuit according to an embodiment of the present invention.
第１図において、本実施例のバイアス回路は、非反転（
＋）入力端と反転（−）入力端とを有する差動増幅器１
の出力端と、ＰＮＰ ｌ−ランジスタＱ、のベースとを
接続し、ＰＮＰ ）ランジスタＱ１のコレクタをＧＮＤ
に接続し、ＰＮＰＩ−ランジスタＱ１のエミッタを抵抗
Ｒ１の一端に接続し、抵抗Ｒ１の他端を、抵抗Ｒ２と差
動増幅器１の反転入力端と定電流源工、とに接続し、抵
抗Ｒ２の他端からコンデンサＣ１を介してＧＮＤに接続
して、非反転入力端を入力端子２とし、差動′増幅器ｌ
の出力端を出力端子３とする非反転増幅器を構成してい
る。In FIG. 1, the bias circuit of this embodiment has a non-inverting (
Differential amplifier 1 having a +) input terminal and an inverting (-) input terminal
Connect the output end of the PNP transistor Q1 to the base of the PNP transistor Q, and connect the collector of the PNP transistor Q1 to GND.
, connect the emitter of the PNPI transistor Q1 to one end of the resistor R1, connect the other end of the resistor R1 to the resistor R2, the inverting input terminal of the differential amplifier 1, and the constant current source, and connect the emitter of the resistor R2 to the resistor R2. The other end is connected to GND via the capacitor C1, the non-inverting input end is set as input terminal 2, and the differential amplifier l
This constitutes a non-inverting amplifier whose output terminal is the output terminal 3.
この入力端子２に、ダイオードＤ１のカソード端と抵抗
Ｒ１と光検知素子Ｄ２とを接続し、ダイオードＤ１のア
ノード端はエミッタが定電流源工２と接続しているＰＮ
Ｐ）ランジスタＱ２のコレクタト接続し、ＰＮＰ ）ラ
ンジスタＱ２のベースを抵抗Ｒ１の他端と基準電圧源ｖ
１とに接続し、非反転増幅器の入力端子２のバイアス回
路を構成している。The cathode end of the diode D1, the resistor R1, and the photodetector element D2 are connected to this input terminal 2, and the anode end of the diode D1 is a PN whose emitter is connected to the constant current source 2.
P) Connect the collector of transistor Q2 to the PNP) Connect the base of transistor Q2 to the other end of resistor R1 and the reference voltage source v
1 and constitutes a bias circuit for input terminal 2 of the non-inverting amplifier.
以上、バイアス回路の構成により、強入力時に光検知素
子Ｄ２が入力端子２より電流をひき、強入力時の光検知
素子電流が抵抗Ｒ１を流れることで、入力端子２の電位
が基準電圧源ｖ１より降下すると、ダイオードＤ、とＰ
ＮＰ ）ランジスタＱ２とを通し、定電流源工２より強
入力時の光検知素子電流は供給され、抵抗Ｒ１に流れる
電流を軽減し、入力端子２の電位降下を防いでいる。As described above, with the configuration of the bias circuit, the photodetecting element D2 draws current from the input terminal 2 during strong input, and the photodetecting element current flows through the resistor R1 during the strong input, so that the potential of the input terminal 2 changes to the reference voltage source v1. When descending further, diodes D and P
NP) transistor Q2, the photodetecting element current at the time of strong input is supplied from the constant current source 2, reducing the current flowing through the resistor R1 and preventing a potential drop at the input terminal 2.
このように、本実施例のバイアス回路は、非反転増幅器
の帰還ラインである抵抗Ｒ２，Ｒ，、ＰＮＰトランジス
タＱ ＋ 、コンデンサＣ１ヘバイアス回路が接続され
ていないため、強入力時の光検知素子電流は、ＰＮＰ）
ランジスタＱ２１ ダイオードＤ１介して定電流源工、
より供給される。ＰＮＰ ）ランジスタＱ２のベース電
流は基準電圧源へ流れ込むので、抵抗Ｒ３へはいっさい
流れ込まない。As described above, in the bias circuit of this embodiment, since the bias circuit is not connected to the feedback line of the non-inverting amplifier, ie, the resistors R2, R, PNP transistor Q + , and capacitor C1, the photodetecting element current at the time of strong input is is PNP)
Constant current source via transistor Q21 diode D1,
Supplied by Since the base current of transistor Q2 (PNP) flows into the reference voltage source, it does not flow into resistor R3 at all.
このため、抵抗Ｒ１の値を自由に選べる。非反転帰還増
幅器の利得は、前記式■によって決まり、抵抗Ｒ３を大
きな値にすることで、非反転帰還増幅器の利得は大きく
できる。Therefore, the value of the resistor R1 can be freely selected. The gain of the non-inverting feedback amplifier is determined by the above equation (2), and by setting the resistor R3 to a large value, the gain of the non-inverting feedback amplifier can be increased.
〔発明の効果〕
以上説明したように、本発明は、第１の抵抗の値が自由
に選べるから、高利得が確保できるという効果がある。[Effects of the Invention] As explained above, the present invention has the advantage that a high gain can be ensured because the value of the first resistor can be freely selected.
略図である。This is a schematic diagram.
１・・・・・・差動増幅器、１１・・・・・・第１の定
電流源、工２・・・・・・第２の定電流源、Ｑ １．
Ｑ ２・・・・・・ＰＮＰ ）ランジスタ、Ｄｌ・・・
・・・ダイオード、Ｄ２・・・・・・光検知素子、Ｒ１
・・・・・・バイアス抵抗、Ｒｔ 、 Ｒｓ・・・・・
・非反転増幅器の帰還抵抗、Ｒ，、Ｒ５・・・・・・バ
イアス回路の抵抗、Ｃ１・・・・・・コンデンサ、■ビ
・・・・・基準電圧源、２・・・・・・入力端子、３・
・・・・・出力端子。1... Differential amplifier, 11... First constant current source, 2... Second constant current source, Q 1.
Q2...PNP) transistor, Dl...
...Diode, D2...Photodetection element, R1
...Bias resistance, Rt, Rs...
・Feedback resistance of non-inverting amplifier, R5...Resistance of bias circuit, C1...Capacitor, ■Bi...Reference voltage source, 2... Input terminal, 3.
...Output terminal.
代理人 弁理士 内 原 晋Agent: Patent Attorney Susumu Uchihara
Claims (1)
端と第１のトランジスタのベースとを接続し、前記第１
のトランジスタのコレクタを定電位に接続し、前記第１
のトランジスタのエミッタを第１の抵抗の一端に接続し
、前記第１の抵抗の他端を第２の抵抗の一端と前記差動
増幅器の反転入力端と第１の定電流源とに接続し、前記
第２の抵抗の他端からコンデンサを介して前記定電位に
接続し、前記非反転入力端を入力端子とし、前記差動増
幅器の出力端を出力端子とする非反転増幅器を設け、前
記非反転増幅器の入力端子にダイオードの一端と第３の
抵抗の一端とを接続し、前記ダイオードの他端を第２の
トランジスタのコレクタに接続し、前記第２のトランジ
スタのエミッタを第２の定電流源に接続し、前記第２の
トランジスタのベースと前記第３の抵抗の他端とを基準
電圧源に接続したことを特徴とするバイアス回路。An output terminal of a differential amplifier having a non-inverting input terminal and an inverting input terminal is connected to the base of the first transistor, and the first
The collector of the transistor is connected to a constant potential, and the collector of the first transistor is connected to a constant potential.
The emitter of the transistor is connected to one end of a first resistor, and the other end of the first resistor is connected to one end of a second resistor, an inverting input terminal of the differential amplifier, and a first constant current source. , a non-inverting amplifier is connected from the other end of the second resistor to the constant potential via a capacitor, the non-inverting input terminal is an input terminal, and the output terminal of the differential amplifier is an output terminal; One end of a diode and one end of a third resistor are connected to the input terminal of the non-inverting amplifier, the other end of the diode is connected to the collector of a second transistor, and the emitter of the second transistor is connected to a second resistor. A bias circuit characterized in that the bias circuit is connected to a current source, and the base of the second transistor and the other end of the third resistor are connected to a reference voltage source.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2232111A JPH04117005A (en) | 1990-08-31 | 1990-08-31 | Bias circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2232111A JPH04117005A (en) | 1990-08-31 | 1990-08-31 | Bias circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04117005A true JPH04117005A (en) | 1992-04-17 |
Family
ID=16934181
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2232111A Pending JPH04117005A (en) | 1990-08-31 | 1990-08-31 | Bias circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04117005A (en) |
-
1990
- 1990-08-31 JP JP2232111A patent/JPH04117005A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4327319A (en) | Active power supply ripple filter | |
| US4410859A (en) | Signal amplifier circuit arrangement with output current limiting function | |
| JP2003087061A (en) | Constant voltage circuit and infrared remote control receiver using the same | |
| US4731529A (en) | Light measuring circuit having circuitry for bypassing a low frequency component in the output of a photoelectric conversion element | |
| JPH0770935B2 (en) | Differential current amplifier circuit | |
| US5155429A (en) | Threshold voltage generating circuit | |
| US4017749A (en) | Transistor circuit including source voltage ripple removal | |
| EP0460273A1 (en) | Gain stabilizing amplifier | |
| EP0508711B1 (en) | Transistor direct-coupled amplifier | |
| JP3419546B2 (en) | Forward type transimpedance circuit | |
| JPH04369907A (en) | High frequency amplifier circuit | |
| JP2546912B2 (en) | AC amplifier | |
| JPH0413692Y2 (en) | ||
| JP2818205B2 (en) | Wide dynamic optical receiver circuit | |
| JP3256404B2 (en) | Light receiving amplifier | |
| JPH0326331B2 (en) | ||
| JPH062337Y2 (en) | ALC circuit | |
| KR100208666B1 (en) | Automatic gain control circuit | |
| JPH0442846B2 (en) | ||
| JPH0371813B2 (en) | ||
| JPH04259105A (en) | Amplifier circuit | |
| JPH0573086B2 (en) | ||
| JPS624886B2 (en) | ||
| JPH08256030A (en) | Automatic control circuit | |
| JPS6043684B2 (en) | limiter circuit |