JPH04118965A - Analog memory element and control circuit - Google Patents

Abstract

PURPOSE:To easily, efficiently, and finely adjust the charge quantity of a floating electrode with high accuracy by successively piling up a bias controlling gate electrode and pulse controlling gate electrode on a floating gate. CONSTITUTION:The potential of a floating gate 1 is adjusted to a fixed value by applying a voltage across a bias controlling gate 6. Then, a pulse voltage is induced across the bias controlling electrode 6 and floating gate 1 by impressing a voltage pulse upon a pulse controlling gate 7 and electric charges are injected into the gate 1 through a tunnel junction 3. However, high resistances are equivalently connected in series in advance between an external circuit joined to the gate 6 and voltage source so that a pulse voltage can be induced across the electrode 6. When a fixed pulse is impressed in a state where the potential at the floating gate is controlled to a fixed value, the injected charge quantity always becomes a fixed value. Since a fixed quantity of electric charges is always injected against the fixed potential pulse by performing bias control on the potential of the floating gate 1, the injected charge quantity can be adjusted easily little by little with high accuracy.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to an analog memory element that stores the amount of accumulated charge as an analog amount, and an element that can easily increase or decrease the amount of charge in small increments. Regarding control circuits.

(Prior Art) There have been many cases where it is necessary to store analog signal amounts on an LSI. For example, storage of audio or image signals, or storage of weighting coefficients for neural circuits are typical examples. However, in the past, there were no semiconductor devices that could be used to store accurate analog quantities. Therefore, when analog storage is required, there is no choice but to first digitize it and store each bit in a digital memory, resulting in an increase in the number of memory devices and an increase in the occupied area.

Therefore, it has been desired to develop a memory element that can directly store analog signal amounts. The most likely conventional device is a so-called floating gate MOS transistor, which performs analog storage using the amount of charge accumulated in a gate that is electrically isolated from the surroundings. However, this floating gate MO3) transistor is not suitable for accurate analog storage as it is; in other words, in conventional floating gate MOS transistors, a voltage pulse is applied to the floating gate to inject charge from the tunnel junction to the floating gate. In this case, the amount of charge injected depends largely on the amount of charge already stored in the floating gate and the height and width of the applied voltage pulse, so it is difficult to accurately set and store an arbitrary analog amount. It wasn't easy. This problem will be briefly explained below using a diagram.

(Policy II to be Solved by the Invention) Figure 5 shows the structure of a conventional floating gate MOS transistor. In Figure 0, 1 is a floating gate, 2 is a control gate, and 3 is a floating gate.
is a tunnel junction, 4 is a drain, and 5 is a source. In this device, when a voltage for charge injection is applied to the control gate 2, a high electric field is applied to the electron barrier of the tunnel junction 3, and as a result, the drain 4 is connected through the tunnel junction 3. and floating gate 1
A tunnel current flows between them, and charges are injected into the floating gate 1-1. A constant pulse voltage (
Figure 6 shows the time change in the amount of charge injected into floating gate 1 when a positive voltage pulse (writing: positive voltage pulse, erasing: negative voltage pulse) is applied repeatedly.As the charge is injected, the potential of floating gate 1 changes. However, the voltage applied to the tunnel junction decreases, the tunnel current stops flowing, and an equilibrium state is reached. That is, the amount of charge injected differs depending on the amount of charge already stored in the floating gate 1. Conversely, in order to inject a certain amount of charge, it is necessary to measure the amount of charge stored in the floating gate 1, and then apply a pulse with a different voltage and width depending on that value. Moreover, complicated planning is required to obtain the pulse voltage and width values for this purpose.

Thus, it has not been easy to control the amount of charge on the floating gate l.

The present invention was proposed to improve the above-mentioned drawbacks, and its purpose is to provide a pulse control gate structure that solves the difficulty of minutely and efficiently adjusting the amount of charge accumulated in a floating gate. An object of the present invention is to provide an analog memory device having the following features and a control circuit thereof.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides a bias potential in a transistor memory element (MOS) having a floating gate arranged through a tunnel junction with respect to a source and a drain. The gist of the invention is an analog memory element characterized in that a bias control gate electrode and a pulse control gate electrode for applying a pulse voltage are formed by stacking them on the floating gate.

Furthermore, the present invention provides an analog memory element in which a bias control gate electrode for applying a bias potential and a pulse control gate electrode for applying a pulse voltage are stacked on the floating gate to control the drain current or voltage to a desired value. The gist of the invention is an analog memory element control circuit characterized in that a gate bias generation circuit for maintaining the voltage is connected to a bias control gate and a control pulse is applied to the pulse control gate.

(Function) The present invention provides a MOS transistor memory element having a floating gate, which is provided with a bias control gate electrode that applies a bias potential to the floating gate and a pulse control gate electrode that applies a pulse voltage. During injection, the amount of floating gate charge can be adjusted with high precision simply by applying a control voltage pulse.

(Example of Actual Rights) Next, an example of the present invention will be described. It should be noted that the examples are merely illustrative, and within the scope of the spirit of the present invention,
It goes without saying that various changes and improvements can be made.

FIG. 1 shows an embodiment of the analog memory device of the present invention.
In the figure, 1 is a floating gate, 6 is a bias control gate,
7 is a pulse control gate, 8 is an oxide film, 4 is a drain,
Reference numeral 5 indicates a gate, which is formed by stacking a bias control gate 6 and a pulse control gate 7 on the floating gate 1.

Next, the operation of the analog memory device of the present invention will be explained.

First, a voltage is applied to the bias control gate 6 and the floating gate 1
A voltage pulse is applied to the zero-order pulse control gate 7, which induces a pulse voltage in the bias control electrode 6 and the floating gate 1, and charges are transferred through the tunnel junction 3. is injected into floating gate 1. However, in order to induce a pulse voltage in the bias control gate electrode 6 at this time, a high resistance is equivalently connected in series with the voltage source in the external circuit coupled to the bias control gate 6. (Figure 3), when a constant pulse is applied while the floating gate potential is controlled to a constant value, the amount of charge injected is always constant.

As described above, according to the analog memory element of the present invention, by controlling the bias of the floating gate potential 1, a constant amount of charge is always injected in response to a constant voltage pulse, so that the amount of injected charge can be controlled. It is easy to accurately adjust small amounts.

A second embodiment of the analog memory device of the present invention is shown in FIG. This embodiment differs from the first embodiment in that the high resistance layer 9 connected in series to the bias control gate electrode is formed as an integral structure. This high resistance layer 9 is intended to reduce the capacitive load of the pulse control gate 7 to the voltage pulse and to ensure that the pulse voltage is sufficiently induced. A similar effect can also be obtained by increasing the time constant of the bias control circuit and suppressing fluctuations and oscillations in the bias control circuit caused by pulse application, and by forming the entire bias control gate electrode with a high-resistance layer. It will be done.

Next, a control circuit for the bias control gate of the analog memory element will be explained. This control circuit is a circuit that controls the voltage of the bias control gate in order to maintain the potential of the floating gate at a certain constant value.

FIG. 3 shows a control circuit of the present invention. A source/drain current/voltage measuring circuit 10 measures the source/drain current or voltage of a MOS transistor.

The gate bias voltage generation circuit 11 compares the source/drain current or voltage with a fixed target value and changes the output voltage, that is, the gate voltage in a direction in which the source/drain current or voltage approaches the fixed target value. In the case of an n-channel MOS transistor, when the source-drain current is smaller than a target value, the source-drain current is increased by increasing the output voltage and raising the gate voltage. Conversely, when it is larger than the target value, the output voltage is lowered and the gate voltage is lowered to reduce the source-drain current. In the case of a p-channel MOS transistor, the increase and decrease are reversed.

A high resistance is equivalently connected in series with the bias control gate electrode (or the output of the gate bias voltage generation circuit is made high impedance. This suppresses the oscillation phenomenon in the feedback control circuit of the bias control gate. can do.

When the voltage of the bias control gate 6 is controlled to maintain the source/drain current or voltage at a certain value, the MOS
) The electric field applied to the channel region of the transistor is held at a certain value. That is, the potential of the floating gate 1 is controlled to be approximately equal to a certain constant value. After this state is established, by applying a voltage pulse to the pulse control gate 7, the amount of charge injected can be kept almost constant regardless of the amount of charge stored in the floating gate. −
The amount of charge injected with each pulse can be adjusted by changing the pulse width, and by shortening the pulse width, the amount of change can be made minute. When a constant pulse voltage for charge injection (writing: positive voltage pulse, erasing: negative voltage pulse) is repeatedly applied to the control gate, the amount of charge injected into the floating gate changes over time almost linearly as shown in Figure 4. become a target.

In FIG. 4, the horizontal axis represents the pulse application circuit, and the vertical axis represents the amount of charge on the floating gate.

As described above, if write/erase control is performed using the control circuit of the present invention, it is easy to arbitrarily set and memorize an analog quantity with a certain precision by repeatedly applying a certain voltage pulse. Can be done. As the memory output, the gate bias voltage in the operating state of the present control circuit may be used, or the drain voltage or drain current when the gate bias voltage is fixed at a specific value may be used.

(Effects of the Invention) As described above, according to the present invention, in a MOS transistor memory element having a floating gate, a bias control gate electrode for applying a bias potential and a pulse control gate electrode for applying a pulse voltage are connected to the floating gate. By stacking the layer on top of the floating gate, the amount of charge on the floating electrode can be easily and efficiently adjusted minutely and with high precision by simply applying a constant control voltage pulse when injecting charge into the floating gate. .

Therefore, if the analog memory device of the present invention is used to store synaptic loads in the synaptic circuits of a neural network, the so-called learning function that gradually increases or decreases the synaptic loads to converge on the optimal synaptic loads can be performed using simple pulse control. This method can be easily realized by using the method, and has the effect of creating a neurochip with learning ability.

[Brief explanation of the drawing]

Figure 1 is a basic structural diagram (first embodiment) of the floating gate type MO3FET of the present invention, and Figure 2 is the floating gate type MO3FET of the present invention.
Embodiment 2 of the O3FET, FIG. 3 is a control circuit diagram of the floating gate type MO5FET of the present invention, and FIG. 4 is a schematic diagram of the temporal change in the amount of injected charge when a constant pulse is repeatedly applied to the floating gate of the present invention. Figure 5 shows the conventional floating gate type M
FIG. 6, which is a structural diagram of an O3FT, is a schematic diagram of the temporal change in the amount of charge injected when a constant pulse is repeatedly applied to a floating gate of a conventional structure. 1... Floating gate 2... Control gate 3... Tunnel oxide film 4... Drain 5... Source 6... Bias control gate 7... Pulse control gate 8... Oxide film 9 ...High resistance layer 10...Drain current and voltage measurement circuit 11...Gate bias voltage generation circuit

Claims (2)

[Claims] (1) In a MOS transistor memory element having a floating gate arranged through a tunnel junction with respect to the source and drain, a bias control gate electrode that applies a bias potential and a pulse control gate electrode that applies a pulse voltage are connected to the floating gate. An analog memory element characterized in that it is formed by stacking it on a gate. (2) Maintain the drain current or voltage at a desired value for an analog memory element formed by stacking a bias control gate electrode that applies a bias potential and a pulse control gate electrode that applies a pulse voltage on the floating gate. 1. An analog memory element control circuit, characterized in that a gate bias generation circuit for this purpose is connected to a bias control gate, and a control pulse is applied to the pulse control gate.