JPH0412014U - - Google Patents

Info

Publication number
JPH0412014U
JPH0412014U JP1990053187U JP5318790U JPH0412014U JP H0412014 U JPH0412014 U JP H0412014U JP 1990053187 U JP1990053187 U JP 1990053187U JP 5318790 U JP5318790 U JP 5318790U JP H0412014 U JPH0412014 U JP H0412014U
Authority
JP
Japan
Prior art keywords
data
memory element
integrated circuit
semiconductor integrated
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990053187U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990053187U priority Critical patent/JPH0412014U/ja
Publication of JPH0412014U publication Critical patent/JPH0412014U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Bipolar Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案に係る半導体集積回路装置の一
実施例を示す回路図、第2図乃至第4図は第1図
の回路構成を組込んだ半導体集積回路装置の外観
の三例を示す各斜視図である。 10……記憶素子、11a,11b…12……
データバス及び書込みパルス用端子、13……D
/A変換素子。
FIG. 1 is a circuit diagram showing one embodiment of a semiconductor integrated circuit device according to the present invention, and FIGS. 2 to 4 show three examples of external appearances of semiconductor integrated circuit devices incorporating the circuit configuration of FIG. 1. FIG. 3 is a perspective view. 10... Memory element, 11a, 11b...12...
Data bus and write pulse terminals, 13...D
/A conversion element.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 所望のデータを書込み及び消去し得る記憶素子
と、その記憶素子のデジタル出力をアナログ変換
するD/A変換素子とを内蔵し、上記記憶素子に
データを任意に書込むデータバス及び書込みパル
ス用端子を有し、上記端子から入力されて記憶素
子に保持したデータに基づいて所望の出力レベル
を設定可能にしたことを特徴とする半導体集積回
路装置。
A data bus and write pulse terminal that includes a memory element in which desired data can be written and erased, and a D/A conversion element that converts the digital output of the memory element into analog, and a data bus and write pulse terminal for arbitrarily writing data into the memory element. 1. A semiconductor integrated circuit device comprising: a semiconductor integrated circuit device, wherein a desired output level can be set based on data input from the terminal and held in a storage element.
JP1990053187U 1990-05-21 1990-05-21 Pending JPH0412014U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990053187U JPH0412014U (en) 1990-05-21 1990-05-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990053187U JPH0412014U (en) 1990-05-21 1990-05-21

Publications (1)

Publication Number Publication Date
JPH0412014U true JPH0412014U (en) 1992-01-31

Family

ID=31574157

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990053187U Pending JPH0412014U (en) 1990-05-21 1990-05-21

Country Status (1)

Country Link
JP (1) JPH0412014U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5786917A (en) * 1980-11-20 1982-05-31 Nec Corp Direct-current stabilized power source device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5786917A (en) * 1980-11-20 1982-05-31 Nec Corp Direct-current stabilized power source device

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