JPH0412030B2 - - Google Patents
Info
- Publication number
- JPH0412030B2 JPH0412030B2 JP56069182A JP6918281A JPH0412030B2 JP H0412030 B2 JPH0412030 B2 JP H0412030B2 JP 56069182 A JP56069182 A JP 56069182A JP 6918281 A JP6918281 A JP 6918281A JP H0412030 B2 JPH0412030 B2 JP H0412030B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- transistor
- diode
- collector
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
Landscapes
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明はトランジスタ、特に保護ダイオードを
有するトランジスタの改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in transistors, particularly transistors with protection diodes.
トランジスタを保護するために第１図に示す如
く、トランジスタのベース・コレクタ間に保護ダ
イオードを接続することが知られている。この保
護ダイオードはトランジスタの二次破壊電圧より
も低いツエナー電圧に設定される。 In order to protect a transistor, it is known to connect a protection diode between the base and collector of the transistor, as shown in FIG. This protection diode is set to a Zener voltage lower than the secondary breakdown voltage of the transistor.
第２図に第１図の回路を集積化したトランジス
タ構造を示す。１はＮ型シリコン半導体基板であ
り、N-型コレクタ領域２とN+型コレクタコンタ
クト領域３より構成され、４はＰ型ベース領域、
５はＮ型エミツタ領域、６はＰ型ダイオード領
域、７はＮ型のガード領域、８，９，１０はコレ
クタ、ベースおよびエミツタ電極である。 FIG. 2 shows a transistor structure in which the circuit of FIG. 1 is integrated. 1 is an N-type silicon semiconductor substrate, which is composed of an N - type collector region 2 and an N + type collector contact region 3; 4 is a P-type base region;
5 is an N-type emitter region, 6 is a P-type diode region, 7 is an N-type guard region, and 8, 9, and 10 are collector, base, and emitter electrodes.
斯上の構造に於いて、ダイオード領域６はベー
ス領域４より一定距離Ｌだけ離間して設けられ、
この距離Ｌで決められるパンチスルー電圧が保護
動作電圧として働く。しかしながら点線で示す空
乏層１１がダイオード領域６に達するパンチスル
ー時においてベース領域４とダイオード領域６間
のインピーダンスRzは約1KΩ（第５図左端）と高
いために、コレクタ電流が増大すると第６図に一
点鎖線で示す如く保護動作電圧の特性の傾きがゆ
るやかになり、実線で示すトランジスタの二次破
壊電圧より大きくなり保護されない領域が存在す
る。 In the above structure, the diode region 6 is provided at a certain distance L from the base region 4,
The punch-through voltage determined by this distance L functions as the protection operating voltage. However, when the depletion layer 11 shown by the dotted line reaches the diode region 6 during punch-through, the impedance Rz between the base region 4 and the diode region 6 is as high as approximately 1KΩ (the left end in FIG. 5), so when the collector current increases, As shown by the dashed line, the slope of the characteristic of the protection operating voltage becomes gentle, and there is a region where the voltage becomes higher than the secondary breakdown voltage of the transistor and is not protected, as shown by the solid line.
本発明は斯点に鑑みてなされ従来の欠点を完全
に除去したトランジスタを実現するものである。
以下に第３図乃至第６図を参照して本発明の一実
施例を詳述する。 The present invention has been made in view of this point, and is an object of realizing a transistor completely eliminating the conventional drawbacks.
An embodiment of the present invention will be described in detail below with reference to FIGS. 3 to 6.
本発明によるトランジスタは第３図の如く、
N-型コレクタ領域２１とN+型コレクタコンタク
ト領域２２より成るシリコン半導体基板２０と、
コレクタ領域２１表面に二重拡散して形成された
Ｐ型ベース領域２３およびＮ型エミツタ領域２４
と、ベース領域２３より一定距離離間してコレク
タ領域２１表面に設けられたＰ型ダイオード領域
２５と、ベース領域２３に近接してコレクタ領域
２１表面に形成されたＰ型付加領域２６と、コレ
クタ領域２１表面の周端に設けられたＮ型ガード
領域２７と、コレクタコンタクト領域２２ベース
領域２３およびエミツタ領域２４に夫々オーミツ
ク接触するコレクタ電極２８ベース電極２９およ
びエミツタ電極３０と、ダイオード領域２５とガ
ード領域２７とを接続する接続電極３１より構成
される。 The transistor according to the present invention is as shown in FIG.
A silicon semiconductor substrate 20 comprising an N − type collector region 21 and an N + type collector contact region 22;
P-type base region 23 and N-type emitter region 24 formed by double diffusion on the surface of collector region 21
a P-type diode region 25 provided on the surface of the collector region 21 at a certain distance from the base region 23; a P-type additional region 26 formed on the surface of the collector region 21 close to the base region 23; 21, an N-type guard region 27 provided at the peripheral edge of the surface, a collector electrode 28, a base electrode 29 and an emitter electrode 30, which are in ohmic contact with the collector contact region 22, the base region 23, and the emitter region 24, respectively, the diode region 25, and the guard region. It is composed of a connecting electrode 31 that connects to 27.
本発明のトランジスタの最大の特徴は付加領域
２６にあり、付加領域２６とベース領域２３とそ
の間のコレクタ領域２１によつてラテラル型のト
ランジスタを形成することにある。従つて本発明
の構造の等価回路図は第４図の如くなり、ダイオ
ードに直列にラテラル型PNPトランジスタが挿
入される。 The greatest feature of the transistor of the present invention lies in the additional region 26, in that the additional region 26, the base region 23, and the collector region 21 therebetween form a lateral type transistor. Therefore, the equivalent circuit diagram of the structure of the present invention is as shown in FIG. 4, in which a lateral type PNP transistor is inserted in series with the diode.
斯上の構造に依ればラテラル型PNPトランジ
スタのトランジスタ作用によりパンチスルー時の
ベース電流を増大できるので、保護動作時におけ
るベース領域２３およびダイオード領域２５間の
インピーダンスPzが従来より大巾に低減できる。
第５図にコレクタ領域２１を4.7Ωcmとし、ラテ
ラル型トランジスタのベース巾を５〜20μ間で変
化させて、ラテラル型PNPトランジスタのhFEと
Rzとの相関を表わす特性図を示す。これに依れ
ばhFEを２以上に設定すればRzを従来より半減で
きることが明らかである。製造上の制約および効
果の程度からhFEを２〜10程度に設定するのが最
も好ましい。 According to the above structure, the base current during punch-through can be increased due to the transistor action of the lateral type PNP transistor, so that the impedance Pz between the base region 23 and the diode region 25 during the protection operation can be reduced to a greater extent than before. .
In Figure 5, the collector region 21 is set to 4.7Ωcm, the base width of the lateral type transistor is varied between 5 and 20μ, and the hFE and hFE of the lateral type PNP transistor are
A characteristic diagram showing the correlation with Rz is shown. According to this, it is clear that by setting h FE to 2 or more, Rz can be halved compared to the conventional one. It is most preferable to set h FE to about 2 to 10 in view of manufacturing constraints and the degree of effectiveness.
上述の様にRzを低減できる結果ダイオードに
よる保護動作電圧は第６図に点線で示す如く、そ
の傾きを急峻でき、実線で示すトランジスタの二
次破壊電圧特性より常に小さく設定できる。これ
により本発明ではいかなる領域でも保護可能とな
つた。なお保護動作電圧は付加領域２６とダイオ
ード領域２５間の離間距離L′で決められるパンチ
スルー電圧となる。 As a result of being able to reduce Rz as described above, the slope of the protective operating voltage of the diode can be made steeper, as shown by the dotted line in FIG. 6, and can always be set lower than the secondary breakdown voltage characteristic of the transistor, shown by the solid line. This allows the present invention to protect any area. Note that the protection operating voltage is a punch-through voltage determined by the distance L' between the additional region 26 and the diode region 25.
以上に詳述した如く本発明に依れば付加領域に
よるラテラル型PNPトランジスタの作用により
その保護動作電圧を電流の大小にかかわらず一定
に維持できるのである。この結果従来では狭い範
囲での保護動作電圧の実現は外付けのツエナーダ
イオードで行つていたのが、本発明によりトラン
ジスタ自身で実現できた。 As described in detail above, according to the present invention, the protective operating voltage can be maintained constant regardless of the magnitude of the current due to the action of the lateral type PNP transistor by the additional region. As a result, the protection operating voltage within a narrow range was conventionally achieved using an external Zener diode, but with the present invention, it can be achieved using the transistor itself.
第１図は保護ダイオードを有するトランジスタ
の回路図、第２図は従来のトランジスタ構造を説
明する断面図、第３図は本発明によるトランジス
タの構造を説明する断面図、第４図は第３図の等
価回路図、第５図および第６図は本発明のトラン
ジスタの動作を説明するための特性図である。
主な図番の説明、２０……半導体基板、２１…
…コレクタ領域、２３……ベース領域、２４……
エミツタ領域、２５……ダイオード領域、２６…
…付加領域である。
FIG. 1 is a circuit diagram of a transistor having a protection diode, FIG. 2 is a cross-sectional view explaining a conventional transistor structure, FIG. 3 is a cross-sectional view explaining the structure of a transistor according to the present invention, and FIG. 5 and 6 are characteristic diagrams for explaining the operation of the transistor of the present invention. Explanation of main drawing numbers, 20...Semiconductor substrate, 21...
...Collector area, 23...Base area, 24...
Emitter region, 25...Diode region, 26...
...This is an additional area.
Claims (1)
に形成された逆導電型のベース領域とこのベース
領域に形成された一導電型のエミツタ領域とを有
したトランジスタと、 前記コレクタ領域に形成された逆導電型のダイ
オード領域で少なくとも構成される保護ダイオー
ドと、 前記ダイオード領域と前記ベース領域との間に
形成された逆導電型の付加領域と前記ベース領域
および前記コレクタ領域とで構成されるラテラル
型トランジスタとを備え、 前記ラテラル型トランジスタは、前記保護ダイ
オードのパンチスルー時に前記トランジスタのベ
ース電流を増大させることを特徴としたトランジ
スタ。 ２ 特許請求の範囲の第１項において、前記ラテ
ラル型トランジスタの電流増幅率を２〜10に設定
したことを特徴とするトランジスタ。[Scope of Claims] 1. A transistor having a collector region of one conductivity type, a base region of an opposite conductivity type formed in this collector region, and an emitter region of one conductivity type formed in this base region, and the collector. a protection diode comprising at least a diode region of opposite conductivity type formed in the diode region; an additional region of opposite conductivity type formed between the diode region and the base region; and the base region and the collector region. and a lateral type transistor configured to increase a base current of the transistor during punch-through of the protection diode. 2. The transistor according to claim 1, wherein the lateral transistor has a current amplification factor of 2 to 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56069182A JPS57183066A (en) | 1981-05-07 | 1981-05-07 | Transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56069182A JPS57183066A (en) | 1981-05-07 | 1981-05-07 | Transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57183066A JPS57183066A (en) | 1982-11-11 |
| JPH0412030B2 true JPH0412030B2 (en) | 1992-03-03 |
Family
ID=13395319
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56069182A Granted JPS57183066A (en) | 1981-05-07 | 1981-05-07 | Transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57183066A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH069208B2 (en) * | 1987-02-27 | 1994-02-02 | ロ−ム株式会社 | Semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5739059B2 (en) * | 1972-04-28 | 1982-08-19 |
-
1981
- 1981-05-07 JP JP56069182A patent/JPS57183066A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57183066A (en) | 1982-11-11 |
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