JPH0412031B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device in which a circuit element in which a diode is inserted between the emitter and base of a first stage transistor is formed in a single semiconductor substrate in a so-called Darlington connection circuit device.

FIG. 1 shows a circuit of a conventional device in which two transistors Tr ₁ and Tr ₂ are connected in Darlington.
The base terminal B is connected to the base electrode of the first stage transistor Tr ₁ , and the emitter electrode of this transistor Tr ₁ is further connected to the base electrode of the second stage transistor Tr ₂ . Further, the emitter terminal E is connected to the emitter electrode of the second stage transistor Tr ₂ , and the collector terminal C is connected to the emitter electrode of the second stage transistor Tr 2.
Connected to the collector electrodes of Tr ₁ and Tr ₂ .

Note that R ₁ is the base of the first stage transistor Tr ₁ .
The emitter-to-emitter resistance, R ₂ , is the second stage transistor Tr ₂
The base-emitter resistance _D1 is the emitter-collector diode of the second stage transistor _Tr2 .

FIG. 2 is a sectional view of the Darlington connection circuit constructed on, for example, a silicon wafer. The first stage transistor Tr ₁ includes an N-type diffusion region 3,
Consists of a P-type diffusion region 2 and an N-type silicon substrate 1
In the NPN transistor, above the N-type diffusion region 3 there is an internal wiring 9 which becomes the emitter electrode of the first stage transistor Tr ₁ and the base electrode of the second stage transistor Tr ₂ , and above the P-type diffusion region 2 there is the base electrode. An electrode 8 is formed. On the other hand, the second stage transistor
Tr ₂ consists of an N-type diffusion region 4, a P-type diffusion region 2, and an N-type silicon substrate 1, and an emitter electrode 10 is formed on the N-type diffusion region 4. Also, resistance
R ₁ is formed in the resistance region 5, resistance R ₂ is formed in the resistance region 6, and the diode D ₁ is formed in the P-type diffusion region 2,
It is formed in a PN junction portion 7 made of an N-type silicon substrate 1. Further, 11 is a collector electrode, 12
is an insulating film.

In the conventional Darlington connection circuit configured in this way, when the base and emitter are reverse biased during switching from ON to OFF, the first stage transistor Tr _{1 becomes OFF state, and the first stage transistor Tr 1} turns OFF. Since no current flows between the base and emitter of Tr ₁ , the carriers accumulated in the base region of the second stage transistor Tr ₂ are gradually discharged to the base electrode of the first stage transistor Tr ₁ through the resistor R ₁ . Just do it. Resistance R ₁
When the resistance value of
It remains in the base region of stage transistor Tr ₂ . As a result, the switching speed becomes slow. In order to improve the above drawbacks, a method is known in which a diode _D2 is inserted between the emitter and base of the first stage transistor _Tr1 , as shown in FIG.

However, it is very difficult to fabricate this diode D ₂ integrally in a single semiconductor substrate like other circuit elements because it involves the inconvenience of forming a parasitic transistor.
Conventionally, it was necessary to configure the circuit using external connections, so using this type of circuit configuration was difficult in terms of manufacturing, mass production, and reliability of the circuit device.
It is not necessarily sufficient.

The present invention solves the above-mentioned problems and provides a multi-stage coupled transistor circuit device having high speed switching operation and high reliability. The present invention provides a semiconductor device in which a diode that does not have a parasitic transistor effect is provided between bases within a single semiconductor substrate.

The present invention will be explained in detail below with reference to the drawings.

FIGS. 4a and 4b show an embodiment of the present invention. FIG. 4a is a sectional view of a semiconductor device in which first and second stage transistors are formed on the left and right sides, and FIG. It is an impurity concentration distribution graph seen from the surface side in the depth direction of the XX cross section.

In Figure 4a, 1 is the first stage transistor
An N-type silicon substrate, which is a semiconductor substrate of one conductivity type, serves as a common collector region of Tr 1 and the second stage transistor Tr _{2 ,} and P 2 serves as a common base region of the first stage transistor Tr ₁ and the second stage transistor Tr _2.
3 is an N-type diffusion region that becomes the emitter region of the first stage transistor Tr ₁ ; 4 is an N-type diffusion region that becomes the emitter region of the second stage transistor Tr ₂ ;
5 is a resistance region forming the resistance R ₁ , 6 is a resistance region forming the resistance R ₂ , 7 is a PN junction part forming the diode D ₁ , and 13 is the first stage transistor Tr _1.
an N-type diffusion region (first region) built into the base region of the diode D2 and serving as the cathode region of the diode _D2 ;
14 is a P-type diffusion region (second region) that is built into the N-type diffusion region 13 and becomes the anode region of the diode D ₂ ; 8 is the base region of the first stage transistor Tr ₁ and the cathode of the diode D ₂ ; a base electrode that also serves as internal wiring for interconnecting the regions;
Reference numeral 9 denotes an internal wiring for interconnecting the emitter region of the first stage transistor Tr ₁ , the anode region of the diode D ₂ , and the base region of the second stage transistor Tr ₂ .

Note that 10 is an emitter electrode, 11 is a collector electrode, and 12 is an insulating film such as silicon dioxide (SiO ₂ ).

P-type diffusion region 1 which becomes the anode region in FIG. 4a
4 and the N-type diffusion region 13 which becomes the cathode region, when operating the PN junction formed by the P-type diffusion region 14, the N-type diffusion region 13,
If the current amplification factor of the so-called PNP parasitic transistor constituted by the P-type diffusion region 2 is made extremely small, its transistor action can be eliminated.

As shown in FIG. 4b, the present invention suppresses the active impurity concentration of the P-type diffusion region 14 to be lower than the active impurity concentration of the N-type diffusion region 13, so that even in the PNP parasitic transistor structure as described above,
The current amplification factor is made extremely small so that the transistor action can be ignored.

Such a concentration distribution can be obtained by suppressing the impurity concentration in the P-type diffusion region 14 to a slightly higher level than the surface concentration of diffused impurities in the N-type diffusion region 13 during impurity deposition. For example, the diffusion impurity surface concentration of the N-type diffusion region 13 is 1.5×
In the case of 10 ²⁰ /cm ³ , by setting the impurity concentration of the P-type diffusion region 14 to 3.0×10 ²⁰ /cm ³ during vapor deposition, the impurity surface concentration of the P-type diffusion region 14 becomes 7.0×10 ¹⁹ /cm after the diffusion heat treatment. It becomes ³ . A graph obtained by measuring such an impurity diffusion profile corresponds to FIG. 4b.

The current amplification factor of the PNP parasitic transistor formed in this way is extremely low, so
The effect of the PNP parasitic transistor can be almost completely eliminated, and the PN consists of a P-type diffusion region 14 which becomes an anode region and an N-type diffusion region 13 which becomes a cathode region.
The junction will behave as a diode.

As is clear from the above explanation, according to the present invention, not only can diodes for speeding up the Darlington connection circuit be integrated into a single semiconductor substrate, but also the cathode region of the diode By making the active impurity concentration of the first region lower than the active impurity concentration of the second region serving as the anode region, the reliability of the semiconductor device can be increased by suppressing parasitic transistor action. Moreover, by simply adding a step to form the diode region to the manufacturing process of conventional Darlington-connected circuit elements, it has the same switching speed and reliability as the conventional circuit configuration in which diodes are added through external connections. It is possible to obtain a semiconductor device that is very excellent in terms of.

Further, in the above explanation, an NPN type Darlington connection circuit device was illustrated, but it goes without saying that the present invention can be similarly applied to a PNP type.

[Brief explanation of drawings]

Fig. 1 is an equivalent circuit diagram of a conventional Darlington connection circuit, Fig. 2 is a cross-sectional view of a conventional Darlington connection circuit device, Fig. 3 is an equivalent circuit diagram of a Darlington connection circuit with a diode inserted, and Fig. 4a is an equivalent circuit diagram of a conventional Darlington connection circuit device. FIG. 4b, which is a cross-sectional view of a Darlington connection circuit device according to an embodiment of the invention, is an active impurity concentration distribution diagram of the diode portion of the invention. 1... N-type silicon substrate, 2, 14... P-type diffusion region, 3, 4, 13... N-type diffusion region, 5, 6
... Resistance region, 7 ... PN junction portion, 8 ... Base electrode, 9 ... Internal wiring, 10 ... Emitter electrode, 11 ... Collector electrode, 12 ... Insulating film.

Claims (1)

[Claims] 1. A semiconductor device having a multi-stage coupled transistor configuration in which a plurality of emitter regions of one conductivity type are provided in a common base region of an opposite conductivity type provided on a semiconductor substrate of one conductivity type, the base region of a first stage transistor. forming a first region of one conductivity type independent of the emitter region; forming a second region of the opposite conductivity type in the first region; The emitter region of the first stage transistor is electrically shorted, and the first region is electrically shorted to the base region of the first stage transistor, and the active region of the second region is electrically shorted. A semiconductor device characterized in that the impurity concentration is lower than the active impurity concentration of the first region.