JPH0412036U - - Google Patents
Info
- Publication number
- JPH0412036U JPH0412036U JP5190890U JP5190890U JPH0412036U JP H0412036 U JPH0412036 U JP H0412036U JP 5190890 U JP5190890 U JP 5190890U JP 5190890 U JP5190890 U JP 5190890U JP H0412036 U JPH0412036 U JP H0412036U
- Authority
- JP
- Japan
- Prior art keywords
- receiver
- memory
- change
- signals
- detection means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 4
- 238000000605 extraction Methods 0.000 description 2
- 241001389010 Tuta Species 0.000 description 1
Description
図面は本考案の一実施例を説明するためのもの
で、このうち第１図は本考案の一実施例における
プロツタインターフエースアナライザの原理的な
構成を示すブロツク図、第２図はこのプロツタイ
ンターフエースアナライザの有効事象抽出回路を
中心とした要部を具体的に示したブロツク図、第
３図はプロツタインターフエースアナライザの具
体的な回路構成を示したブロツク図、第４図は表
示器の表示内容の一例を示す平面図である。
１３……ライン、１３Ａ……データ線、１３Ｂ
……制御線、１４……レシーバ、１６……メモリ
回路、１８……有効事象抽出回路、２２……表示
器。
The drawings are for explaining one embodiment of the present invention. Among them, Fig. 1 is a block diagram showing the basic configuration of a plotter interface analyzer in one embodiment of the present invention, and Fig. 2 is a block diagram showing the basic configuration of a plotter interface analyzer according to an embodiment of the present invention. A block diagram specifically showing the main parts of the Tuta Interface Analyzer, centering on the effective event extraction circuit, Figure 3 is a block diagram showing the specific circuit configuration of the Protuta Interface Analyzer, and Figure 4 is the display. FIG. 3 is a plan view showing an example of display contents of the container. 13...Line, 13A...Data line, 13B
...Control line, 14...Receiver, 16...Memory circuit, 18...Valid event extraction circuit, 22...Display device.
Claims (1)
ストコンピユータとプロツタとの間で授受するた
めに用意された複数の線路からこれら各種信号を
傍受するレシーバと、 前記複数の線路のうちの特定の線路から傍受し
た信号の論理レベルの変化を検出するレベル検出
手段と、 このレベル検出手段が論理レベルの変化を検出
した時点における前記レシーバによりて受け取つ
た各種信号を記憶するメモリと、 このメモリに記憶されたこれらの信号を解析用
データとして表示する表示手段 とを具備することを特徴とするプロツタインター
フエースアナライザ。[Claims for Utility Model Registration] A receiver for intercepting various signals for plotting characters and figures from a plurality of lines prepared for transmitting and receiving these signals between a host computer and a plotter; Level detection means for detecting a change in the logic level of a signal intercepted from a particular line among the lines; and a memory for storing various signals received by the receiver at the time when the level detection means detects a change in the logic level. and display means for displaying these signals stored in the memory as data for analysis.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5190890U JPH0412036U (en) | 1990-05-18 | 1990-05-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5190890U JPH0412036U (en) | 1990-05-18 | 1990-05-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0412036U true JPH0412036U (en) | 1992-01-31 |
Family
ID=31571759
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5190890U Pending JPH0412036U (en) | 1990-05-18 | 1990-05-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0412036U (en) |
-
1990
- 1990-05-18 JP JP5190890U patent/JPH0412036U/ja active Pending
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