JPH04120736A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is classified as a method of manufacturing a semiconductor device for the purpose of improving characteristics, and more specifically, it is an improvement of a method of manufacturing a polycrystalline silicon thin film transistor in a self-aligned manner.

[Prior Art] In order to achieve a self-aligned structure of a polycrystalline silicon thin film transistor (hereinafter referred to as TPT), ion implantation into a staggered structure is known. However, in this structure, elements in the gate insulating film are knocked on to the polycrystalline silicon in the channel portion, which poses a problem in improving characteristics by thinning the channel portion.

[Problems to be Solved by the Invention] It is an object of the present invention to devise a self-aligned manufacturing method for an inverted staggered structure TPT that prevents knock-on to the channel portion, with the aim of improving the characteristics of the TPT.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention is intended to solve the above-mentioned problems, and includes the steps of forming a first polycrystalline silicon serving as a gate electrode on an insulating substrate or an insulating film; There is a step of forming a gate insulating film on the first layer, then a step of depositing and patterning a second polycrystalline silicon that will become the source and drain regions, and then using the second polycrystalline silicon as a mask to remove impurities from the first layer. doping the polycrystalline silicon, then annealing to activate the impurities, then depositing and patterning a third polycrystalline silicon that will form the channel region, and then The method is characterized by comprising the steps of forming an insulating film, then patterning the interlayer insulating film to open contacts from the source/drain regions, and then forming electrode wiring in the source/drain regions. A method for manufacturing a semiconductor device is used as a means.

[Example] The details of the present invention will be explained with reference to an example. FIG. 1 is an embodiment showing the steps of a method for manufacturing a semiconductor device according to the present invention.

As shown in FIG. 1(a), an insulating film 102 is first formed on a glass substrate 101. As shown in FIG. The purpose of the insulating film is to prevent heavy metals and the like contained in the glass substrate from diffusing into the element portion during heat treatment, and it is not necessary as long as the purity of the glass substrate is sufficiently high. Next, undoped polycrystalline silicon 10
3 is deposited and patterned to form a part of the gate electrode of the semiconductor element. Next, as shown in FIG. 1(b), 1000 gate insulating films 104 are deposited.

Next, polycrystalline silicon I containing phosphorus or boron impurities
I! 3,000 layers of 105 are deposited and patterned to form drain and source regions. Here, the source/drain regions may be formed by depositing impurity-free polycrystalline silicon and then implanting impurities by ion implantation.Next, as shown in FIG.
Ions are implanted into the polycrystalline Zinocon 103 at an energy of 150 KeV using the drain and source portions as masks.

Impurities are implanted into the first polycrystalline silicon in a self-aligned manner. Next, the implanted impurities were heated to 600°Cl2O
Activate by annealing for a time. As a result, a gate electrode 107 is formed in a self-aligned manner on the polycrystalline silicon 103. As shown in FIG. 1
1i 109 is deposited, contacts are opened in the source/drain regions, and electrode wiring is performed at A1.

[Effects of the Invention] According to the present invention, it is possible to manufacture a self-aligned structure of polycrystalline silicon TPT, the parasitic capacitance of the TPT is reduced, and the characteristics of the TPT can be improved.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(d) are process diagrams of an embodiment showing a method for manufacturing a semiconductor device according to the present invention. 101 ・ 102 ・ Glass substrate, insulating film, first polycrystalline silicon containing no impurities, gate insulating film, polycrystalline silicon containing impurities, ion beam, self-aligned gate electrode, first polycrystalline silicon containing no impurities 2. Polycrystalline silicon, interlayer insulating film, A1 electrode and above Applicant: Seiko Epson Corporation

Claims (1)

[Claims] A step of forming a first polycrystalline silicon film that will become a gate electrode on an insulating substrate or an insulating film, a step of forming a gate insulating film on the polycrystalline silicon, and a step of forming a second polycrystalline silicon film that will become a source and drain region. Depositing and patterning polycrystalline silicon, then doping the first polysilicon with impurities using the second polysilicon as a mask, and annealing to activate the impurities. Next, a step of depositing and patterning a third polycrystalline silicon to form a channel region, then a step of forming an interlayer insulating film, and then patterning the interlayer insulating film to form a source layer. 1. A method of manufacturing a semiconductor device, comprising the steps of opening a contact from a drain region, and then forming an electrode wiring in the source/drain region.