JPH04120984A - Magnetic recording and reproducing device - Google Patents

Abstract

PURPOSE:To copy an address multiplex control signal by sending duty information of a reproduced address multiplex control signal to a transmission destination and controlling the duty ratio of the control signal through the use of the sent duty information. CONSTITUTION:When a video signal is not delayed, a reproduced video signal is inputted to an output circuit 404 via a switch 403 and sent to a 2nd VTR, and when the video signal is delayed, the switch 403 selects the video signal from a D/A converter 407 and the selected signal is fed to the output circuit 404. A synchronizing separator circuit 408 separates a synchronizing signal from the reproduced video signal and gives it to a timing generator 409, from which a clock is generated and in which various timing signals synchronously with the video signal are generated. The digitized video signal by an A/D converter 405 is stored once in a frame memory 406 and then read. The timing with the duty information is coincident with the video signal by delaying the video signal by one frame and an address is matched accurately.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) This invention is a method for recording information contained in a control signal of a magnetic recording/reproducing device (video tape recorder: VTR) onto another VTR. The present invention relates to a magnetic recording and reproducing device that can perform the following functions.

(Prior Art) Recent VTRs are equipped with a circuit that records cue information and program search information using control signals.

FIG. 5(a) shows a 30 Hz control signal waveform in a VTR. The leading edge of the control signal is
Normally, there is a 1:1 relationship for one track (one field) by helical scanning, and the trailing edge is as shown in Figure (b).
As shown in (C), it is used as "0" or "1" information.

In this way, a method (V
ISS) and a method for recording and reproducing addresses for program searches (VASS) are known. Hereinafter, a control signal containing such information will be referred to as an address multiplex control signal.

FIG. 6 shows a conventional system for recording the above address multiplex control signal, and FIG. 7 shows a system for reproducing the above address multiplex control signal.

In FIG. 6, a recorded video signal is input to an input terminal 11 and introduced into a synchronization separation circuit 14. The input terminal 12 receives a phase pulse containing rotational phase information of the rotating drum section 24 on which the magnetic head is mounted, and the input terminal 13 receives a frequency pulse containing rotational speed information.

The vertical synchronization signal separated by the synchronization separation circuit 14 is input to a recording control signal generation circuit 15 and a phase comparator 21. The control signal generation circuit 15 is shown in FIG. 5(a).
A control signal with a duty of -50% as shown in is created and supplied to the recording amplifier 16. recording amplifier 16
Then, as will be described later, the duty of the control signal is controlled to create an address multiplex control signal, and its output is supplied to the control head 17. As a result, the address multiplex control signal is recorded on the control track of the magnetic tape 18.

The drum phase pulse and the vertical synchronization signal are determined by the phase comparator 21.
The phases are compared and the phase difference is detected. The phase error information is input to the drive circuit 23. The frequency pulse is also input to the speed discrimination circuit 22 and
Fluctuations in the rotational speed are detected. This rotation speed information also
The signal is input to the drive circuit 23. As a result, the drive circuit 23
controls the rotation of the motor of the rotary drum section 24 so as to have a constant speed and to be phase synchronized with the vertical synchronization signal of the input video signal.

Note that the drum phase pulse is also input to the control signal generation circuit 15 in order to set the phase of the control signal so that this phase pulse and the leading edge phase of the control signal have a constant relationship.

50 is a duty control circuit for controlling the duty of the control signal. Heading information or address information from a microcomputer or an operation input section is input to the data creation section 51. The data creation unit 51 creates serial data corresponding to the contents of input information (address, etc.), and generates serial data once per period of the control signal.
Output the corresponding bits. This output is input to the duty command signal generation section 52. Then, the duty command signal generation section 52 outputs a control signal to set the duty shown in FIG. 5(b) or (C) according to the data "0" or "1", and and control its gain.

FIG. 7 shows a system for reproducing address multiplex control signals recorded on the magnetic tape 18 as described above.

The address multiplexed control signal picked up by the control radar 17 is input to a regenerative amplifier 31 and amplified, and then input to a waveform shaping circuit 32 where it is waveform-shaped. The waveform-shaped address multiplex control signal is input to the phase discrimination circuit 33 and also to the duty discrimination circuit 61.

The phase discrimination circuit 33 detects the phase of the leading edge of the address multiplex control signal and detects the phase relationship with the reference vertical synchronization signal. The reference vertical synchronization signal is input from the input terminal 35 and is input to the phase discrimination circuit 33 via the tracking adjustment circuit 34. As a result, the phase discrimination circuit 3
3 detects whether or not the control signal has a predetermined phase relationship with respect to the reference vertical synchronization signal, and inputs the error into the drive circuit 44.

On the other hand, a frequency pulse from a capstan section 45 that drives the magnetic tape 18 to travel is input to the input terminal 40 . This frequency pulse is inputted to a waveform shaping circuit 42 via an amplifier 41, subjected to waveform shaping, and inputted to a speed discrimination circuit 43. In the speed discrimination circuit 43, for example, the reproduction mode (
Since the frequency of the frequency pulse is known depending on the normal playback, double speed, etc.), it is possible to detect whether it is the desired frequency or not.
Detect the frequency error. This frequency error information is also input to the drive circuit 44.

Thereby, the drive circuit 44 drives the capstan motor of the capstan unit 45 at a speed corresponding to the desired reproduction mode, and controls the reference vertical synchronization signal and the control signal so that a predetermined phase relationship is maintained. The reference vertical synchronization signal is passed through the tracking adjustment circuit 34 to the phase discrimination circuit 3.
The reason why the reproduction timing of the control signal and the vertical synchronizing signal is to correct an error in the reproduction timing of the control signal and the vertical synchronizing signal is that the mechanical positions of the rotary drum and the control head do not necessarily match depending on the VTR model.

Since this error appears as a tracking deviation, a tracking adjustment signal is supplied from the terminal 36, and the tracking adjustment circuit 34 adjusts the amount of delay of the reference vertical synchronization signal.

Next, the duty of the address multiplex control signal outputted from the waveform shaping circuit 32 is detected by the duty determining circuit 61 and input to the code conversion section 62. The code converter 62 accumulates the "0" and 1" pigs obtained for each field, creates a code, and determines the header contents and address contents. This determination result is sent to the system control section, and the It is used for controlling, stopping, speed switching, playback mode switching, etc.

(Problem to be Solved by the Invention) According to the above-described conventional magnetic recording/reproducing device, there is a function to create and record an address multiplex control signal by itself, and a function to reproduce an address multiplex control signal recorded in advance on a magnetic tape. It has functions that can be used. However, when dubbing, it does not have a function to send the address multiplex control signal as it is to the destination recording device, and a function to directly record the manually inputted address multiplex control signal as it is. In other words, in the conventional system, dubbing of the address multiplex control signal itself is not taken into account.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a magnetic recording/reproducing apparatus that is capable of dubbing the address multiplex control signal itself as it is.

[Structure of the Invention] (Means for Solving the Problems) In a reproduction system, the present invention includes a determination means for determining the duty of a reproduced control signal, and a duty determination obtained from the determination means. a delay means for delaying the signal and synchronizing it with the reproduced video signal of the next frame; and a multiplexing means for multiplexing the duty discrimination signal outputted from the delay means on a specific horizontal line in the vertical retrace period of the reproduced video signal. , in the recording system, extracting means for extracting duty information multiplexed on the reproduced video signal and reproducing a duty discrimination signal;
and control signal control means for controlling the duty of the non-modulated control signal for recording based on the duty discrimination signal obtained by this means.

(Function) By the means described above, the duty information of the reproduced address multiplex control signal can be sent to the transmission destination.

Furthermore, the duty of the control signal can be controlled using the transmitted duty information, and as a result, the address multiplex control signal can be duplicated (dubbed).

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The block surrounded by 200 represents the reproduction system of the first VTR, and the block surrounded by 300 represents the recording system of the second VTR.

It is now assumed that an address multiplex control signal is recorded on the magnetic tape 201.

202 is a video magnetic head for recording and reproducing video signals, and 203 is a control head for recording and reproducing control signals. The signal reproduced by the video magnetic head 202 is input to a video signal reproduction processing circuit 204 and is reproduced into a video signal. This reproduced video signal is input to a clamp circuit 211 and a synchronization separation circuit 22. Further, the reproduced video signal is supplied to one terminal of the switch 215.

The clamp circuit 211 is a circuit that clamps the level of the reproduced video signal to a constant flat level, thereby stabilizing the DC level. Synchronous separation circuit 21
2 separates a synchronization signal from the reproduced video signal and supplies it to a phase-locked loop circuit 213. The phase-locked loop circuit 213 creates a system clock synchronized with the separated synchronization signal and various timing signals. The system clock and timing signals are input to the duty-information multiplex control circuit 214.

This duty-information multiplexing circuit 214 is connected to the switch 21
During a specific period of the reproduced video signal (for example, one appropriate horizontal period from 10H to 20H of the vertical blanking period) (hereinafter this period will be referred to as the duty-information multiplexing period), the clamp circuit 211 The output from the video signal reproduction processing circuit 204 (the stabilized part of the DC level) is selected and sent to the multiplex circuit 216, and during other periods, the reproduced video signal from the video signal reproduction processing circuit 204 is sent to the multiplex circuit 216.

The multiplexing circuit 216 receives the duty discrimination data from the duty information multiplexing circuit 214 during the duty information multiplexing period, and outputs the reproduced video signal from the switch 215 as is during other periods.

The duty discrimination data is created as follows.

The address multiplex control signal is regenerated by the control head 203 and amplified by the regenerative amplifier 205.
The waveform is shaped by a waveform shaping circuit 206. Waveform shaping circuit 2
The signal shaped in step 06 is sent to the duty discrimination circuit 207.
The duty is determined. The discrimination data from here is that when dubbing is not performed,
The signal is introduced into a code converter (not shown) via switch 208. However, when dubbing is in progress,
The signal is inputted to the duty-information multiplex control circuit 214 via the delay circuit 209.

Here, the duty-information multiplexing circuit 214 sends out the discrimination data during the above-described duty-information multiplexing period and supplies it to the multiplexing circuit 216.

As a result, the reproduced video signal output from the multiplexing circuit 216 has the following characteristics during the duty-information multiplexing period within the vertical blanking period:
This means that the duty information of the control signal is multiplexed. This reproduced video signal is outputted to an output terminal 218 as a transmission signal via an output circuit 217.

The reproduced video signal sent to the input terminal 301 of the second VTR is input to a video signal recording processing circuit 302, a clamp circuit 311, and a synchronization separation circuit 312. The video signal recording processing circuit 302 converts the input signal into a signal suitable for the recording format and supplies it to the video magnetic head 303. As a result, a video signal is recorded on the magnetic tape 304.

The synchronization separation circuit 312 separates the synchronization signal from the reproduced video signal and sends the separated synchronization signal to the phase-locked loop circuit 3.
13 and the control signal generation circuit 314.

The control signal generation/circuit 314 utilizes the separated vertical synchronization signal to generate a signal at 30Hz (duty -50%).
) and send it to the recording amplifier 31.
Enter 5.

The duty of this control signal is controlled by the previous duty information, and the converted address multiplex control signal is supplied to the control head 320.

The reproduction of duty information will be explained.

The synchronization signal separated by the synchronization separation circuit 312 is input to a phase locked loop circuit 313. The phase-locked loop circuit 313 creates a clock synchronized with the synchronization signal and various timing signals, and inputs them to the duty information extraction control circuit 316.

As a result, the duty information extraction control circuit 316
The period during which the duty information is multiplexed is grasped, and the slice circuit 317 is operated at this timing. Therefore, the slice circuit 317 slices and extracts the duty information from the signal whose DC level has been stabilized by the clamp circuit 311. The extracted duty information is input to the data creation section 318 and formatted into the same data as the duty discrimination data reproduced on the sending side.

This discrimination data is input to the duty command signal generation section 319 in synchronization with the timing of the control signal. The duty-command signal generation unit 319 outputs a gain control signal to control the gain of a predetermined section of the control signal according to the discrimination data “O”1, and supplies it to the recording amplifier 315. Note that the switch 321 , in the dubbing mode, the duty command signal generation section 319
However, when creating and recording an address multiplex code signal for the first time in this VTR, the duty command signal created by instructions from the microcomputer or operation unit is selected. do.

As mentioned above, in this system, the first VT
The same address multiplex control signal as the address multiplex control signal reproduced in R can be dubbed to the second VTR side. In this case, since the duty information of the address multiplex control signal is multiplexed and transmitted during a specific period of the video signal, a special dedicated transmission path is not required.

In the above explanation, the playback system of the first VTR and the second VT
Although an R recording system is shown, the first VTR is also provided with a similar recording system, and the second VTR is also provided with a similar reproduction system.

The reason why the delay circuit 209 is provided in the reproduction system will be explained below with reference to FIG.

FIG. 2(a) shows a head switching signal for alternately switching between the A head and B head, which are provided 180 degrees opposite to each other on the rotating drum, and FIG. 2(b) shows the reproduced video signal,
FIG. 2C shows the reproduced address multiplex control signal. The leading edges of the address multiplex control signal are at regular intervals, but the trailing edges have different phases depending on the information being multiplexed, that is, are duty-modulated.

FIG. 4(d) shows a path 402 from the duty discrimination circuit 207.
The video signal played back is analog digital (A/D)
The signal is input to the converter 405 and the synchronous separation circuit 408, and is also input to one input terminal of the switch 403.

When the video signal is not delayed, the reproduced video signal is input to the output circuit 404 via the switch 403 and transmitted to the second VTR side.

When delaying the video signal, switch 403 selects the video signal from digital-to-analog (D/A) converter 407 and supplies it to output circuit 404 .

A synchronization separation circuit 408 separates a synchronization signal from the reproduced video signal and supplies it to a timing generator 409. A timing generator 409 generates a clock and various timing signals synchronized with the video signal. A
The video signal digitized by the /D converter 405 is once stored in a frame memory 406 and then read out.

As a result, the video signal is delayed by one frame. The video signal output from the frame memory 406 is D
The signal is converted into an analog video signal by the /A converter 407 and supplied to the output circuit 404 via the switch 403.

If the video signal is delayed by one frame in this way, the timing will match with the corresponding duty information shown in FIG. 1, and the addresses will correspond accurately.

[Effects of the Invention] As explained above, according to the present invention, by simply adding a relatively simple circuit, it is possible to dub the address multiplex control signal itself as it is, and the VISS
/VASS function can be used effectively.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing one embodiment of the present invention, FIG. 2 is a timing chart shown to explain the operation of the circuit in FIG. 1, and FIG. 3 is an explanatory diagram of a state in which the invention is used. FIG. 4 is an explanatory diagram showing an example of transmission of duty information, FIG. 5 is a configuration diagram showing another embodiment of the present invention, and FIG. 6 is an explanatory diagram of waveforms shown to explain an example of the use of control signals. , FIG. 7 is a circuit diagram showing a recording system for address multiplex control signals, and FIG. 8 is a circuit diagram showing a reproduction system for address multiplex control signals. 100...Reproduction system, 200...Recording system, 117.2
17...Control spatula F, 118.218...Magnetic tape, 131...Reproduction amplifier, 132...Waveform shaping circuit, 161...Duty discrimination circuit, 162
. . . code converter, 201 . . . delay circuit, 202.
... Output circuit, 116... Recording amplifier, 151...
Data creation unit, 152.206...Duty command signal creation unit, 205...Input circuit, 207...Switch. Applicant's agent Patent attorney Takehiko Suzue

Claims (4)

[Claims] (1) In the reproduction system, there is a determining means for determining the duty of the reproduced control signal, and a delaying means for delaying the duty determination signal obtained from the determining means and synchronizing it with the reproduced video signal of the next frame. and multiplexing means for multiplexing the duty discrimination signal outputted from the delay means onto a specific horizontal line in the vertical retrace period of the reproduced video signal; The present invention includes an extraction means for extracting information and reproducing a duty discrimination signal, and a control signal control means for controlling the duty of a non-modulated control signal for recording based on the duty discrimination signal obtained by the means. A magnetic recording/reproducing device characterized by: (2) The magnetic recording and reproducing apparatus according to claim 1, wherein a clamp circuit for stabilizing the pedestal level of the reproduced video signal is provided in the reproduced video signal path upstream of the multiplexing means. . (3) The reproduced video signal path before the multiplexing means is provided with a delay means for delaying the reproduced video signal by one frame in order to synchronize the timing of the reproduced video signal and the duty information. The magnetic recording/reproducing apparatus according to claim 1, wherein: (4) The magnetic recording/reproducing apparatus according to claim 1, wherein the multiplexing means includes rise information and fall information of a control signal on the reproduction side.