JPH04128890A - Frame memory control method for bit map display device - Google Patents

Abstract

PURPOSE:To obtain a frame memory which enables fast drawing in an X and a Y direction with the same data by dividing a screen into block areas which consists of X- and Y-directional picture elements as many as memories and processing picture element data. CONSTITUTION:The screen is divided into the block areas BL1 consisting of the X- and Y-directional picture elements as many as the memories, respective picture elements in each of X- and Y-directional arrays in the areas BL1 are made to correspond to the memories A - D in specific correspondence pattern, and picture element data determined by the correspondence pattern are stored in the memories in display address order. When picture elements are displayed, one corresponding picture element is read out of each of the memories A - D at the same time and arrayed in the display address order. For any X- or Y-directional picture element array in one area BL1, the picture element data is stored in the areas of the respective memories corresponding to the respective picture elements in the picture element array at the same time.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a method for controlling a frame memory in a bitmap display device having a frame memory. Note that in the following figures, the same reference numerals indicate the same or corresponding parts.

[Conventional technology]

FIG. 12 shows an example of the configuration of this type of bitmap display device. In the same figure, 1 is C that displays the image on the screen.
RT, 21 is a frame memory that stores pixel data corresponding to each pixel on the display screen, and 20 is a CPU that controls the entire display device. By the way, in order for the CPU 20 to display straight lines on the CRTI or display filled figures at high speed, when writing the same data to consecutive address spaces in the frame memory 21, this write operation is performed as fast as possible. A method is known in which consecutive address spaces are constructed from separate memories, and the same data is written to each memory every time. FIG. 13 is a block diagram showing a configuration example of a conventional frame memory 21 having a plurality of memories A to D in which such data can be written. In the same figure, memory A, memory B
, memory C, and memory D each have pixel data of pixels sequentially arranged in the X direction of the CRTI. That is, FIG. 14 shows the correspondence between each memory A to D and the address (display address) of the CRTI, and memory A, memory B, memory C, and memory D correspond to A, B, C, and C in the figure, respectively. Corresponds to the symbol D. In addition, in FIG. 13, 12 is the lead/read of memories A-D.
A memory control unit that controls writing; 5 a display address generator that generates an address (display address) on the display screen in the order of CRTI screen scanning to the memory control unit 1'2 during screen display; 11 a memory control unit; From part 12 to each memory A-
A memory address 6 is given to each memory at the same time to D, and a read/write memory control signal 6 is given individually to each memory A to D from the memory control unit 12. 15 is a data bus connected to a CPU 20 (not shown) and exchanges pixel (image) data, etc.; 16 is an address bus for receiving display addresses, etc. for pixel data on the data bus 15 from the CPU 20; and 17 is a bus given from the CPU 20; This is a read/write control signal for memories A-D. Further, 14 is a memory bus selector, 19 is an image data bus connecting this selector 14 and each memory A to D,
The memory bus selector 14 selects any or all of the memories A to D via the image data bus 19 to exchange image data with the data bus 15. FIG. 15 shows an example of writing the same data into memories A to D in FIG. 13 at one time. In this case, the memory bus selector 14 selects all image data buses 19. In FIG. 13, the parallel/serial converter 3 inputs display image data (pixel data) from memory A, memory B, memory C, and memory D via the display image data bus 18 at - degrees, and inputs the display image data (pixel data) to the DA converter 2. Output in units of pixels (hereinafter also referred to as pixels). In addition, the DA converter 2 converts the output data of the converter 3 into a CRTI
Let it be the luminance signal.

[Problem to be solved by the invention]

However, in the conventional bitmap display device as described above, the same data can be written in the X direction in one access, but cannot be written in other directions. SUMMARY OF THE INVENTION An object of the present invention is to provide a frame memory control method for a bitmap display device that can write the same data not only in a specific direction but also at high speed.

[Means for Solving the Problems] In order to solve the above problems, the method of claim 1) is based on the following method: ``Raster scanning is performed by a plurality of memories (A-D, etc.) having the same structure (CRTl, etc.). In a bitmap display device configured with one frame memory (such as 21) corresponding to a screen, the screen is divided into blocks whose number of pixels in each of the X and Y directions is equal to the number of the memory in the order of display address. The block area is divided into areas (such as BLI), and each pixel in each pixel column in the X direction and each pixel column in the Y direction in each block area is made to correspond one-to-one to each memory in a predetermined correspondence pattern, The pixel data of each pixel determined by the corresponding pattern is stored in each memory in the order of its display address, and when displaying the pixel, (memory control unit 12. memory address 11. 18, etc.), one corresponding pixel data is simultaneously taken out from each of the above-mentioned memories, and the taken out pixel data is arranged in the order of its display address (via selector 4, display address generator 5, etc.). Also, for any pixel column in each of the X and Y directions in the block area, The same pixel data can be stored simultaneously in each memory area corresponding to each pixel in this pixel column. The method of claim 2) is the method of claim 1), further comprising: the block area being a small block area having the same number of pixels in each of the X and Y directions, and each pixel in the area having one pair. 1
consists of small block areas corresponding to each of the above-mentioned memories, and for any small block area in the block area, simultaneously to the area of each of the above-mentioned memories corresponding to each pixel in this small block area. Assume that it is set to 1 so that the same pixel data can be stored.

[For use]

Divide the display screen into block areas in the order of display addresses in which the number of pixels in each of the X and Y directions is equal to the number of memories A-D (four in this case), and each pixel in the X direction in each block area. Each pixel in each column and each pixel column in the Y direction is arranged in a predetermined one-to-one correspondence pattern in each memory A.
-D, pixel data of each pixel determined by the corresponding pattern is stored in each of the memories A to D in the order of their display addresses, and a memory that controls read/write of the memories A to D. A control section 12 is provided within the frame memory 2, and supplies a memory address 11 and a memory control signal 6 to each memory A to D based on addresses from a display address generator 5 and an address bus 16. Furthermore, since the display position of the pixel data output from each memory A to D differs depending on the display address, a selector 4 is provided to rearrange the output data from the memories A to D.

【Example】

The present invention will be described in detail below based on FIGS. 1 to 12. FIG. 1 is a block diagram showing the configuration of a frame memory 21 as an embodiment of the present invention, and corresponds to FIG. 13. In FIG. 1, this frame memory 21
The memory sections within are memory A, memory B, and
The data bus I5 consists of four parts: memory C and memory D.
and is connected via the memory bus selector 14. However, in FIG. 1, compared to FIG. 13, the memory address 11 given to each memory A to D from the memory control unit I2 is given to each memory A to D individually, and the display address generator 5
The difference is that the address output of is also given to the selector 4, and that a conversion mode register 13 is newly provided between the data bus 15 and the memory control section 12. The memory control unit 12 inputs data from the conversion mode register 13 to the CPU.
20, and inputs a display address from address bus 16 and display address generator 5. The selector 4 outputs data from each memory A to D to the parallel-serial converter 3 based on address information from the display address generator 5. Figure 2 shows the addresses of memories A-D and CRTI in Figure 1 (
display address). In other words, each four pixels are associated with each other in both the X and Y directions, and the symbols A, B, C, and D in the figure represent memory A, respectively.
, memory B, memory C, and memory D. Note that this area has a total of 16 pixels, with 4 pixels in each of the X and Y directions,
That is, each area divided by solid lines in FIG. 2 is block area B.
It's called LI. FIG. 3 shows an example in which the same pixel data is written in four pixels lined up in the X direction in the block area BLI, and FIG. 4 shows an example in which the same pixel data is written in four pixels lined up in the Y direction. Further, FIG. 5 shows an example in which the same pixel data is written into a small block area BL2 formed within the block area BLI. With such address correspondence, when four pixels are consecutive in the X direction as shown in FIG. 3, the corresponding memory is memory D from FIG. Memory C, memory B, and memory A are all separate memories, and the write data ladder "4" from the data bus 15 is sent to each memory A to D via the memory bus selector 14 and written simultaneously. Similarly, as shown in Figure 4,
It is also possible to write the same data for four consecutive pixels in the Y direction. Furthermore, as shown in FIG. 5, it is also possible to write the same data to the small block area BL2 of two pixels each in both the X and Y directions. However, in the case of writing the same data to four pixels, the memory addresses 11 for accessing each memory A to D are different in FIGS. 4 and 5. However, for example, address 11 to be given to memory A,
The difference (relative address) from address 11 to be given to another memory BD is the writing mode of the same 4 pixel data within block area BLl (in other words, the block area B
Pixel column or small block area BL to be written in LI
2), which is independent of the position of the block area BLI within the screen. Therefore, by specifying this write mode to the memory control section 12, it is possible to simultaneously write the same data for four pixels as shown in FIGS. 4 and 5 to the memories A to D. Therefore, in order to distinguish between the write modes shown in FIGS. 3 to 5, the CPU 20 sets the corresponding write mode in the conversion mode register 13 before the memory control unit 12 accesses the memories A to D. The memory control unit 12 supplies a memory address 11 and a memory control signal 6 to each memory A to D based on the write mode of the conversion mode register 13 and the address and control signal 17 on the address bus 15 to write pixel data. . On the other hand, when displaying the CRTI, it is necessary to output pixel data from each of the memories A to D in response to the scanning of the CRTI electron beam and send it to the DA converter 2 via the parallel-serial converter 3. In FIG. 6, the pixels on the CRTl are numbered. FIG. 7 shows the numbers of pixels stored in each of memory A, memory B, memory C, and memory D.
The pixel arrangement in the X direction in the order of B, C, and D differs from the scanning order of the CRTI depending on the address in the Y direction. For this reason, C
If the RTI scanning method is a so-called raster scan method in which scanning in the X direction is repeated sequentially in the Y direction, memory A
, B, CD, the selector 4 rearranges the array of pixel data inputted to the parallel-serial converter 3 in the scanning order of the CRTI. 8 to 11 are explanatory diagrams of the pixel data array conversion operation for each Y-direction address by the selector 4, and the upper A, B, C, and D in these FIGS. 8 to 11 are memory A, memory B
, memory C, and memory D, and each pixel data input from each memory A to D is transferred to the lower part of FIGS. This shows that the data is rearranged in the order of scanning in the X direction, as shown in the data marked as output. Here, FIG. 8 shows the arrangement conversion operation of the selector 4 during horizontal line scanning with a Y-direction address value of 0, and similarly, FIGS. This shows the array conversion operation. Further, the arrangement conversion operation of the selector 4 similar to that shown in FIGS. 8 to 11 is repeated for each of the Y-direction address values 4 to 7 and the subsequent Y-direction address values in units of four horizontal scanning lines.

【Effect of the invention】

According to the invention of claim 1, in a bitmap display device in which one frame memory 21 corresponding to a screen of a CRTl that is raster scanned is configured by a plurality of memories A to D having the same structure, the screen is divided into block areas BLI in which the number of pixels in each of the X and Y directions is equal to the number of memories in the order of display addresses, and each pixel column in the X direction and each pixel column in the X direction in each block area BLI. Each pixel therein is made to correspond one-to-one to each of the memories A to D in a predetermined correspondence pattern, and the pixel data of each pixel determined by the correspondence pattern is stored in each memory in the order of its display address. and when displaying the pixels, the memory control unit 12. Memory address 11. The corresponding pixel data is simultaneously taken out one by one from each of the memories A to D via the memory control signal 69 display image data bus 18, etc., and the taken out pixel data is sent to the selector 4, display address generator 5, etc. The conversion mode register 13, the memory control unit 12. Memory address 11. Memory control signal 6. The same pixel data can be stored simultaneously in the areas of each memory corresponding to each pixel in this pixel column via the memory lot selector 141 image data bus 19, etc., so that drawing in the X direction or a straight line in the X direction is possible. It can be done quickly. According to the method of claim 2), in the invention of claim 1), furthermore, the block area is a small block area having the same number of pixels in each of the X and Y directions, and each pixel in the area is 1 to 1
A small block area BL corresponding to each of the above-mentioned memories is
2, and for any small block area BL2 in the block area, this small block area B
Since the same pixel data can be stored simultaneously in each memory area corresponding to each pixel in L2, partial areas on the screen can be filled with the same pixel data at high speed.

[Brief explanation of the drawing]

Fig. 1 is a block circuit diagram showing the configuration of a frame memory as an embodiment of the present invention, Fig. 2 is a diagram showing the correspondence between the memory in Fig. 1 and display addresses, and Figs. 3 to 5 respectively. A diagram showing an example of writing the same continuous data on the display screen to the memory of FIG. 1, FIG. 6 a diagram showing the correspondence between display addresses and pixel numbers, and FIG. 7 a difference between the memories of FIG. 1, Figures 8 to 11 are diagrams showing the correspondence with the numbers of pixels stored in this, and Figures 8 to 11 are for displaying the memory data in Figure 1. , respectively, is an explanatory diagram of an array conversion method for each Y-direction address, FIG. 12 is a block diagram showing configuration examples of the present invention and a conventional display device, and FIG. 13 is a block circuit of a conventional frame memory corresponding to FIG. 1. 14 is a diagram showing the correspondence between the memory in FIG. 13 and the display address, and FIG. 15 is a diagram showing an example of writing continuous identical data on the display screen to the memory in FIG. 13. 1: CRT, 2: DA converter, 3: Parallel/serial converter, 4: Selector, 5: Display address generator,
6: Memory control signal, A-D: Memory, 11: Memory address, 12: Memory control unit, 13: Conversion mode register, 14: Memory path selector, 15: Data hash, 1
6: Address bus, 17: Control signal, 18: Display image data bus, 19: Image data bus, 20: CPU, 21
: Frame memory, BLI block area, BL2: Small block area. Figure 2 Jyo 8 Figure O 9 Figure 10 Figure 11 Figure 14 Figure 15

Claims (1)

[Scope of Claims] 1) In a bitmap display device in which a plurality of memories having the same structure constitute one frame memory corresponding to a screen to be raster scanned, the screen is scanned in the order of display addresses X, Y. is divided into block areas in which the number of pixels in each direction is equal to the number of memories, and each pixel column in the X direction and Y
Each pixel in each pixel column in the direction is made to correspond one-to-one to each of the above-mentioned memories in a predetermined correspondence pattern, and the pixel data of each pixel determined by the above-mentioned correspondence pattern is stored in each memory in the order of its display address. When displaying the pixels, one corresponding pixel data is simultaneously retrieved from each of the memories, and the retrieved pixel data are arranged in the order of their display addresses, and the block area is A bitmap characterized in that, for any pixel column in each of the X and Y directions, the same pixel data can be stored simultaneously in each memory area corresponding to each pixel in this pixel column. Frame memory control method for display device. 2) In the method according to claim 1, furthermore, the block area is a small block area having the same number of pixels in each of the X and Y directions, and each pixel in the area has a one-to-one ratio.
consists of small block areas corresponding to each of the above-mentioned memories, and for any small block area in the block area, simultaneously to the area of each of the above-mentioned memories corresponding to each pixel in this small block area. A frame memory control method for a bitmap display device, characterized in that the same pixel data can be stored.