JPH0413300A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To accelerate a test by shortening time for testing the semiconductor memory device by simultaneously comparing data for one line after simultaneously writing the data for one line of a memory cell matrix. CONSTITUTION:A transfer means is provided to transfer all the data for one line written into one specified line of memory cell matrixes 1-4 to the other line selected by row decoders 5 and 6 according to a write instruction signal when a data control circuit 7 is set in a test mode, and a comparing means is provided to detect whether or not the data for one line of the memory cell matrixes 1-4 read by a read instruction signal is coincident with the data for one specified line. Thus, the data for one line can be simultaneously compared after simultaneously writing the data for one line of the memory cell matrixes 1-4, and the test can be accelerated by shortening the testing time.

Description

[Detailed Description of the Invention] [Summary] An object of the present invention is to provide a semiconductor memory device that can speed up the writing of test data and speed up functional tests, and which is addressed by row and column. a memory cell matrix; a row decoder that selects one of the rows of the memory cell matrix in response to an address signal; a column decoder that selects one of the columns of the memory cell matrix in response to an address signal; a data control circuit that controls writing/reading of data in a memory cell corresponding to a row and column, and the data control circuit controls writing/reading of data in a memory cell corresponding to a specific row and column of the memory cell matrix in response to a write instruction signal in a test mode. A transfer means that transfers all written data for one row to another row selected by a row decoder, and a transfer means that transfers all written data for one row to another row selected by a row decoder; and a comparison means for detecting whether or not it matches the data.

Further, in the semiconductor memory device, the column decoder includes column selection means that can select all the columns, and when in the test mode, the data control circuit selects one specific row of the memory cell matrix by the column selection means. and the same data written in all other rows, the comparison means compares the data in the specific row to see if they match the data in the other row.

[Industrial application field]

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that can speed up functional testing.

In the /-1-Li LSI, a memory cell and its peripheral circuits are mounted on the same chip. In testing memory LSIs, functional tests that test the operation of these circuits play the most important role, and various test patterns are used.

[Conventional technology]

When testing a conventional semiconductor memory device, such as a RAM, a test pattern consisting of input patterns such as addresses, write data, write/read signals, etc. and output expected value patterns is generated and executed using a pattern generator dedicated to the RAM. ing.

For example, in the case of a 256Kxl-bit RAM, in order to confirm that all memory cells can hold 0" and 1", write "0" 256 times, write "1" 256 times, 0” reading 256 times, 1
” is read 256 times.

[Problem to be solved by the invention]

However, in such conventional semiconductor memory devices, when testing a large capacity RAM, in order to confirm that all memory cells can hold "0" and "1", it is necessary to test "0" and "1". It is necessary to perform writing and reading for each memory cell, which poses a problem in that the test takes a lot of time.

On the other hand, as related prior art, for example,
There is a semiconductor memory device described in Japanese Patent No. 9-207477. This device detects whether data with the same bit pattern as the bit pattern given from the outside exists inside the device, and outputs the result. but,
This device is only used to quickly confirm whether or not a specified value has been written, and is a method of comparing the values of one row of the memory cell matrix with reference data at one time. Although this publication shows an example of a DRAM, normal writing to a DRAM is performed by reading out one row, changing only one column of it, and writing to the original row. In this case, only one change is made in one access.
It is only a bit, and it is not possible to write one row of data at the same time when writing to DRAM.
Therefore, it is only effective for reading data, but cannot speed up data writing.

There is also a technique described in Japanese Unexamined Patent Publication No. 59-82695, which is also a similar technique and is aimed at facilitating the search of stored data. Therefore, all of them were devised simply for data retrieval, and it is impossible to achieve high-speed writing of test data at all.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor memory device that can speed up the writing of test data and speed up functional tests.

[Means for Solving the Problems] In order to achieve the above object, the semiconductor memory device according to the present invention has a memory cell matrix addressed by rows and columns, and a memory cell matrix that is addressed by rows and columns, and a row decoder that selects one of the rows of the cell matrix; a column decoder that selects one of the columns of the memory cell matrix according to an address signal; and a column decoder that selects one of the columns of the memory cell matrix in response to an address signal; and a data control circuit that controls writing/reading, and when in the test mode, the data control circuit transfers all data for one row written to a specific row of the memory cell matrix to a row decoder in response to a write instruction signal. a transfer means for transferring data to another row selected by the above, and a comparison means for detecting whether or not the data for one row of the memory cell matrix read by the read instruction signal matches the data for the specific one row. It consists of and.

Further, in the invention according to claim 2, in the semiconductor memory device, the column decoder includes selection means capable of selecting all columns, and the data control circuit selects the memory by the column selection means in the test mode. The comparison means compares the same data written in one specific row and all other rows of the cell matrix to see if the data in the specific one row matches the data in the other one row. Vf to do
It is a sign.

[Effect]

In the first aspect of the invention, during testing, all columns are set to test mode, and when writing test data, test data written in one specific row of the memory cell matrix is transferred to other rows. Furthermore, when reading test data, it is detected whether the data for one row of the memory cell matrix read to the bit line matches the data for the specific one row or not, and the result is output.

Therefore, after data for one row of the memory cell matrix is written at one time, data for one row can be compared at one time, thereby significantly shortening test time and speeding up the test.

In the second aspect of the invention, during testing, all columns are set to test mode, and when writing test data, the same test data is written to all rows of the memory cell matrix. Also, when reading test data, all the data for one row of the memory cell matrix read to the bit line is “
0” or “1” is detected and the result is output.

Therefore, in addition to significantly reducing exam time,
When writing test data, the input data is written to all columns of the specified row at the same time, making testing particularly efficient.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

1 to 5 are diagrams showing a first embodiment of a semiconductor memory device according to the present invention, which is an example applied to a RAM.

Figure 1 is an overall configuration diagram of RAM, and in this figure,
1 to 4 are memory cell matrices that are addressed by row and column; 5.6 is a row decoder that selects one of the rows of the memory cell matrices 1 to 4 according to an address signal; and 7 is an address signal. The column decoder includes a selector and selects one of the columns of the memory cell matrices 1 to 4 according to the column decoder. Memory cell matrices 1 to 4 constituting the RAM are appropriately divided to adjust the aspect ratio of the chip and speed up access time, and this example shows an example in which a 256K×1 RAM is divided into four. . In this case, row decoder 5.6 uses row addresses AIO to A
Column decoder 7 decodes column address AO-A9 to select one row out of 256 rows, and column decoder 7 decodes column address AO-A9 to select one row from 256 rows.
IK and the l bit in the bit are selected to input and output data. FIG. 2 shows one of these blocks. One block consists of a 256×256 memory cell matrix.

A concrete circuit of one block shown in FIG. 2 is shown in FIG. In the figure, a memory cell matrix 1 has word lines W1 to W25 represented by rows 1 to 256 in the row direction.
6 and bit lines B1 to 8256 and 81 to 82 in the column direction
There are 56.

Describing the detailed circuit for one column j, M
1, j-M256. j (however, j
=256) is a memory cell, C, A 1 , j −G
A256. j and GBI.

j-Cy B256. j is a transfer gate, and there are 256 of these, but only the necessary parts are depicted in the figure. 14 is a sense amplifier, 15.16 is a gate, 17.18 is an inverter, 19 is an exclusive
20 is an output buffer, and 21 is a transistor. Further, Bj and Bj are bit lines, Cj is an output line of the gate 15, Dj is an output line of the sense amplifier 14, and G
l j, G2 j is a transfer gate, Slj, S2
j is a selector and DIO is a data line. To explain the signals, WE is a write enable signal, RE is a read enable full signal, and TEST signal. In addition, in the above, the sense amplifiers 14 of each column 1 to 256
The subsequent portion including Sense A and B (the portion below the sense A and B in the figure) together with the transistor 21 constitutes a data control circuit 22 as a whole.

The detailed circuit of the column decoder 7 as a transfer means and comparison means is shown in FIG. ~34, Nantes Gate 35~40,
Inverter 41 and AND gates 421 to 42-j,
43-1 to 43-j (j = 256). As shown in FIG. 5, the decoder 31 has two bits,
It converts 2-bit input data XO, XI into 4-bit output data 30-53, and outputs the 4-bit output data 30-53. . The same applies to the other decoders 32 to 34.

The outputs of the decoders 31 to 34 are combined by Nante gates 35 to 37, and the NAND logic is taken.
It is input to one of the input terminals 8 to 40. A TEST signal is input to the other input terminals of the Nant gates 38 to 40 via an inverter 41, and when the TEST signal is active (TEST=1), the Nant gates 35 to 3
The outputs of the Nant gates 38 to 40 are "1" regardless of the output level of the gate 7. Therefore, the signals at the levels corresponding to the write enable signal WE and the read enable signal RE at that time are applied to the AND gates 42-1 to 42-j.
, 43-1 to 43-j, respectively. The Nant gates 35 to 40 constitute column selection means that can select all columns. That is, when the TEST signal becomes active, the write enable signal WEi (i=1 to 256)
and read enable signal REi all become 1”,
It enters the state of test writing and test reading.

Next, the effect will be explained.

The operation will be divided into normal operation and operation during testing, and will be sequentially explained based on the circuit shown in FIG.

Normal writing to "seat" Lb is executed by setting the TEST signal to TEST=O and the write enable signal WE@WE=1.

When the data to be written is manually input to the data line DrO and an address signal is input, the row decoder 5 selects one row (row i) specified by the row address and selects the word line Wi corresponding to that row.
Outputs “1” to As a result, transfer gates CAi,j and CBi,j on word line Wi are opened.

The column decoder 7 selects one column (column J) specified by the column address, and inputs "1'" to the decode output WEj corresponding to that column.
′ is output. When WE j = l, transfer gates C1j, 02 j are turned on.

On the other hand, selectors Slj and S2j select data line DIO when TEST=O. As a result, the write data is output from the data line DIO to the bit lines Bj and B after passing through the selector S1j, transfer gates Glj and C2j. At this time, one side of the write data is inverted by the gate 16 and the inverter 18 and output to the bit lines Bj and Bd. The data on bit lines Bj, Bj are stored in memory cells Mi, j selected by row decoder 5.
be taken in. Through the above operations, data is written to the memory cell in the i row and j column.

Normal reading is performed by setting the TEST signal to TEST=O and setting the read enable signal RE to RE=1.

The row decoder 5 selects one row (row i) specified by the row address and outputs "1" to the word line Wi corresponding to that row. As a result, transfer gate GAi on word line Wi.

j, CB i+ J is opened, and the data of the selected row is transferred to all bit lines Bk, Bk (k=1 to 25
6). The data read onto the bit lines Bk and T is amplified by the sense amplifier 14 and sent to the selector S.
Pass through 2j. Selector S2j selects the output of sense amplifier 14 when TEST=O. On the other hand, the column decoder 7 selects one column (column j) specified by the column address,
#11+ is output to the decode output REj corresponding to that column. When REj=1, the output buffer 20 is turned on and the output value of the selector S2j is output to the data line DIO. However, the data line DIO is precharged in advance. By the above operation, the value of the memory cell in the i-th row and the j-th column is read to the data line DIO.

The test write is performed by setting the TEST signal to TEST=1 and setting the write enable signal WE to WE=1.

At this time, data in row 256 is transferred to the row selected by the row address. The row decoder 5 selects the 1 specified by the row address.
A row (row i) is selected and "1" is output to the word line Wi corresponding to the row. On the other hand, the data in row 256 is gate 1
It is output to the output line Cj of No. 5. Selector Slj is T
When EST=1, output line Cj of gate 15 is selected.

The column decoder 7 ignores the column address and outputs "1" to all decode outputs WEj (where j=1 to 256). When WE j = 1, the transfer gate CI L G2 j is turned on, and the data in row 256 of each column is output to Pip) & SBj, Bj via selector Slj, and written to all memory cells in row i. It will be done. By the above operation, data in row 256 is transferred to row i.

Test reading is performed by setting the TEST signal to TEST=1 and setting the read enable signal RE to RE=1.

At this time, the data in row 256 is compared with the data in the row selected by the row address, and the comparison result is output. The row decoder 5 selects one row (row i) specified by the row address and outputs "1" to the word line Wi corresponding to that row.

The data of the selected row is transmitted to all bit lines Bj, Bj
(However, j=1 to 256). The data read onto the bit lines Bj and Bj is sent to the sense amplifier 14.
The signal is amplified by the output line Dj and output to the output line Dj.

On the other hand, data in row 256 is output to output line Cj of gate 15. The data on output lines Cj and Dj is subjected to exclusive OR logic by exclusive OR gate 19, selected by selector S2j as a comparison result, and outputted to data line DIO via output buffer 20. As a result of this comparison, "1" is output when the above two match.

When TEST=1, the column decoder 7 ignores the column address and sets all decode outputs R, Ej (j=1 to 256) to "1". As a result, the output buffers 20 of all columns are turned on, and the data lines DIO
Above you will get the wired AND of the comparison results for all columns. However, the data line DIO is precharged in advance. Through the above operations, a comparison result indicating whether or not the data in row 256 and row i match is output to data line DIO.

Next, a test operation for the entire RAM will be explained.

(1) Write all “0” to row 256 by normal writing. Row 256 is a reference row.

(n) Transfer the value of row 256 to all other even-numbered rows in a test write.

(I[[) Writes all “1”s in line 256 by normal writing.

(IV) Test write transfers the value of row 256 to all other odd numbered rows. Note that the reason why the same data is displayed every other row is to detect level interference between rows.

(V) Check whether the values of row 256 and all odd-numbered rows match in test reading.

("vT) Write all "0" in line 256 by normal writing.

(■) Check whether the values of row 256 and all other even-numbered rows match during test reading.

By exchanging "0" and "1" and repeating this operation, "0" and "1" are written to all memory cells and checked.In this way, in this embodiment, the memory After writing one row of cell matrix data at a time, it is possible to compare one row of data at a time.This greatly reduces RAM test time and speeds up testing compared to conventional methods. For example, in the case of a 256K x 1 bit (7) RAM with 1 row = IK bits, the test time is approximately 1/1000th of that of conventional RAM.
become. Additionally, the test time is approximately halved compared to RAM, which only has the added function of comparing one row of data at a time.

Next, FIG. 6 is a diagram showing a second embodiment of the present invention.

In the above embodiment, when writing test data, line 25
6, it is necessary to set it for each column. All “1” in one line
Alternatively, if all "O"s are to be written, it is more efficient to write the input data to all columns than to transfer the value in row 256.

Therefore, in this embodiment, when writing test data, the input data is simultaneously written in all digits of a designated line. Its circuit diagram is shown in FIG. In the figure, 29 is an exclusive OR gate, Sj is a selector, and one input terminal of the exclusive OR gate 29 has a column address LS.
B is input.

The column address LSB serves as a comparison reference value for testing, and becomes "0" or "1" depending on the test state. As in the previous embodiment, the subsequent portions including the sense amplifiers 14 of each column 1 to 256 together with the transistors 21 constitute the data control circuit 23 as a whole. The rest is the same as in the previous embodiment.

The operation is as follows, but since normal writing and normal reading are the same as in the previous embodiment, their explanation will be omitted.

Writing of the lame limb prison test is executed by setting the TEST signal to TEST=1 and setting the write enable signal WE to WE=1.

First, data to be written is input to the data line DIO. The row decoder 5 selects one row (row i) specified by the row address.
is selected, and "1" is output to the word line Wi corresponding to that row. The column decoder 7 ignores the column address and outputs 1" to all decode outputs WEj. When WEj=l, the transfer gates G1 j, 02 j turn on. As a result, the write data data line D
The signal passes from the IO to the transfer game) GI L G2j and is output to the B, 7, and T lines Bj and B of each column. Data on bit lines Bj, Bj of each column are taken into memory cells selected by row decoder 5. By the above operation, the same value is written to all memory cells in the i row.

Over base 11 no 1.

Test reading is performed by setting the TEST signal to TEST=1 and the read enable signal RE to RE=1.

At this time, it is determined whether all the rows specified by the row address are "1" or "0°", and the result is output. The row decoder 5 selects one row (row i) designated by the row address and outputs "l" to the word line Wi corresponding to that row. The data of the selected row is transmitted to all bit lines Bj, B
j. The data read onto the bit lines Bj and B is amplified by the sense amplifier 14, and the output line D is amplified by the sense amplifier 14.
output to j. Next, the data on the output line Dj and the data on the column address LSB are sent to the exclusive OR gate 29.
Exclusive OR logic is taken, and as a result of comparison, it is selected by selector Sj, and the output Huffer 20
It is output to the data line DIO via the data line DIO. Column address LSB
When =1, if the read value is "0", it is determined to be a correct value.

If the value is correct, "1" is output from the output buffer 20.

When TEST=1, the column decoder 7 ignores the column address and sets all decode outputs REj to "1". As a result, the output buffers 20 of all columns are turned on, and a wired AND of the determination results of all columns is obtained on the data line DIO. However, the data line DIO is precharged in advance. Through the above operations, a result indicating whether all data in row i are correct values is output to data line DIO.

Next, a test operation for the entire RAM will be explained.

(1) Transfer “0” to all even-numbered lines in test writing.

(n) Transfer "1" to all odd numbered rows by test writing.

(1t[) Test reading shows that all values in even numbered rows are “
Check whether it is 0pa.

(IV) Read the test and all the values in the odd numbered rows are “
Check whether it is 1°.

By exchanging "0" and "1" and repeating this operation, "ON" and "1" are written in all memory cells and checked.Here, all columns in the same row There is a concern that a test in which the same value is written to the bit lines may not be able to detect short circuits in bit lines in adjacent columns.

This depends on the layout of the RAM, but normally the non-inverted bit lines Bj and the inverted bit lines Bj are arranged alternately, so
If the same value is written to each column, short circuits in bit lines in adjacent columns can be detected.

Therefore, this embodiment has the advantage that when writing test data, manually entered data can be written simultaneously to all digits of a designated row, making the test more efficient.

〔Effect of the invention〕

According to the present invention, data for one row of a memory cell matrix can be written at one time and then data for one row can be compared at one time, and the test time for semiconductor memory devices can be significantly reduced compared to conventional methods. It can be shortened to speed up the test.

[Brief explanation of the drawing]

1 to 5 are diagrams showing one embodiment of a semiconductor memory device according to the present invention, in which FIG. 1 is a diagram of its overall configuration, FIG. 2 is a diagram of its one block configuration, and FIG. 3 is its epoch. 4 is a diagram showing a circuit of a column decoder, FIG. 5 is a diagram showing a circuit of one decoder in the column decoder, and FIG. 6 is a diagram showing a semiconductor memory device according to the present invention. FIG. 2 is a diagram showing a specific circuit of one block showing an embodiment of the present invention. 1 to 4...Memory cell matrix, 5.6...
... Row decoder, 7... Column decoder (transfer means, comparison means), M
i, j-M256. j...-Memory cell, GAI, j~G A256. j. (JB 1.j-GB256.j...
・Transfer gate, 14...Sense amplifier, 15.16...Gate, 17.18.41.51.52...Inverter, 19.29... Exclusive OR gate, 20...Output bumper, 21...Transistor, 22.23...Data control circuit, 31-34.
... decoder, 35-40 --- Nantes gate (column selection means),
Bj, Bj---Bit line, Cj, Dj---Output line, Glj, G2j---Transfer gate 1Sl
j, S2j, Sj...Selector, DI○...
-...Data line.

Claims (2)

[Claims] (1) a memory cell matrix that is addressed by row and column; a row decoder that selects one of the rows of the memory cell matrix in response to an address signal; and a row decoder that selects one of the rows of the memory cell matrix in response to an address signal; It has a column decoder that selects one column among them, and a data control circuit that controls writing/reading of data in a memory cell corresponding to the selected row and column, and the data control circuit receives a write instruction when in a test mode. a transfer means for transferring all data written in one specific row of the memory cell matrix in response to a signal to another row selected by a row decoder; and one of the memory cell matrices read in response to the read instruction signal. A semiconductor memory device comprising: comparison means for detecting whether or not the data of a row matches the data of the specific one row. (2) In the semiconductor memory device, the column decoder includes column selection means that can select all columns, and when in the test mode, the data control circuit selects a specific one of the memory cell matrix by the column selection means. row and other 1
The same data written in all rows is
A semiconductor memory device characterized in that the comparison means compares data in a row to determine whether data in the other row matches.