JPH0413375A - Synchronizing separator circuit - Google Patents

Abstract

PURPOSE:To attain stable synchronization by ANDing an output of a delay circuit retarding a composite synchronizing signal with the composite synchronizing signal for a prescribed time so as to extract a vertical synchronizing signal and ANDing an output of an inverting circuit inverting an output of the delay circuit with the composite synchronizing signal. CONSTITUTION:A composite synchronizing signal as shown in figure (a) is inputted to a composite synchronizing signal input terminal 1. The composite synchronizing signal is delayed by a delay circuit 4 and outputted in a waveform as shown in figure (b). An output of the delay circuit 4 and the composite synchronizing signal are inputted to a 1st AND circuit 6, which extracts a vertical synchronizing signal portion and the result is outputted to a vertical synchronizing signal output terminal 2. On the other hand, the output of the delay circuit 4 is inputted also to an inverting circuit 5, the output of the inverting circuit 5 is inputted to a 2nd AND circuit 7 together with the composite synchronizing signal. Then a horizontal synchronizing signal portion is extracted and the result is outputted to a horizontal synchronizing signal output terminal 3. Thus, vertical and horizontal synchronizing signals are separated from the composite synchronizing signal with excellent reproducibility and stable synchronization is implemented.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a synchronization separation circuit for separating horizontal synchronization signals and vertical synchronization signals used in television receivers, display devices, and the like.

BACKGROUND OF THE INVENTION In recent years, so-called AV equipment, which is a device for reproducing software that combines audio data and video data, has become more sophisticated, with a focus on larger displays.

(As mentioned above, as the playback screen of the video display section has become larger and the resolution has become higher, defects in the playback screen have become very noticeable, and various performance improvements have been made. Regarding the synchronization relationship, various improvements have been proposed because if the synchronization becomes even slightly unstable, the screen will fluctuate and the image quality will drop significantly.

Conventionally, a synchronization separation circuit for separating this synchronization signal from a video signal has a configuration as shown in FIG.

As shown in FIG. 3, a composite synchronizing signal is input to a composite synchronizing signal input terminal 1, and a vertical synchronizing signal is outputted to a vertical synchronizing signal output terminal 2 via an integrating circuit 8.

Also, the horizontal synchronization signal output terminal 3 is the output of the horizontal synchronization signal.
is passed through the differentiation circuit 9. 4(a) shows the waveform of the composite synchronizing signal input to the composite synchronizing signal input terminal 1 of FIG. 3, and FIG. 4(b) shows the vertical synchronizing signal of the vertical synchronizing signal output terminal 2 of FIG. FIG. 4(C) is the horizontal synchronizing signal waveform of the horizontal synchronizing signal output terminal 3 in FIG.

The relationship and operation of the circuit components will be explained below with reference to these drawings. When the composite sync signal shown in FIG. 4(a) is input to the composite sync signal input terminal 1 of FIG. 3, the composite sync signal is input to the integrating circuit 8 and the differentiating circuit 9. The integrating circuit 8 generally consists of a resistor, a capacitor, etc., and integrates the input composite synchronization signal and outputs it to the vertical synchronization signal output terminal 2.
The waveform shown in FIG. 4(b) is output. The differentiating circuit 9 also generally consists of a resistor, a capacitor, etc., and differentiates the input composite synchronizing signal, and outputs the waveform shown in FIG. 4(C) to the horizontal synchronizing signal output terminal 3.

In this way, the composite synchronization signal can be separated into a vertical synchronization signal and a horizontal synchronization signal.

Problems to be Solved by the Invention In such a conventional configuration, the vertical synchronizing signal waveform shown in FIG. 4(b) and the vertical synchronizing signal waveform shown in FIG. Since the horizontal synchronization signal waveform shown in (C) is considerably different from the respective ideal synchronization signal shapes, the vertical and horizontal synchronization stability deteriorates, resulting in an inconvenience that the synchronization becomes unstable.

The present invention takes these problems into consideration and provides a vertical synchronization signal that can perform stable vertical and horizontal synchronization.

The present invention aims to provide a synchronization separation circuit that can obtain a horizontal synchronization signal.

Means for Solving the Problems In order to achieve the above object, the present invention extracts a vertical synchronization signal by logically multiplying the output of a delay circuit that delays a composite synchronization signal by a predetermined time and the composite synchronization signal, and outputs the vertical synchronization signal using the same delay circuit. This is a synchronization separation circuit that inputs the output of the horizontal synchronization signal to an inverting circuit that inverts it, and extracts the horizontal synchronization signal by ANDing this output with the composite synchronization signal.

The configuration includes a delay circuit that delays a composite synchronization signal by a predetermined time, a first AND circuit that takes the logical product of the output of this delay circuit and the composite synchronization signal, and an inversion circuit that receives the output of this delay circuit as an input. , a second AND circuit that takes the logical sum of the output of the inverting circuit and the composite synchronization signal;
This is a synchronization separation circuit in which the output of the D circuit is used as a vertical synchronization signal, and the output of the second AND circuit is used as a horizontal synchronization signal.

Furthermore, in the above synchronization separation circuit, the delay time caused by the delay circuit is longer than the pulse width of the horizontal synchronization signal and does not exceed the period of the horizontal synchronization signal.

Effect The synchronization separation circuit of the present invention having the above-mentioned configuration has a composite synchronization signal that is
When the signal is delayed by a predetermined time and input to the first AND circuit together with the original composite synchronization signal, if this delay time is greater than or equal to the pulse width of the horizontal synchronization signal, the horizontal synchronization is achieved at the output of the first AND circuit. The signal portion is not output, and the vertical synchronization signal, which has a wider pulse width than the horizontal synchronization signal, is output, although the pulse width has changed slightly. Also, when this delayed signal is inverted and input to the second AND circuit in the same way, only the horizontal synchronization signal part has both signals at 1 value (High).
Therefore, the horizontal synchronization signal is output as is.

In addition, by setting the delay time by the delay circuit to be greater than or equal to the pulse width of the horizontal synchronization signal and less than its period, the horizontal synchronization signal portion of the composite synchronization signal delayed by the delay circuit is changed to the composite synchronization signal portion before the delay. , there is no temporal overlap, and reliable synchronization separation is performed without noise.

Embodiment FIGS. 1 and 2 (a) to (e) are timing charts showing a synchronization separation circuit and waveforms of essential parts thereof according to an embodiment of the present invention.

As shown in FIG. 1, a composite synchronizing signal is input to a composite synchronizing signal input terminal 1 and distributed to a delay circuit 4, a first AND circuit 6, and a second AND circuit 7. The output of the delay circuit 4 is input to a first AND circuit 6, and the output of the first AND circuit 6 serves as the vertical synchronization signal output terminal 2. The other output of the delay circuit 4 is input to a second AND circuit 7 via an inversion circuit 5, and the output of the second AND circuit 7 serves as the horizontal synchronization signal output terminal 3.

2(a) is the composite synchronizing signal waveform, FIG. 2(b) is the output waveform of the delay circuit 4, FIG. 2(Cc) is the output waveform of the inverting circuit 5, and FIG. The waveform of the vertical synchronizing signal output terminal 2, FIG. 4(e) is the waveform of the horizontal synchronizing signal output terminal 3 of FIG.
This is the waveform of

The related operations of the circuit components will be described below with reference to these drawings.

In Figure 1, the composite synchronization signal input terminal 1 is connected to the composite synchronization signal input terminal 1 in Figure 2 (a).
) Input the composite synchronization signal shown in The composite synchronization signal is delayed by the delay circuit 4 and output in the waveform shown in FIG. 2(b). The time delayed by the delay circuit 4 is
Since the pulse width of the horizontal synchronization signal is approximately 4 to 5 μSec, the width is approximately 6 μsec to several μSec. The output of the delay circuit 4 and the composite synchronization signal are input to the first AND circuit 6, and the AND circuit 6 calculates the logical product of the respective signals as shown in FIG. 2(d) because the horizontal synchronization signal portion is shifted. The horizontal synchronizing signal part disappears, and the vertical synchronizing signal part is extracted and output to the vertical synchronizing signal output terminal 2 in FIG. 2. On the other hand, the output of the delay circuit 4 is also input to the inverting circuit 5, and the output of the inverting circuit 5 has the waveform shown in FIG. By means of the circuit 7, only the horizontal synchronization signal portion of the logical product of each signal is set to 1 value (High).
Therefore, the waveform becomes as shown in FIG. 2(e), and the horizontal synchronizing signal portion is extracted and output to the horizontal synchronizing signal output terminal 3 in FIG. In this way, the vertical synchronization signal and the horizontal synchronization signal are separated and extracted from the composite synchronization signal with good reproducibility, and stable synchronization is performed.

Effects of the Invention As is clear from the above description, according to the present invention, a vertical synchronization signal is extracted by logically multiplying the output of a delay circuit that delays a composite synchronization signal by a predetermined time and the composite synchronization signal, and By taking the AND of the output of the inverting circuit that inverts the output of the inverter and the composite sync signal to extract the horizontal sync signal, the vertical sync signal and horizontal sync signal can be separated from the composite sync signal with good reproducibility and stable synchronization can be achieved. You can get the effect of being covered.

In addition, the delay time caused by the delay circuit is
By setting the value to a value that is equal to or larger than the width of the horizontal synchronizing signal and does not exceed the period of the horizontal synchronizing signal, reliable synchronization separation without noise can be performed.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a synchronous separation circuit according to an embodiment of the present invention, Fig. 2 is a timing chart showing signal waveforms at each point in the same embodiment, and Fig. 3 shows a synchronous separation circuit with a conventional configuration. The block diagram and FIG. 4 are timing charts showing signal waveforms at various points in a conventional synchronous separation circuit. 4... Delay circuit, 5... Inverting circuit, 6
. . . 1st AND circuit, 7 . . . 2nd AND circuit. Name of agent: Patent attorney Shigetaka Awano (1 person) Figure 2 Shima

Claims (2)

[Claims] (1) a delay circuit that delays a composite synchronization signal by a predetermined time; a first AND circuit that takes a logical product of the composite synchronization signal and each signal of the output delayed by the delay circuit; and a delay circuit that delays the composite synchronization signal by the delay circuit. an inverting circuit into which the output of the input signal is input; and a second AND circuit that performs a logical product of the output of the inverting circuit and each of the composite synchronization signal inputs, the output of the first AND circuit. A synchronization separation circuit in which a vertical synchronization signal is used as a vertical synchronization signal, and an output of the second AND circuit is used as a horizontal synchronization signal. (2) The synchronization separation circuit according to claim 1, wherein the delay time by the delay circuit is equal to or longer than the horizontal synchronization pulse width and does not exceed the horizontal synchronization period.