JPH04134827A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve reliability and reduce wiring capacitance by preventing any cavity from being produced by forming a reverse tapered groove in an interlayer insulating film on a semiconductor substrate correspondingly to a wiring pattern and burying the groove with a wiring material. CONSTITUTION:A groove corresponding to a wiring pattern is formed in an interlayer insulating film 2 deposited on a semiconductor substrate 1 with a wiring shape thereof being reversely tapered. Thereafter, wiring is formed by burying the groove with a single or a plurality of layers of a wiring material 3. With the resulting reverse taper-shape, burying of the wiring material into the groove is facilitated to restrict cavity production for improvement of reliability and reduction of wiring capacitance. Further, flattening of the top layer is facilitated.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) This invention involves forming a tapered groove corresponding to a wiring pattern in an insulating film on a semiconductor substrate, and inserting wiring into the groove. A buried interconnect is formed by embedding the material.

The present invention relates to a method for forming wiring in a semiconductor device.

(Prior Art) When the wiring becomes sub-micron level or less, when the wiring is formed using the conventional technology, it becomes difficult to planarize the upper insulating film as shown in FIG. One way to solve this problem is to use forward taper etching for wiring as shown in Figure 5. However, by using forward taper etching, the capacitance of adjacent wiring increases, resulting in a rapid increase in wiring capacitance as shown in Figure 6. occurs.

This becomes even more remarkable as wiring becomes finer. Since the wiring capacitance has a great effect on the operating speed of the LSI, it must be made as small as possible, and forward taper etching of the wiring is undesirable from the point of view of the wiring capacitance. From the point of view of wiring capacitance, it is considered more advantageous to form the wiring into a reverse tapered shape, but if the wiring is formed into a reverse tapered shape, it becomes increasingly difficult to form an interlayer insulating film.

Furthermore, when wiring is formed in a buried manner, flatness is good, but as the aspect ratio increases, cavities are likely to occur inside the wiring. This situation is shown in FIGS. 7(a) to 7(C) and FIGS. 8(a) to 8(b). In FIG. 7(a), an interlayer insulating film 2 is deposited on a substrate 1, and after resist coating, mask alignment, exposure, and development steps, the interlayer insulating film 2 is etched using the resist as a mask. FIG. 7(b) shows the wiring material 3 deposited on the etched interlayer insulating film 2. As shown in FIG. FIG. 7(C) is a diagram in which the wiring material 3 has been etched up to the interlayer insulating film 2, and the wiring material 3 is deposited in the groove. By embedding the wiring in the interlayer insulating film in this way, a flat shape can be obtained.

However, FIG. 8(a) shows a case where the aspect ratio of the trench is increased in FIG. 7, and the step coverage of the wiring material 3 is poor, and a cavity is formed inside the trench. If the wiring material 3 is etched down to the interlayer insulating film 2 in this state, the wiring will become concave (Fig. 8(b)) or a cavity will be formed inside the wiring, resulting in problems in terms of flatness, reliability, and resistance. It becomes a problem.

(Problem to be Solved by the Invention) When forming sub-micron level interconnects in an embedded manner using conventional methods, cavities will occur inside the interconnects as the aspect ratio increases, causing reliability problems. . Therefore, by tapering the groove in which the wiring is formed, the generation of cavities is suppressed and reliability is improved. At the same time, it is an object of the present invention to provide a method of forming a wiring that can reduce the wiring capacitance by forming the wiring into an inverted tapered shape.

[Structure of the Invention] (Means for Solving the Problems) A groove corresponding to a wiring pattern is formed in an interlayer insulating film deposited on a semiconductor substrate so that the groove is tapered so that the wiring shape has an inversely tapered shape. Thereafter, the trench is filled with a single layer or multiple layers of wiring material to form a reverse tapered wiring.

(Function) By embedding the wiring in the lower layer insulating film, the level difference in the wiring is eliminated, making it easier to planarize the upper layer. Further, by tapering the groove in which the wiring is formed so that the wiring has an inversely tapered shape, it becomes easy to fill the wiring material into the groove, and at the same time, the wiring capacitance can be reduced.

(Example) A first example of the present invention is shown in FIGS. 1(a) to 1(C). FIG. 1(a) shows an interlayer insulating film 2 on a semiconductor substrate 1.
is deposited, followed by resist application, mask alignment, exposure,
After the development process, the interlayer insulating film 2 is taper-etched so that the wiring has a reverse tapered shape, and a groove corresponding to the wiring pattern is formed in the interlayer insulating film 2. In this state, wiring material 3 is deposited as shown in FIG. 1(b). Since the groove is tapered, the wiring material 3 can be deposited easily. FIG. 1(e) shows the wiring material 3 that has been etched up to the interlayer insulating film 2. The wiring material 3 is embedded in the groove, and a flat surface is obtained at the same time as the wiring is formed. There is.

As a second embodiment, a case where a plurality of wiring layers are used in order to improve reliability etc. is shown in FIGS. 2(a) to 2(b).

FIG. 2(a) shows a state in which two layers of wiring materials 3, eg TIN, 4, eg Ai) have been deposited, and FIG. Now, the wiring has been formed.

The third embodiment is shown in FIGS. 3(a) to 3(e).

FIG. 3(a) shows a first plate that can be electrolessly plated on the entire surface of the interlayer insulating film 2, including the grooves formed by taper etching.
The wiring material 5, for example TIN, has been deposited relatively thinly. After that, resist 6 is applied only to the groove where the wiring will be formed.
Fig. 3(b) shows the result in which the image was processed so as to leave the above. Here, by etching the entire surface, the first wiring material 5 that can be electrolessly plated is left at the bottom or the bottom and sides of the trench, and after peeling off the resist 6, electroless plating is performed.
FIG. 3(C) shows the trench filled with a second wiring material 7 such as Cu or NiCo. Here, the buried layer may be a single layer or multiple layers. Alternatively, the trench may be filled by selectively growing the second wiring material 7. in this case,
The first wiring material is appropriately selected depending on the material to be selectively grown.

As the contact size becomes finer and the aspect ratio exceeds 1, if the contact is formed using the conventional technology, as shown in FIG. The material becomes thinner and the metal is cut at different levels. Furthermore, if the thickness of the metal on the side of the contact becomes thinner, reliability also becomes a problem.

In order to solve these problems, it is effective to embed metal in the contact, and in order to deal with finer contacts, selective growth of W or the like by CVD is effective. However, at this time, there is no difference in embedding depth due to the difference in contact diameter, but if there are contacts with different contact depths due to differences in the underlying step, it is not possible to embed both shallow and deep contacts at the same time. Can not.

This situation is shown in FIGS. 15(a) and 15(b). FIG. 15(a) shows a case where a contact is opened in the gate 8 on the diffusion layer 2 and the field 7, and the contact is buried by selective growth using CVD to match the shallower side of the contact. . In this case, a step remains on the deeper side of the contact. FIG. 15(b) shows a case where a contact is buried according to the deeper side of the contact by a process similar to that of FIG. 15(a). In this case, the material buried in the shallower contact will overflow.

In addition, in selective growth by CVD, the base material (single crystal S
There are problems such as that the growth rate differs depending on the type of diffusion layer (such as whether S1 is polycrystalline S1) or the type of diffusion layer, and that the underlying layer is destroyed.

As described above, as the contact size becomes finer and the aspect ratio of the contact exceeds 1, when the contact is formed by sputtering, which is the conventional technology, shards occur inside the contact, and the wiring material (
As metal materials (metal materials) become thinner, reliability becomes a problem. Furthermore, in selective growth by CVD, it is difficult to embed contacts of different depths at the same time. Therefore, by forming a base metal on the bottom or side of the contact after opening the contact, and then selectively embedding a metal material, contacts having different contact depths can be buried at the same time, and a highly reliable contact can be obtained. At this time, by tapering the opening of the contact so that it becomes narrower toward the bottom of the contact, the base metal can be deposited with good uniformity even in a contact with a high aspect ratio.

Here, a contact is placed on an interlayer insulating film deposited on a semiconductor substrate, with the shape of the contact increasing toward the bottom of the contact.
A buried contact is created by tapering the opening to make it narrower, forming a base metal on the bottom or side of the contact, and then selectively filling the contact with a single layer or multiple layers of metal material. Form.

By embedding the contact with a metal material, it is possible to prevent the formation of debris inside the contact, and it is also possible to prevent the metal material from becoming a thin film on the contact sidewall, improving reliability. . Furthermore, since there is no step difference on the contact, it becomes easier to planarize the upper layer. By forming a base metal on the bottom or side of the contact, it is possible to embed contacts with different contact depths at the same time, and by tapering the contact opening, even contacts with a high aspect ratio can be buried under the base metal. It becomes possible to form metal with good uniformity.

Examples of the present invention are shown in FIGS. 9(a) to 9(d).

FIG. 9(a) shows that an interlayer insulating film 3 is deposited on a semiconductor substrate 1 on which a diffusion layer 2 has been formed, and then resist coating, mask alignment, exposure, and development steps are performed to form a tactile bottom part on the interlayer insulating film 3. A contact is opened with a taper so that it becomes narrower, and a relatively thin layer of base gold H4 is deposited on the entire surface of the interlayer insulating film 3. At this time, the base metal is, for example, Al! .

TlSi. , TIN, polycrystalline 81. It contains at least one of νS1° and νN, and may be a single layer or multiple layers. Since the contact is tapered, the underlying metal can be deposited with good uniformity even on contacts with a high aspect ratio. After that, the resist 5 was left only in the contact hole as shown in Figure 9 (
b). By etching the entire surface, the underlying metal 4 is left at the bottom or side of the contact hole and removed from the resist 5, as shown in FIG. 9(C). FIG. 9(d) shows a state in which the metal material 6 is then selectively filled into the contact hole. Materials used for contact embedding include, for example, AI, Au, Cu, W, and Zn.
, N1. It contains at least one of Co and Pd, and the buried layer may be a single layer or a plurality of layers. As a method for selectively embedding metal, selective CVD method, electroless plating method, etc. are used. If electroless plating method is used, if necessary, heat treatment in N2 in a vacuum with A This removes moisture contained in the plating layer.

FIG. 10 shows a state where a contact opened on the diffusion layer and a contact opened on the gate on the field (contacts having different depths) are buried at the same time. Since the base metal 4 is formed not only on the bottom of the contact but also on the side thereof, contacts having different contact depths can be buried at the same time.

Similar effects can be obtained when the above process is used for contacts (Via) on wiring.

Figures 11(a) to 11(d) show an example of forming wiring in a similar manner after embedding contacts.
). FIG. 11(a) shows that after contacts have been buried by the method described above, an interlayer insulating layer 119 is deposited, and a resist 10 is patterned through resist coating, mask alignment, exposure, and development steps.

FIG. 3-2 shows an interlayer insulating film 9 using the resist 10 as a mask.
A groove corresponding to the wiring pattern has been formed on the wafer.

In this case, the etching of the groove corresponding to the wiring pattern is
Although it is desirable to stop the etching just above the contact, the bottom of the wiring groove may be uneven as shown in FIG. 11(b) due to over-etching. After forming the wiring trench, a base metal 4 is formed on the bottom and sides of the trench as shown in FIG.
e). FIG. 11(d) shows the state in which the metal material 6 is then selectively embedded. Here, the embedding layer is
It may be a single layer or multiple layers. In addition, if contacts and wiring are formed using electroless plating, it is possible to
Moisture contained in the plating layer is removed by heat treatment in N2, Ar, or the like.

FIG. 12 shows a case where misalignment occurs between the contact and the wiring. Further, FIG. 13 shows a case where the wiring width is narrower than the contact size. By using this method, it is possible to eliminate the alignment margin between contacts and wiring, and high integration is expected.

[Effects of the Invention] According to the present invention, by forming an embedded reverse tapered wiring, it is possible to eliminate the level difference in the wiring, and the upper layer can be easily flattened. Furthermore, since an increase in the capacitance of adjacent wirings can be suppressed, the overall capacitance of the wirings is reduced. Furthermore, when forming the embedded wiring, since the groove in which the wiring is formed is tapered, the step coverage of the wiring is improved and the possibility of forming a cavity inside the wiring is reduced.

Therefore, reliability is improved.

Furthermore, by embedding the contacts, it is possible to prevent the generation of whiskers inside the contacts, and it is also possible to prevent the metal material from becoming a thin film on the side walls of the contacts, thereby improving reliability. Furthermore, since there is no step difference on the contact, it becomes easier to planarize the upper layer. Further, according to the present invention, it is possible to simultaneously embed contacts having different contact depths, which simplifies the process.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention, and FIG. 2 is a sectional view showing an embodiment of the present invention. FIG. 3 is a sectional view showing another example, FIGS. 4 and 5 are sectional views showing a comparative example, FIG. 6 is a diagram showing simulation results of wiring capacitance, FIG. FIG. 8 is a diagram showing a comparative example, FIG. 9 is a sectional view, FIG. 1O, and FIG. 11 are diagrams showing other embodiments of the present invention. 12 and 13 are cross-sectional views showing other embodiments, and FIG. 14 is a sectional view showing another embodiment.
The figure and FIG. 15 are cross-sectional views showing a comparative example.

Claims (5)

[Claims] (1) A wiring forming method for a semiconductor device includes a step of forming a groove corresponding to a wiring pattern in an interlayer insulating film on a semiconductor substrate with a reverse taper so that the wiring shape has a reverse taper shape; 1. A method of manufacturing a semiconductor device, comprising a step of forming wiring by embedding it with a material. (2) The method for manufacturing a semiconductor device according to claim 1, wherein the wiring structure has a single layer structure or a multilayer structure. (3) A contact forming method for a semiconductor device includes a step of forming a contact so that the contact has a narrow taper shape at the bottom, and forming a base metal on the bottom or side of the contact, and then forming a contact with a metal material. 1. A method of manufacturing a semiconductor device, comprising a step of forming a contact by selectively burying the contact. (4) Claim 1 characterized in that the metal material is embedded using a selective CVD method or an electroless plating method.
A method of manufacturing the semiconductor device described above. (5) The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the buried layer of the contact has a single layer structure or a multilayer structure.