JPH04139877A - Gallium arsenide fet integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit using a field effect transistor (ET) on a gallium arsenide substrate.

[Conventional technology]

In high-speed integrated circuits using m-group compound semiconductors such as gallium arsenide (GaAs), transistors are formed on semi-insulating semiconductor substrates.

[Problem to be solved by the invention]

A semi-insulating compound semiconductor substrate includes a large amount of deep levels in the substrate, and when an external electric field is applied, charges move in and out of the deep levels, generating space charges. This space charge greatly affects the characteristics of elements formed on the substrate surface.

It has long been known that in integrated circuits using FET-based devices such as GaAs-MESFETs, there is a characteristic interference effect between elements called a side gate effect.

A typical side gate effect will be explained with reference to FIG.

Focusing on the N-channel FET 2 on the surface of the semi-insulating substrate 1, a negative potential is applied to the adjacent element 3 (corresponding to the N-type layer of the adjacent FET, etc., and this is called a side gate) (and the FET 2 The source of this side gate effect is the space charge at the interface between the N-type layer and the substrate 1.

An object of the present invention is to provide an integrated circuit structure that can suppress side gate effects that occur when FETs are formed on the surface of a semi-insulating substrate.

[Means to solve the problem]

The FET integrated circuit using gallium arsenide as a substrate of the present invention has the following features:
It is characterized in that a light emitting element that emits light with an energy in the range of 1.0 to 1.4 eV is incorporated into the same package.

[Effect]

Consider the situation when an N-channel F'ET is fabricated directly on a semi-insulating substrate.

An N-I junction in which an N-type channel and a semi-insulating substrate are joined has an energy band tr+$ as shown in FIG. 5, which is similar to a P-N junction.

The Fermi level of the N-channel is just below the bottom of the conduction band, and the Fermi level of the semi-insulating substrate is near the center of the forbidden band.

When no voltage is applied from the outside (thermal equilibrium state), the Fermi levels of both coincide. The conduction band and the valence band have a potential step near the N-I interface.

This potential step is created by charges generated on both sides of the N-I interface. On the semi-insulating substrate side, a deep level in the substrate is charged and negative space charge is accumulated with a width of W, and on the N channel side, free electrons are accumulated by d to cancel out the negative charge.
(Poisson's equation suggests that the potential step is proportional to the square of the width W and d of the charged region).

When a negative potential is applied to the semi-insulating substrate side, this N-I junction becomes in a state similar to a reverse-biased P-N junction, and the potential step difference between the conduction band and the valence band increases. Therefore, the width W of the negatively charged region on both sides of the N-T interface
and the width d of the positively charged region respectively increases.

Viewed from the N-channel side, the widening of d, which is the depletion layer width, narrows the channel region where free electrons exist.

If this N channel is the operating channel of the FET, channel pinching means a decrease in the drain current of the FET, which explains the state in which the side gate effect occurs.

However, in FET integrated circuits, the adjacent elements (
side gates) are separated by several μm or more. Therefore, a special mechanism is required for the voltage applied to this side gate to affect the N-1 junction of the F'ET of interest and cause the side gate effect.

In the case of N-channel FETs, one mechanism for this is the presence of deep levels in the semi-insulating substrate that act as hole traps.

When a negative voltage is applied to the side gate, a portion of the voltage reaches the N-I interface on the back surface of the FET channel, creating a weak reverse bias.

Regarding the free carrier concentration inside the potential step near the N-I interface (region where the potential is tilted),
Drift of free carriers due to electric field (electrons from inside the step go to the N channel, holes go to the semi-insulating substrate) and diffusion due to differences in carrier preparation (electrons go from the N channel to the inside of the step, holes go to the semi-insulating substrate) (from the substrate to the inside of the step), and the free carrier concentration becomes a constant value.

In a reverse bias state, the electric field (potential gradient) at this N-1 interface increases, so only the drift of free carriers increases, and electrons near the NI interface move toward the N channel side, and holes move toward the semi-insulating substrate. excluded by the side.

That is, within the potential step near this N-I interface, both free electrons and free holes are depleted compared to the case where no side gate effect voltage is applied.

As shown in Figure 6, if there is something cloudy as a hole trap in a deep level in a semi-insulating substrate, that deep level will become cloudy due to the depletion of free holes near the N-I interface. It releases holes and becomes negatively charged, resulting in the accumulation of extra negative charges near the N-I interface.

The charging continues until the reverse bias voltage of this N-1 junction becomes equal to the side gate voltage, and the side gate voltage reaches -0- directly to the N-■ junction.

FIG. 3 shows the relationship between the energy of light irradiation, the side gate voltage Ov, and the drain current of the FET at -4V.

When no light is irradiated and the energy of the irradiated light is 1
．． When the side gate voltage is below OeV, a decrease in the drain current of F'ET is observed compared to when the side gate voltage is OV.

On the contrary! When the j6 emitted light is 1.0 to 1.4 eV, no decrease in drain current is observed.

Further, when the irradiation light has an energy of 1.4 eV or more, a decrease in drain current is also observed.

This is according to the following machine +14 Hl(/ll
1l is given.

The deep level that becomes cloudy as a hole trap releases holes to the valence band and captures electrons from the valence band on the semi-insulating substrate side (I side) of the N-I junction of the FET channel, becoming negatively charged. This causes a side gate effect.

As shown in Figure 4, in the case of a GaAs substrate fabricated by the LEC method, there is an EL2 near the center of the forbidden energy band.
There is a deep donor level 4 called , which determines the Fermi level inside the substrate. Level 5, which functions as a hole trap, also exists near this region, and is located at a position of about 0.7 eV from the valence band.

By the way, in addition to these levels, a deep level 6 exists in the GaAs substrate at a position about 0.4 eV from the valence band. (For example, Spring 1990 Proceedings of the Japan Society of Applied Physics 109
0 page, 29p-P-2) Light irradiation with an energy of 1. OeV or more enables a transition from the valence band to the conduction band and the 0.4 eV level 6.

This level 6 of 0.4 eV is below the Fermi level in the absence of light irradiation and should be filled with electrons (completely depleted of holes), but 1. Due to the transition caused by light of OeV or more, these electrons are released into the conduction band and become positively charged.

It is thought that this positive charging cancels out the negative charging of the hole trap level 5 and suppresses the decrease in the drain current of the FET.

As shown in Figure 6, this positive charging is caused by the potential difference of the N-■ junction on the left, the diffusion potential difference of N-I (the potential step on both sides of the N-I interface at the applied voltage OV, shown in Figure 5). continues until it becomes equal to .

Since positive charging does not proceed any further, the drain current of the FET does not increase more than necessary compared to when the side gate voltage is OV.

〔Example〕

Next, one embodiment of the present invention will be described with reference to FIGS. 1 and 2.

This is a GaAs integrated circuit using an N-type MESFET,
It is combined with an InP light emitting diode (LED) with an energy of 1.24 eV as a light emitting element.

An N-type channel layer is formed by silicon (Si) ion implantation, and a gate electrode made of tungsten is formed to form a G
It constitutes an aAs MESFET.

The light emitting diode is manufactured separately from the GaAs substrate and housed in the same casing during assembly.

As shown in FIG. 1, the G, aAs integrated circuit and the light emitting diode can be placed adjacent to each other on the case 7.

Alternatively, it may be attached to the cap 8 facing directly above the GaAs integrated circuit, and more light is irradiated onto the integrated circuit, increasing the effect.

Figure 2 shows how to create an integrated circuit using InP light emitting diodes.
It was made integrally with an aAs substrate. InP
The part is formed by epitaxial growth on the second part of the GaAs 1iξ plate. Since InP has a lattice mismatch with GaAs, a buffer layer 9 is first deposited between it and GaAs.

This light emitting diode is made of InGaAs or nGaA.
It may also be made of an sp-based mixed crystal. In this case as well, the substrate of the light emitting diode portion is InP.

Further, the present invention is applicable to H
MESF is also used for EMT and other hetero MIS type FETs.
The same applies as in the case of ET.

10- [Effects of the Invention] As explained above, the present invention generates positive charges by light from the light-emitting element of a specific wavelength incorporated in the device, and eliminates the negative charges generated due to the negative potential of the adjacent FET. cancel out the charges.

As a result, it becomes possible to suppress the side gate effect.

[Brief explanation of drawings]

1 and 2 are cross-sectional views showing the structure of the integrated circuit of the present invention, FIG. 3 is a graph showing the characteristics of the drain current with respect to the irradiation light energy of the single FET in the integrated circuit of the conventional structure and the present invention, and FIG. The figure is an energy band diagram showing the energy of deep levels in the semi-insulating substrate in the conventional structure and the present invention, and Figure 5 is the FE of the conventional structure and the present invention.
An energy band diagram near the N-I interface of T, Figure 6 is an energy band diagram showing the potential energy between the FET and the side gate in the conventional structure, and Figure 7 explains the side gate effect of the conventional FET. FIG. 1... Semi-insulating substrate, 2... N-channel FET, 3...
...Side gate, 4...Deep level in semi-insulating substrate (
EL2), 5... deep level in the semi-insulating substrate (hole trap level), 6... deep level in the semi-insulating substrate, 7...
- Case, 8... Cap, 9... Buffer layer.

Claims (1)

[Claims] An FET integrated circuit using gallium arsenide as a substrate, characterized in that a light emitting element that emits light with an energy in the range of 1.0 to 1.4 eV is incorporated into the same package.