JPH04141724A - Display signal converter - Google Patents

Abstract

PURPOSE:To execute display on a second display device at high speed without disturbing the screen display while adding new display contents to the display contents of an original display device by externally writing/reading data in/out of a memory when an ineffective period is detected. CONSTITUTION:A synchronizing signal 27 (a high-level flyback period) for a second display device (CRT) 25 is inputted to a memory control circuit 14a. By making use of the ineffective period for write/read provided in the flyback period of the CRT 25 for the purpose of balancing between the write and read of a memory 1, the write from a CPU 1 to the memory 17 is executed. That is, by making use of the flyback period from the CRT 25, data is written from the CPU 1 into an arbitrary address in the memory 17 and displayed on the CRT 25 while adding the arbitrary data to it. Thus, display can be executed on the second display device 25 at high speed without disturbing the screen display while adding the new display contents to the contents displayed on the original display device 8.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a display signal conversion device using a memory, and in particular, when a second display device is installed in a personal computer, it generates display information on the second display device. Use a display signal conversion device suitable for this purpose.

[Prior Art] Conventionally, in a personal computer or the like, a second display device is provided in addition to the original display device, and a display signal conversion device is used to display the same content as the original display on this display device. . Conventional examples of this display signal conversion device include rHD6
6840 LVIC Application Note, Hitachi, Ltd. Semiconductor Division (September 1986), and FIG. 5 is a block diagram showing its configuration. In the same figure, a display circuit 4 has a video memory etc. therein, and is connected to a CPU 1 via a data bus 2 and an address bus 3.
The synchronization signal 5, dot clock 6, and display data 7 are generated from the information sent from the original display! ! Display is performed on a liquid crystal panel 8.

In addition to this liquid crystal panel 8, a CRT as a second display device
25, the output of the display circuit 4 cannot be directly connected to the CRT 25 because a liquid crystal panel and a CRT generally require different display timings. For this purpose, a display signal converter 30 is provided to control the CRT 25 at separate and independent timing. The operation will be explained below.

In FIG. 5, when display data 7 (serial data) is output, the SP converter 10 converts it into parallel data. In this example, assuming that the parallel data congestion is 8 minutes) of display data, the SP converter 10
Every time display data for a dot is input, it is converted into parallel data and set in the latch 11. At the same time, the divide-by-8 circuit 12 divides the 608 dot clocks into 1
This is the write request signal]3
The write counter 15 counts this signal 13 and updates the write address of the memory 17.

Memory control circuit 14 to which write request signal 13 is input
gives the address indicated by the counter 15 of the memory 17 to the memory 17 via the switch 16, and writes the contents of the latch 11.

On the other hand, the oscillator 20 outputs a dot clock 26 whose period is the time per dot when displaying on the CRT 25. This signal is inputted to the divide-by-8 circuit 21, where the frequency is divided by 8, and is input to the memory control circuit 14 as a read request signal 22, and at the same time, the read counter 23 is updated. In response to this request, the memory control circuit 14 provides the output address of the counter 23 to the memory 17 via the switch 16, and reads data at that address from the memory 17 and sends it to the UPS converter 24. The PS converter 24 converts this data into serial data and outputs it to the CRT 25 as display data.

In this way, the dot clock 6 from the display circuit 4, that is, the data for every 8 dots on the liquid crystal panel 8, is loaded into the memory 17, and the data for every 8 dots on the CRT 25, that is, the 8 clocks of the oscillator 20, is stored in the memory 17. 81+W data is read from the memory 17 and displayed on the CRT 25, and the difference in display timing between the liquid crystal panel 8 and the CRT 25 is adjusted using the memory 17 as a buffer. In this operation, since the dot clock 6 and the output of the oscillator 20 are generally completely asynchronous, memory control is performed in synchronization with the earlier dot clock to prevent display data from being written or read. Ru. FIG. 6 is a timing chart showing memory control when the frequency of the dot clock 26 is higher than the dot clock 6. The memory control circuit 14 divides one period of the faster memory read signal 22 into the memory read period and the memory write period. It is divided into two parts and controlled. That is, when the read request signal 22 is generated at time t1, the memory control circuit gi! 114 starts the read operation of the memory 17 at that point. Then, at time t2 when the memory read operation is completed, the state of the write request signal 13 is checked. The write request signal 13 is generated at time t asynchronously with the memory operation.
Since it has already occurred in w 1, latch 1 at this time
The output of 1 is written to the memory 17. When this operation is completed, the memory read operation is performed again from time t3 when the read request signal 22 is generated. At time t4 when this ends, the state of the write request signal 13 is checked in the same way as last time.

, but here there is no requirement. This means that the frequency of dot clock 6 on the write side is the same as that of dot clock 2 on the read side.
This is because the serial-to-parallel conversion for 8 dots has not yet been completed by the SP converter 10. At this time, there is a write period as a memory operation, but nothing is written to the memory 17. This period is hereinafter referred to as the invalid period. Immediately after this, at time t w 2, the serial-to-parallel conversion is completed and the latch 11 is updated, but this data is written to the memory ]7 at the next time t6. However, at this point, the next data is latch 11.
Since it is never set to , no data is written down.

On the other hand, when the frequency of the dot clock 6 is higher, memory operation is performed in synchronization with this, thereby making it possible to control the CR7 display without omitting data readout.

[Problems to be Solved by the Invention] In the above-mentioned conventional technology, the second display H position only has the function of displaying the same display as the original display device, and the original display screen is left as it is and another display is displayed. No consideration is given to adding other display content only to the device. For example, if the original display device displays at a resolution of 640X400F, another display device will display at the same resolution.
400 dots cannot be displayed or displayed. However, in the case of the above number of dots, the memory capacity of the display signal converter is 32,000 bytes, where 1 dot Y=1 bit (2-level screen). However, for boat fishing, a memory element has a capacity of 20 bytes, and if a memory element with a capacity of 2+5=32768 bytes is used, 768 hides will be unused. This is 64
It has a capacity that can display 9.6 lines of 0 dots. When you want to actively use the remaining memory in this way, or when you want to add additional memory and display additional information, you can change the value of the read counter 23 in Figure 2 to display, for example, 640x409). Although it is possible to do so, the display data for the added 9 dots is not written, and there is no consideration given to rewriting the memory contents to arbitrary values, so there is no way to do so, and the display becomes completely meaningless. I end up.

An object of the present invention is to provide a display signal conversion device that can add new display content to the original display content of a display device and display it on a second display device.

[Means for Solving the Problems] The above object is to provide a first means for writing display information for a first display device into a memory, and a second display device for reading out the display information written to the memory. a third means for controlling the display information to be displayed on the second display device by alternately assigning operation periods to the first and second means; In the display signal conversion device, the third means has a function of detecting a boiling period during which the operation of the first or second means is unnecessary, and the third means detects the invalidation period. This is achieved by providing a fourth means for writing or reading data from the outside into or from the memory when detected.

[Operation] The CPU uses the blanking period of the display device or the invalid period of writing or reading provided to balance writing and reading of the memory when the dot clock speeds of the two display devices are different. By writing to CP [1], it is possible to write from CP [1 and display it on the second display device without disturbing the display on the display device and by effectively utilizing free time.

[Example code] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a first embodiment of the apparatus of the present invention, and the same parts as in FIG. 5 are given the same numbers. The differences between this display signal converter 30A and FIG. 5 are as follows.
The synchronization signal 27 for the CRT (retrace period when the bell goes high) is manually input to the memory control circuit 4A, and the decoder 3
1 is provided to input a request signal 32 for write access to the memory of the CPU 1 to the memory control circuit 14A, and a contact is provided to the switch 16A, and a switch 34 is provided to input the write address and data from the CPU 1 to the memory control circuit 14A. 17 and the memory control circuit 16
The point is that the wait signal 33 is output from A to the CPU 1.

FIG. 2 is a time chart showing the write operation from the CPU 1 to the memory 17 in this embodiment. CPU 1
outputs a write address to write to the memory, the decoder 31 detects the write address and sends a CPU write request signal 3 to the memory control circuit 14.
Generates 2.

Assuming that time is tel in FIG. 2, the memory control circuit 14
A receives this and sends a wait signal 33 to CPU 1.
is set to low level. During this period, writing and reading of display data is performed at the same timing as in FIG. At time tc2, when the CRT synchronization signal 27 becomes high level indicating the retrace period, the CRT 25 enters the non-display period, so reading from the memory 17 becomes unnecessary. Therefore, if writing is performed from the CPUI using this period, the display on the CRT 25 will not be disturbed in any way and only writing will be possible. That is, writing from the CPU may be performed during the reading period from the first reading time t5 after time tc2. Therefore, when the address switch 16A and the synchronization signal 27 are at a high level and the write request signal 32 is at a high level, the memory control circuit 14A switches the switches 16A and 34 to CPt, respectively, during a period corresponding to reading.
The CPU 1 switches to the J side and causes the CPU 1 to perform a write operation to the memory 17. Finally, writing is done at time tc3
When the process is completed, the wait signal 33 is released.

As described above, in this embodiment, data can be written from the CPU 1 to any address in the memory 17 using the retrace period from the CRT 25, and any data can be added to the CRT, which is the second display device. can be displayed.

3 and 4 are block diagrams showing a second embodiment of the present invention and time charts showing its operation. In this embodiment, the CPU uses an invalid period for writing (or reading) display data into the memory, not the retrace period of the CRT.
The display signal converter 30B of this embodiment eliminates the input of the synchronization signal 27 shown in FIG.
The function of the 14A is different from that of the 14A. This operation will be explained below.

As in the first embodiment, the CPU write request signal 32 is generated at time t e l, and after the wait signal 33 becomes low level, the memory control time i? l! 14B detects a write (or read) invalid period. That is, as in the conventional example, the read dot clock is faster and the 6th dot clock is faster.
As shown in the figure, if there is no write request signal 13 at the end time t4 of the read period in FIG. The switching is made to write to the memory 17. The time t when this ended
, c2, the wait signal 33 is canceled and normal operation is resumed. Similarly, if the dot clock 6 for writing is faster than for reading, an invalid period for reading occurs, and this can be used.

In this embodiment, the invalid period explained in FIG. 6 is required.

This invalid period is the dot clock 6 output from the display circuit 4.
The frequency of occurrence is determined by the ratio of the frequency of the dot clock 26 output from the oscillator 20, but if the generation period of the invalid period is shorter than 270 cycles of the synchronization signal in the embodiment of FIG.
The method using the invalid period shown in this embodiment has a shorter average waiting time for CPU writing than the method using the retrace period shown in the first embodiment.

In the above embodiment, it is assumed that the dot clock of the original display device and the dot clock of the second display device are different, but if they are the same, no invalid period occurs, so the second embodiment is not applicable. Further, in the first embodiment, memory writing was performed using the retrace line U lock of the second display device, but the retrace period of the original display device can also be used. In this case, the memory writing from the CPU can be performed using the display data writing period during the retrace period of the original display device and the display data read period during the retrace period of the second display device. can. In addition, in the above embodiment, the case where writing is performed to the CPU or memory is explained, but the CPU
It goes without saying that the present invention can also be applied to the case where the data is read from the memory. Furthermore, it goes without saying that both the original display device and the second display device are not limited to a liquid crystal panel or a CRT, respectively, but can be any display device.

[Effects of the Invention] According to the present invention, additional data can be written directly from the CPU to the memory, so the original display! ! Any display content can be added to the content displayed on the second display device and displayed on the second display device. In addition, the writing may be performed during a period in which writing or reading of display data is unnecessary, or during a period in which writing or reading of display data is unnecessary.
Since the writing or reading invalid period that occurs when the two display devices have different clocks can be used for writing or reading, there is an effect that writing can be performed at high speed without disturbing the display screen.

[Brief explanation of drawings]

1 and 2 are block diagrams and operation time charts showing a first embodiment of the present invention, and FIGS. 3 and 4 are block diagrams and operation time charts showing a second embodiment of the present invention. 5 and 6 are a block diagram and an operation time chart showing a conventional display signal conversion device. 1...cpu, s...original display device, 14A, 1
4B...Memory control circuit, 16A, 34...Switch, 17...Memory, 25...CRT, 30A, 3
0B...Display signal conversion device, 31...Decoder.

Claims (1)

[Claims] 1. A first means for writing display information on a first display device into a memory, and reading out the display information written in the memory to create display information on a second display device. and third means for controlling the display information to be displayed on the second display device by alternately assigning operation periods to the first and second means. In the signal conversion device, the third means has a function of detecting an invalid period in which the operation of the first or second means is unnecessary, and when the invalid period is detected by the third means, the external A display signal conversion device characterized in that a fourth means for writing or reading data into or from the memory is provided. 2. The invalid period is a period during which the operation of the first display device is in a retrace period and the first means is in an operation period;
Alternatively, the second display device is operating during a retrace period and the second means is operating during a period, or the dot display speed of the first display device is slower than that of the second display device. during a period when the operation of the first means is off, or when the first display device has a faster dot display speed than the second display device. 2. The display signal converting device according to claim 1, wherein the display signal converting device is set during one of the periods in which the period is a holiday.