JPH041437B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a nonvolatile semiconductor memory device, and relates to a field effect transistor, particularly a field effect transistor that can change a threshold voltage depending on information and retain information for a long time. The present invention relates to a memory device using a so-called nonvolatile memory transistor.

[Prior art]

Non-volatile memory using field-effect transistors generates an avalanche phenomenon near the drain and injects the generated hot electrons into a control gate and a floating gate formed in an insulating film between substrates to change the threshold voltage. FAMOS writes information by pressing
(Floating gate Avalanche injection MOS)
MNOS uses a tunneling phenomenon to inject charge into the trap between the gate oxide film and the silicon nitride film formed on top of it by making the gate oxide film extremely thin.
(Metal Nitride Oxide Semiconductor) structure. In either case, it takes time on the order of milliseconds to write information into one transistor, that is, to change the threshold voltage of the memory into which charge is injected.

Figure 1 is a cross-sectional view showing the schematic structure of FAMOS.
In the figure, 1 is a p-type substrate, 2 and 3 are respectively
An n ⁺ type source and drain, 4 an insulating layer, 5 a floating gate embedded in the insulating layer 4, and 6 a control gate insulated above.

FIG. 2 is a diagram showing an example of the write characteristics of a FAMOS transistor. In FIG. 2, the vertical axis represents the threshold value of the memory transistor, and the horizontal axis represents the cumulative width of applied pulses for writing. In this example, the memory threshold before writing is 1.5V, but for example,
Ground the source 2 in Figure 1 and apply 15V to the drain 3.
When 25V is applied to the control gate 6, the threshold voltage increases as write pulses accumulate. The degree of increase is large at the beginning and tends to saturate over time. This increase in the threshold value corresponds to the amount of charge accumulated in the floating gate 5 in FIG.

Memory retention in FAMOS type memory is achieved by keeping electrons injected into the floating gate 5 there, so in order to obtain a sufficient memory retention time, a sufficient amount of charge is injected into the floating gate 5. It is necessary to raise the threshold sufficiently.
FIG. 3 shows an example of memory retention characteristics. In general, temperature can accelerate the decay of memory retention;
The higher the temperature, the faster electrons are emitted, which means the threshold value decreases faster.

In the case of Figure 2, if the voltage applied to the control gate 6 during readout is set to 5V, the 8m
Although the threshold value gradually increases as the write pulse is applied, the memory transistor remains in the ON state until after the write pulse is applied for 8ms.
The memory transistor to which the above write pulses have been applied is in an OFF state. Therefore, in the past, in order to maintain the temperature for more than 10 years at a temperature of 70°C, which is close to the worst practical condition, 80°C was used to ensure safety.
The write pulse was applied for a longer time than necessary, well over ms.

On the other hand, the threshold value of the memory transistor written by the write pulse decreases with time, and the voltage (output signal) read from the memory transistor also decreases with time, so that the information stored in the memory transistor In order to determine whether the information is binary information, the voltage read from the memory transistor is compared with a reference voltage signal. When the voltage read from the memory transistor is equal to or higher than the reference voltage signal, that is, when the threshold value of the memory transistor is equal to or higher than a predetermined value, the information stored in the memory transistor is determined to be binary information "0", and the memory transistor When the voltage read from the memory transistor is less than or equal to the reference voltage signal, that is, the threshold value of the memory transistor is less than or equal to a predetermined value, the information stored in the memory transistor is determined to be binary information "1".

When a power supply voltage of 5V is used, the median value of 5V, 2.5V, is used as the reference voltage signal.

Therefore, the threshold of the memory transistor is when the output voltage read from the memory transistor is 2.5V.
If the above settings are made, the "0" information stored in the memory transistor will be read out without fail.

Then, when the output voltage read from the memory transistor is 2.5V, the threshold of the memory transistor is 3.5V. Therefore, as shown in Figure 2, if a 5ms write pulse is applied for the time when the threshold of the memory transistor becomes 3.5V, This is fine, but with a 5ms applied pulse, there is no margin, so if the threshold value drops even a little, the read voltage from the memory transistor will drop below 2.5V, causing the information written to the memory transistor to be erroneous. .

By the way, the inventors investigated the relationship between the retention time of information in the case of writing in a memory transistor and the threshold voltage of the memory transistor, and obtained the results shown in FIG. 3.

As is clear from Figure 3, in order to be able to maintain the memory transistor for more than 10 years at a temperature of 70°C, which is close to the worst practical condition, the threshold value of the memory transistor must be set at 3.5V with a margin of 1V. Just set it to 4.5V.

However, when the reference voltage signal is set to 2.5V,
If the threshold of the memory transistor is 3.5V or higher,
Since it is always judged as "0" information, it is unclear whether the threshold value of the memory transistor is 3.5V or has risen to 4.5V, and the anxiety remains unresolved.

Next, a conventional nonvolatile semiconductor memory device will be explained using the drawings.

FIG. 4 is a block diagram showing a configuration example of a conventional memory device, in which 7 is a row address signal input terminal, 8 is a column address signal input terminal, 9 is a row address input buffer, 10 is a row address decoder, and 11 is a memory array. , 12 is a column address input buffer, 13 is a column address decoder, 14 is a group of column output selection transistors, 15 is a writing/reading switching transistor, 16 is a readout amplifier circuit (sense amplifier), 17 is a reference signal generation circuit, 18 is an output buffer, 19 is an input/output terminal, and 20 is a data input buffer during writing.

Since this conventional device is well known, the read operation will be briefly explained. The storage information of the memory transistor in the memory array 11 specified by the address input is applied to the gate of the selected memory transistor via the row address decoder 10, and a voltage is applied to the gate of the selected memory transistor.
As a result, the drain voltage of the selected memory transistor is input to the sense amplifier 16 via the column output selection transistor 14 selected by the column address decoder 13 and the write/read switching transistor 15, and is supplied from the reference signal generation circuit 17. compared to the standard level. The output of the sense amplifier 16 is amplified by an output buffer 18 and output to an input/output terminal 19 as a data output.

FIG. 5 is a circuit diagram showing the circuit configuration of a memory array, a group of column output selection transistors, and a reference signal generation circuit in relation to a sense amplifier, and portions equivalent to those in FIG. 4 are designated by the same reference numerals. 21 is a row address decoder output, 22 is a column address decoder output, 23 is an output terminal from the sense amplifier 16 to the output buffer, 2
4 is a load resistance of the write/read switching transistor 15.

Row address decoder output 21 is input to the gate of a memory transistor (eg 111), and column address decoder output 22 is input to the gate of a column output selection transistor (eg 141). The drain voltage of the selected memory transistor 111 is applied to the column output selection transistor 141 and the write/
The signal is inputted to one input of the differential amplification type sense amplifier 16 through the readout switching transistor 15. The drain voltage of a dummy memory transistor 171 in the reference signal generation circuit 17 is supplied to the other input ○ and B of the differential amplification type sense amplifier 16 via a transistor 172 corresponding to the transistor 141 and a transistor 173 corresponding to the transistor 15. be done. 174 is a load resistor corresponding to the load resistor 24. Memory transistor 111
and 171, transistors 141 and 172, transistors 15 and 173, and resistors 24 and 174 are designed to have the same characteristics in order to improve the balance of the sense amplifier 16.
The gate signal values of transistors 1 and 172 and transistors 15 and 173 are also set equal.

Now, when the memory transistor 111 is written (that is, its threshold value is 3.5V or higher), the potential at point ○A is approximately 2.5V, and the memory transistor 111 is not written (that is, its threshold is 3.5V or higher).
When the threshold is around 1.5V), the potential at point A is approximately
It is set to 1.5V. Then, the dummy memory transistor is set so that the reference potential to point ○ is a value (for example, 2.5V) close to the intermediate value between 1.5V, which is the output voltage read from the memory transistor 111, and a value exceeding 2.5V. 171, finely adjust the characteristics of transistors 172 and 173; The read voltage to point A changes as shown in FIG. 6 along with the threshold value of the memory transistor according to the write pulse width. In this example, since the reference input voltage at the point ○ is 2.5V, the output of the sense amplifier 16 is inverted by applying a write pulse for 5 ms or more. The output of the sense amplifier 16 does not change when more pulses are applied. Therefore, it is impossible to tell from the outside how much margin was written into the memory transistor, and in the end,
In the past, it was necessary to set standards to apply a pulse width with a sufficient margin of 50 ms, assuming all the worst conditions, and the time required for writing became extremely long.

[Summary of the invention]

The present invention has been made in view of the above points, and the reference input potential of the differential sense amplifier during read in write verification mode during write is set by a predetermined value from the reference input potential during normal read. By increasing the value, it can be assumed that sufficient writing has been completed when the output is inverted during reading in the write verify mode, thereby providing a nonvolatile semiconductor memory device that can perform reliable writing in a short time. be.

[Embodiments of the invention]

As explained in Figure 3, in order to have a memory retention characteristic of 10 years, the threshold voltage of the memory transistor must be the lowest threshold that can determine whether it is "0" information or "1" information at the time of reading (in this explanation 3.5V), it is sufficient to have a margin of 1V. That is, in a memory transistor having characteristics as shown in FIG. 2, if a pulse with a width of 7 ms is applied, the threshold value of the memory transistor becomes 4.5 V, which is sufficient. For the application of pulses with a width of 7 ms, the fifth
The signal potential at point ○ in the figure is 3.8V when viewed from Figure 6. Therefore, if the reference signal potential at point ○ in Figure 5 is set to 3.8V when reading in the write verify mode during writing, the output of this sense amplifier will not be inverted until the writing pulse width becomes 7ms. , at the time of inversion, even if writing is stopped, the threshold value of the memory transistor is a value slightly exceeding 4.5V. If the reference signal potential during reading during writing, that is, during normal reading other than during write verification, is set to the original 2.5V, this difference, that is, the difference in the threshold voltage of the memory transistor, will be 1V, and the temperature will rise to 70°C. at a temperature of
This means that it is possible to retain memory for 10 years.

FIG. 7 is a circuit diagram of a reference signal generation circuit used in an embodiment of the present invention, and parts equivalent to those in the conventional example are designated by the same reference numerals. 25 is a program power supply terminal, 26 is a program voltage detection circuit, and 27 is a transistor connected between the gate of the dummy memory transistor 171 and the ground point. In the program voltage detection circuit 26, each constituent transistor is selected so that the overall threshold value is around 10V. That is, if a voltage of 10V or more is applied to the program power supply terminal 25, a voltage of about 2V is generated at the output point ○C, and the transistor 27 is slightly turned on.If the input voltage is 10V or less, the potential of the output point ○C is becomes 0V and the transistor 27 is turned off. The transistor 27
When it is OFF, it becomes the same as the conventional circuit shown in FIG.

Normally, in the write verify mode, a high voltage is applied to the program power supply terminal 25, and during normal reading, the voltage of the program power supply terminal 25 is about 5V, so this changes the conduction state of the transistor 27. do. In other words, the transistor 27 is OFF during normal read operation.
Therefore, as explained in the conventional example of FIG. 5, this reference signal generating circuit obtains a voltage of 2.5V at the output point ○○, and in the case of reading in the write verify mode during writing, the voltage of 2.5V is obtained from the transistor 27. is slightly
It becomes ON, and a voltage of 3.8V can be obtained at output point ○○. In this way, by detecting the program voltage, the reference signal potential of the sense amplifier is changed between the write verify mode read during write and the normal read. Writing that can guarantee memory retention can be performed efficiently.

〔Effect of the invention〕

By utilizing the configuration of the present invention described above, the write pulse width is set to a small value of about 1 ms, and each time the pulse is applied, the write verification mode is used to check for output reversal.
By repeating writing to the same address until the output is reversed, and proceeding to the next address when the output is reversed, there is no wasted time at all, and reliable writing is possible, eliminating the problem of write time. This is particularly effective for large-capacity memory devices.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view showing the schematic structure of a FAMOS transistor, Figure 2 is a diagram showing an example of the write characteristics of the FAMOS transistor, Figure 3 is a diagram showing an example of its memory retention characteristics, and Figure 4 is a diagram of a conventional memory. FIG. 5 is a block diagram showing an example of the configuration of the device. FIG. 5 is a circuit diagram showing the circuit configuration of the memory array, column output selection transistor group, and reference signal generation circuit of a conventional memory device in relation to a sense amplifier. FIG. 7 is a characteristic diagram showing the relationship between write pulse width and read voltage of a FAMOS transistor, and is a circuit diagram of a reference signal generation circuit used in an embodiment of the present invention. In the figure, 11 is a memory array, 111 is a memory transistor (memory element), 16 is a sense amplifier (reading amplifier), 17 is a reference signal generation circuit, 25 is a program power supply terminal, and 26 is a program voltage detection circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1 A plurality of non-volatile semiconductor memory devices each storing one of binary information, and a high voltage output read out when sufficient data has been written corresponding to one of the binary information stored in the semiconductor memory device. intermediate voltage signal generating means for generating an intermediate reference voltage signal between the signal and a low voltage output signal read when not being written, corresponding to the other binary information stored in the semiconductor memory element;
a comparison reading means for comparing an output signal read from the semiconductor memory element with a reference voltage signal and identifying whether the information read from the semiconductor memory element is one of the binary information; means for writing either one of the value information; and boosting means for further increasing the intermediate reference voltage signal generated by the intermediate voltage signal generating means to a write confirmation voltage between this and the high voltage output signal; When reading information from the semiconductor memory element by the normal comparison readout means, the reference voltage signal to be compared with the output signal read from the semiconductor memory element is the intermediate reference voltage signal, and the semiconductor memory In a write verify mode for confirming completion of writing information to the element, the intermediate voltage signal generating means and the boosting means are configured to raise the intermediate reference voltage signal, which becomes the reference voltage signal, to the write confirmation voltage. 1. A nonvolatile semiconductor memory device comprising: means for controlling.