JPH0414860A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0414860A
JPH0414860A JP2118421A JP11842190A JPH0414860A JP H0414860 A JPH0414860 A JP H0414860A JP 2118421 A JP2118421 A JP 2118421A JP 11842190 A JP11842190 A JP 11842190A JP H0414860 A JPH0414860 A JP H0414860A
Authority
JP
Japan
Prior art keywords
lead
semiconductor device
leads
main body
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2118421A
Other languages
Japanese (ja)
Inventor
Yoshihiko Gomi
五味 良彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2118421A priority Critical patent/JPH0414860A/en
Publication of JPH0414860A publication Critical patent/JPH0414860A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce protrusion of a lead toward a main surface of a body as compared with a protruding lead from the side of the body and to decrease its mounting area by leading leads from the lower surface of the body, forming the led end in an L shape. CONSTITUTION:A semiconductor chip 12 is placed on a base 10 by a die bonder by using a lower die 9 formed of glass epoxy material and formed integrally with a lead 11. In this case, the chip 12 is secured with adhesive. Then, the electrode 13 of the chip 12 is bonded via a wire 14 at the L-shaped part toward the center of the lower mold 9 of the lead 11. Thereafter, an upper mold 15 is formed by a molding machine to provide a completely assembled product. In a semiconductor device 8 obtained in this manner, since the leads 11 protrude from the lower surface of a body 16, the protruding area of the lead toward the main surface of the body can be reduced to decrease its mounting area.

Description

【発明の詳細な説明】 [産業上の利用分野コ 本発明は、半導体装置の製造技術に関し、特に大きいサ
イズの半導体装置の製造に利用して有効な技術に関する
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technology for manufacturing semiconductor devices, and particularly to a technology that is effective when used in manufacturing large-sized semiconductor devices.

[従来の技術] 従来の技術としては、第2図に示すようなものがある。[Conventional technology] As a conventional technique, there is a technique as shown in FIG.

図において1は半導体装置を示す。2は半導体チップで
あり、半導体装置の心臓部となるものである。5はワイ
ヤであり、金属細線からなっており、前記半導体チップ
の電極4と後述するリードとの導通をとる為のものであ
る0 5はリードであり、前記ワイヤ3の一端がボンデ
ィングされている。このリード5は、前記ワイヤ6がボ
ンディングされている一端とは異なる他端が、後述する
本体の側面から、本体主表面に平行して導出した後、L
字状に曲げられている。6はダイパッドであり、四方形
状の板状物で、前記半導体チップが、図示しない接着剤
によってボンディングされている。7は本体であり、前
記半導体チップ2、ワイヤ5等、半導体装置の主要部を
覆う四方形状物である。
In the figure, 1 indicates a semiconductor device. 2 is a semiconductor chip, which is the heart of the semiconductor device. Reference numeral 5 represents a wire, which is made of a thin metal wire, and is used to establish electrical conduction between the electrode 4 of the semiconductor chip and a lead to be described later.0 5 represents a lead, to which one end of the wire 3 is bonded. . The other end of the lead 5, which is different from the one end to which the wire 6 is bonded, is led out from the side surface of the main body, which will be described later, parallel to the main surface of the main body, and then
It is bent into a letter shape. Reference numeral 6 denotes a die pad, which is a rectangular plate-like object to which the semiconductor chip is bonded with an adhesive (not shown). Reference numeral 7 denotes a main body, which is a rectangular object that covers the semiconductor chip 2, wires 5, and other main parts of the semiconductor device.

[発明が解決しようとする課題] 本発明者は、上述した従来技術を用い、多ピン(例えば
、100P工N以上のリードのもの)の半導体装置を製
造したところ、以下に示すような問題があることを見い
出した。
[Problems to be Solved by the Invention] When the present inventor manufactured a semiconductor device with a large number of pins (for example, one with leads of 100P or more) using the above-mentioned conventional technology, the following problems were found. I discovered something.

すなわち、多ビンになるに従い、リードを多数配置する
必要がある為、本体の主表面のサイズが大きくなるとい
う問題である。この事により、本体の側面からリードが
導出する従来の半導体装置では、本体のさらに外側にリ
ードがある為、実装(プリント基板等への実装)面積が
大きくなってしまうという問題があることを、本発明者
は見(・出した。
That is, as the number of bins increases, it is necessary to arrange a large number of leads, which causes the problem that the size of the main surface of the main body increases. As a result, in conventional semiconductor devices in which the leads are led out from the side of the main body, there is a problem in that the mounting area (mounting on a printed circuit board, etc.) becomes large because the leads are located further outside the main body. The inventor found out.

本発明の目的は、多ビンの半導体装置であっても、実装
面積を小さくできる半導体装置の製造技術を提供する事
にある。
An object of the present invention is to provide a semiconductor device manufacturing technique that can reduce the mounting area even for a multi-bin semiconductor device.

cm題を解決するための手段] 本発明の半導体装置は、半導体チップと半導体チップの
周囲に配されたリードとそれらのうち少なくとも一部を
封止した本体からなる半導体装置において、リードが本
体の下面から突出し、その先端がL字状になっているこ
とを特徴とする。
Means for Solving the CM Problem] The semiconductor device of the present invention comprises a semiconductor chip, leads arranged around the semiconductor chip, and a main body in which at least a part of them is sealed. It is characterized by protruding from the lower surface and having an L-shaped tip.

[実施例コ 第1図は、本発明の一実施例である半導体装置を示す概
略側面図である。
Embodiment FIG. 1 is a schematic side view showing a semiconductor device which is an embodiment of the present invention.

図において、8は半導体装置を示す。9は下型であり、
後述する上型とで本体を形成する。1Dは載置部であり
、前記下型の中央部分に設けられ、後述する半導体チッ
プを載置する凹部が形成されている。11はリードであ
り、前記下型9の上面から下面にかけて貫通し、下型9
と一体的に形成されていて、その両端はL字状に曲げら
れている。前記下型9は、例えば、ガラエボ材料からな
っており、その中にリード11を埋め込んだかたちにな
っている。12は半導体チップであり、前記載置部10
に、図示しない接着剤を介して載置されている。15は
電極であり、前記半導体チップ12の上面に設けられて
いる。14はワイヤであり、金属細線からなり、前記半
導体チップ12の電極13と、前記リードとの導通をと
る為に、ボンディングされている。15は上型であり、
樹脂によって成形され、前記半導体チップ等、半導体装
置8の主要部を覆い、前記下型9とで、本体16を形成
する。
In the figure, 8 indicates a semiconductor device. 9 is the lower mold;
A main body is formed with an upper mold described later. Reference numeral 1D denotes a mounting portion, which is provided at the center of the lower mold, and has a recessed portion on which a semiconductor chip, which will be described later, is placed. Reference numeral 11 denotes a lead, which penetrates from the upper surface to the lower surface of the lower mold 9.
Both ends are bent into an L-shape. The lower mold 9 is made of, for example, Gala Evo material, and has a lead 11 embedded therein. 12 is a semiconductor chip, and the above-mentioned mounting section 10
It is placed on the board with an adhesive (not shown) in between. Reference numeral 15 denotes an electrode, which is provided on the upper surface of the semiconductor chip 12. A wire 14 is made of a thin metal wire and is bonded to establish electrical conduction between the electrode 13 of the semiconductor chip 12 and the lead. 15 is the upper mold;
It is molded from resin, covers the main parts of the semiconductor device 8 such as the semiconductor chip, and forms a main body 16 together with the lower mold 9 .

以下、上述した構成の本発明の一実施例について、その
作用を説明する。
Hereinafter, the operation of an embodiment of the present invention having the above-described structure will be explained.

ガラエボ材料からなり、リード11と一体化して成形さ
れた下型9を用い、先ず図示しないダイボンダーにより
、半導体チップ12を、その載置10に載置する。この
際、半導体チップ12は、図示しない接着剤により固定
される。次いで、図示しないワイヤボンダーにより、半
導体チップ12の電極13と、リード11の下型9中心
に向ったL字状部分が、ワイヤ14でボンディングされ
る。その後、モールド装置(図示せず)により上型15
が形成され、組立完成品となる。
First, a semiconductor chip 12 is placed on a holder 10 using a die bonder (not shown) using a lower mold 9 made of Gala Evo material and molded integrally with the leads 11 . At this time, the semiconductor chip 12 is fixed with an adhesive (not shown). Next, using a wire bonder (not shown), the electrodes 13 of the semiconductor chip 12 and the L-shaped portions of the leads 11 facing the center of the lower mold 9 are bonded with wires 14. After that, the upper mold 15 is molded using a molding device (not shown).
is formed, resulting in a finished assembled product.

このようにして得られた半導体装置8は、リード11が
本体16の下面から突出している^、本体の側面から突
出するものに比べ、リードの本体主表面方向への突出面
積を小さくでき、実装面積を少なくできる。
In the semiconductor device 8 obtained in this manner, the leads 11 protrude from the lower surface of the main body 16, and the protruding area of the leads toward the main surface of the main body can be made smaller than when the leads 11 protrude from the side surfaces of the main body. The area can be reduced.

[発明の効果] (1) 半導体装置の、本体下面からリードを導出し、
導出した先端をL字状に成形することにより、本体の側
面からリードが突出するものに比べ、本体の主表面方向
へのリードの突出を低減できる為、多ピンの半導体装置
においても、その実装面積を小さくできるという効果が
得られる。
[Effects of the invention] (1) Leads are led out from the bottom surface of the main body of the semiconductor device,
By forming the led-out tip into an L-shape, the protrusion of the lead toward the main surface of the main body can be reduced compared to the case where the lead protrudes from the side of the main body, making it easy to mount even in multi-pin semiconductor devices. This has the effect of reducing the area.

(2) 半導体装置の本体下面からリードを導出し、導
出した先端をL字状に成形することにより、−に本体下
面から、直線的に伸ばしたものに比べ、実装時に安定す
るという効果が得られる。
(2) By leading out the leads from the bottom surface of the semiconductor device body and forming the leading ends into an L-shape, the lead is more stable during mounting compared to the case where the leads are extended linearly from the bottom surface of the body. It will be done.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の一実施例である半導体装置を示す概
略側面図。 第2図は、従来技術を説明する為の、半導体装置を示す
概略側面図。 1.8−−−−・・・・半導体装置 2 、12 ・・・−・半導体チップ 3.14−・−ワイヤ 4.13−・−・電 極 5,11・・・・・・−リード 6・・・・−・−・−・−・・・・ダイパッド7.16
−・−・−・本 体 9・・・・・・・・・−・・・・・−下 型10・−一
・−・−・−・載置部 15−・・・−・・・・−・上 型 出願人 セイコーエプソン株式会社 代理人 弁理士 鈴木喜三部(他1名)下型 リード ワイヤ 本体 第1図
FIG. 1 is a schematic side view showing a semiconductor device that is an embodiment of the present invention. FIG. 2 is a schematic side view showing a semiconductor device for explaining the prior art. 1.8------Semiconductor device 2, 12---Semiconductor chip 3.14---Wire 4.13---Electrode 5, 11---Lead 6・・・・−・−・−・−・・Die pad 7.16
−・−・−・Main body 9・・・・・・・・・−・・・Lower mold 10・−1・−・−・−・Placement part 15−・・・・・・・--Top mold applicant Seiko Epson Co., Ltd. agent Patent attorney Kizobe Suzuki (and one other person) Bottom mold lead wire main body Figure 1

Claims (1)

【特許請求の範囲】[Claims] (1)半導体チップと半導体チップの周囲に配されたリ
ードと、それらのうち少なくとも一部を封止した本体と
からなる半導体装置において、リードが本体の下面から
突出し、その先端がL字状になっていることを特徴とす
る半導体装置。
(1) In a semiconductor device consisting of a semiconductor chip, leads arranged around the semiconductor chip, and a main body in which at least a portion of these leads are sealed, the leads protrude from the bottom surface of the main body, and the tips thereof are L-shaped. A semiconductor device characterized by:
JP2118421A 1990-05-08 1990-05-08 Semiconductor device Pending JPH0414860A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2118421A JPH0414860A (en) 1990-05-08 1990-05-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2118421A JPH0414860A (en) 1990-05-08 1990-05-08 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0414860A true JPH0414860A (en) 1992-01-20

Family

ID=14736225

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2118421A Pending JPH0414860A (en) 1990-05-08 1990-05-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0414860A (en)

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