JPH04150255A - Image sensor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] With the advancement of information processing equipment in the field of industrial application, the need for image sensors as input devices has increased.The present invention provides an image sensor that makes it possible to read document information at high speed and with high sensitivity. This is related to a sensor.A Conventional technology Photodiodes receive force between electrons and holes generated by light irradiation on a semiconductor p-n junction.Electrons move to the n-type layer due to the internal electric field existing at the junction. Holes move to the p-type layer. It is also possible to accumulate the signal charge generated by moving to
As an image sensor that uses an array of photodiodes to read out signal charges in charge accumulation mode? ! M.O.S.
Although MOS, amplified MOS, and CCD image sensors have been developed and put into practical use, MOS image sensor ζ has a simple configuration and is a method in which the signal charge of the photodiode is sequentially taken out as an image signal through an access MOSFET. In contrast, amplified MOS image sensors have an amplification function for each pixel in order to obtain high sensitivity.
As shown in FIG. 5, the anode voltage which is the residual voltage after discharge due to the photocurrent of the photodiode 7 is transferred to
To the gate of ET8 Amplification MO according to the gate voltage
This method extracts the output current flowing through SFET8 and access MOSFET9 as an image signal.This method has higher sensitivity than a MOS image sensor.
Although the sensitivity is still lower than that of a CCD image sensor, both LMOS and amplified MOS image sensors have a small drive capacity and are easy to scan at high speed. Although it consists of an output amplifier, etc., the signal charge G&
The transfer gate transfers the signal charge to the potential well of the transfer COD shift register, and the clock pulse moves this potential well and transfers it to the output amplifier.The output amplifier converts the signal charge into voltage, amplifies it, and converts it into an image signal. As can be inferred from the size of the gate capacitance and line capacitance of the transfer CCD shift register, high-speed scanning is difficult because the driving capacitance is considerably large.The invention will solve this problem. As mentioned above, among the conventional image sensors, MOS
High-speed scanning is easy for amplified MOS image sensors, but the problem still remains that it is difficult to increase sensitivity due to physical limitations. Although high sensitivity has been achieved in CCD image sensors (there is also the problem that high-speed scanning is difficult due to the large drive capacity), the present invention takes into consideration the above-mentioned problems and provides an image sensor that is highly sensitive and capable of high-speed scanning. Means for Solving the Problems In order to solve the above problems! ζ Image sensor C of the present invention Photodiode At least two stages of MOS type gates adjacent to the photodiode, and at least two stages of MOS type gates adjacent to the rear stage of the MOS type gate. A pixel consisting of a FET for receiving and amplifying the voltage generated at the pn junction, an access FET, and a reset FET for receiving and amplifying the voltage generated at the pn junction, which has a junction capacitance smaller than that of a photodiode, and the access FET. FET, and a scanning shift register for sequentially driving the reset FET.These elements can be formed on the same semiconductor substrate using integrated circuit technology, but the above-described structure of the present invention has a photo-optical function. Transfer pulses are sequentially applied to the signal charge accumulated in the diode for a certain period of time to two adjacent MOS gates, and the potential well generated in the semiconductor substrate layer under the gate electrode is moved from the photodiode side to the small junction capacitance side. As expected from the relational expression &V=Q/C, the transferred charge can transfer the photo to the small junction capacitance, which has a smaller junction capacitance than the photodiode. A voltage higher than that obtained by directly detecting the terminal voltage of the diode will be generated.
By receiving this voltage at the gate of the amplification MOSFET and amplifying it, high output can be obtained and sensitivity can be increased.
In addition, since the driving capacity is mainly the gate capacitance of the two-stage MOS gate, the capacity is small, and at the same time, the transfer time can be longer than the scanning clock time. Embodiment Hereinafter, an embodiment of the image sensor according to the present invention will be described with reference to the drawings. The photodiode I
a-1d, two-stage MOS gates 2a to 2d, small junction capacitances 3a to 3d, amplification n-channel MOS FET 4
a to 4 d, n-channel MOSFE for access
T5a to 5d, n-channel MOSFE for reset
It consists of pixels consisting of T6a to 6d and a scanning shift register 4 Here F and VDD are power supply voltages (5V to 6V)
terminal, VBB is the reset voltage (2,5V to 3V) terminal,
IS is an image signal output terminal, Φf and Φ2 are charge transfer pulse input terminals, and A1 to A6 are scanning pulse output terminals of a scanning shift register.The scanning pulse output terminal is the gate of an n-channel MOSFET for accessing each pixel. They are commonly connected to the gates of the reset n-channel MOSFETs of the pixels in the previous stage, and the scan pulse simultaneously accesses the pixel and resets the pixels in the previous stage. Figure 2 is a cross-sectional view of the device structure of the light receiving/transfer section in the pixel of the image sensor of the present invention when an n-type semiconductor substrate is used. Even if the structure is such that a full p-diffusion layer is created for each pn junction and a two-stage MOS gate is placed between them, the junction capacitance of the pn junction has a small junction capacitance equal to that of a photodiode in order to obtain high sensitivity. The n-type substrate is connected to the power supply voltage, and even if a reverse bias is applied to the two pn junctions, it will be as small as possible compared to Fig. 3 1, Φ1 and Φ2.
Charging transfer pulses applied to the terminals A1 to As are scan pulses that are output to the terminals. A timing diagram of the image signal output waveform output from the IS terminal. This is a diagram showing the surface potential distribution and charge distribution of the light receiving/transfer section.Although the potential diagram is drawn based on the hole energy level in this case, the operation stage of the image sensor of the present invention is the charge accumulation period. There are three stages: charge transfer operation and image signal readout operation, and these stages will be explained in order using Figures 1 to 4. Among the electron-hole pairs generated in
The gate voltage Φ1 of the first stage MOS type gate adjacent to the p full diffusion layer is at a HIGH level, but the surface potential of the p type diffusion layer is lower than that of the n type substrate layer under the gate electrode of the first stage gate. Therefore, the holes generated by photoexcitation are collected and held in the p total diffusion layer, but these holes, or positive charges, become signal charges.At time t1, the charge transfer operation starts, and Φ1 is at the LOW level)I<2 steps Since the gate voltage Φ2 of the MOS type gate is at HIGH level,
The surface potential of the n-type substrate layer under the gate electrode of the first stage MOS type gate becomes lower than that of this p total diffusion layer and the n-type substrate layer under the gate electrode of the second stage MOS type gate. A potential well is formed in the n-type substrate layer under the gate electrode of the MOS type gate. Therefore, the positive charge held in the p-all diffusion layer flows into this well. At time t2, both Φ1 and Φ2 become LOW level, and 1 The surface potentials of the n-type substrate layers under the gate electrodes of the MOS type gates in the first and second stages are the same and are lower than those of the p-type full diffusion layer of the photodiode and the p-type full-diffusion layer of the small junction capacitance. A potential well was created that spanned the n-type substrate layer under the gate electrode of the MOS gates in the first and second stages, but the potential was held in the potential well in the n-type substrate layer under the gate electrode of the first stage MOS gate. Although the positive charge spreads and is distributed in the newly created potential well and is held, at time ts, Φ1 becomes HIGH level) L< Φ2 becomes LOW level, and the n-type substrate layer under the gate electrode of the second stage MOS gate. The surface potential is the first MO
The n-type substrate layer under the gate electrode of the S-type gate and the small junction capacitance p
The potential well is lower than that of the entire diffusion layer, and a potential well is formed in the n-type substrate layer under the gate electrode of the second-stage MOS gate. The positive charges that were distributed and held in the potential well spanning the layers gather in this well. At time t4, both Φ1 and Φ2 become HIGH level, and the surface potential of the entire p-diffusion layer with small junction capacitance is It is lower than that of the n-type substrate layer under the gate electrode of the second-stage MOS gate (and a potential well is formed in this p total diffusion layer. Therefore, the n-type substrate layer under the gate electrode of the second-stage MOS gate The positive charges held in the potential wells are collected in the potential wells of the entire p-diffused layer with small junction capacitances. This charge transfer operation is performed at the same timing for all pixels, and the signal charges of each pixel are transferred by their respective small junction capacitances. When the state is maintained, the image signal is read out by the scanning pulse from the scanning shift register.
Even if pixels are sequentially accessed and reset, pixel a is first accessed by the scan pulse output to the A1 terminal, and the access n-channel MOSFET 5a is turned ON.
An anode voltage, which is a voltage converted in proportion to the amount of signal charge in the small junction capacitance 3a, is connected to an n-channel M for amplification.
Depending on the gate voltage, an n-channel MOSFET 4a for amplification and an n-channel MOSFET 4a for access are connected to the gate of OSFET4a.
The output current flowing through channel MOSFET 5a is I
Even if it is taken out as an image signal from the S terminal, as mentioned earlier, the scanning pulse accesses the pixel and resets the previous pixel at the same time, so the pixel that has been accessed is reset at the timing of the access of the next pixel. In other words, in the case of pixel a, although it is reset at the timing when the pixel is accessed, the reset n-channel MOSFET 6a is 0NI - the terminal voltage of the small junction capacitance 3a is reset to VDD - VBB.
Similarly, access and reset operations are sequentially performed for pixels b to d, and the reading of image signals from all pixels is completed.Then, the three operation steps described above are repeated.

In this way, when the image sensor of the present invention is used, the positive charge generated in the photodiode is efficiently transferred to the small junction capacitance by the two-stage MOS gate. The fact that it is smaller than that of a diode and the relational expression of V=Q/C is correct.The transferred charge generates a voltage in the small junction capacitance that is higher than the voltage obtained by directly detecting the terminal voltage of the photodiode. Therefore, this voltage is applied to the amplifying MOSFE
High output can be obtained by receiving the signal at the gate of T and amplifying it.
l, compared to MOS and amplified MOS image sensors
It is also possible to create a more sensitive image sensor.
The image sensor of the present invention & other drive capacitances are mainly the gate capacitance of a two-stage MOS type gate and the access MOSFET
When only the gate capacitance of the MOS FET for reset and reset is small, the transfer time is longer than the scanning clock time (although it may take longer). Effects of the Invention As described above, according to the present invention, a photodiode, at least two stages of MOS type gates, a small junction capacitance amplification FET having a junction capacitance smaller than that of the photodiode, an access FET, and a reset FET can be used. By providing a scanning shift register for sequentially driving these FETs and pixels, it is possible to provide an image sensor that is highly sensitive and easy to drive, making it extremely useful in practice.

[Brief explanation of the drawing]

Figure 1 is an equivalent circuit diagram of the image sensor of the present invention. Figure 2 is a cross-sectional diagram of the device structure of the light receiving/transfer section of the image sensor of the present invention. Figure 3 is the timing of charge transfer pulse input, scanning pulse input, and image signal output waveform. Figure 4 shows the surface potential distribution and charge distribution of the light receiving/transfer section at each time shown in Figure 3. Figure 5 is an equivalent circuit diagram of a conventional amplification type MOS image sensor. ...Photodiode, 2a-2d...
・Two-stage MOS type gate, 3a to 3d...small junction capacitance, 4a to 4d - n-channel MOSFET for amplification
, 5a to 5d... n-channel MOSFET for access
. 6a to 6d...N-channel MOS F for reset
ET. 7a-7d...photodiode, 8a-8d...
- MOSFET for amplification, 9a to 9d-- MOSFET for access, 10a to 10d... MOSFET for reset. Name of agent: Patent attorney Akira Okaji and two others Figure l z

Claims (2)

[Claims] (1) A photodiode, at least two stages of MOS type gates provided adjacent to the photodiode to transfer signal charges accumulated in the photodiode, and the MOS
A small junction capacitance having a smaller junction capacitance than the photodiode provided adjacent to the rear stage of the type gate, and a gate electrode for receiving and amplifying the voltage generated at the small junction capacitance pn junction due to the transferred charge. Field effect transistor (FET), access FET, reset F
An image sensor comprising: a pixel consisting of an ET; and a scanning shift register for sequentially driving the access FET and the reset FET. (2) Claim (1) characterized in that the gate electrode of the first MOS type gate and the gate electrode of the second MOS type gate are commonly connected between the pixels, and transfer pulses are sequentially applied outside the scanning period. The image sensor described.