JPH0415302U

JPH0415302U -

Info

Publication number: JPH0415302U
Application number: JP5578890U
Authority: JP
Priority date: 1990-05-28
Filing date: 1990-05-28
Publication date: 1992-02-07

Description

[Brief explanation of the drawing]

第１図はこの考案のスイツチドライン形移相器
の一実施例を示す斜視図、第２図はこの考案の他
の実施例を示す斜視図、第３図は従来のスイツチ
ドライン形移相器の一例を示す斜視図である。第１図、第３図において、１は半導体基板、２
は地導体、３はＲＦスイツチ、４は入出力線路、
５はＦＥＴ、５ａはゲート電極、５ｂはソース電
極、５ｃはドレイン電極、６はインダクタ用線路
、７は分布定数バイアス回路、７ａは高インピー
ダンス線路、７ｂは低インピーダンス線路、７ｃ
はバイアス端子、８は基準線路、９は遅延線路、
１０はインバータ回路、１１は導電性線路、１２
はＦＥＴ、１３は抵抗、１４は電源端子、１５は
接地端子である。また第２図において７は集中定
数バイアス回路、７ａは抵抗、７ｂはキヤパシタ
、７ｃはバイアス端子、７ｄは接地端子である。
なお、図中同一符号は同一または相当部分を示す
。 Fig. 1 is a perspective view showing one embodiment of a switched line phase shifter of this invention, Fig. 2 is a perspective view showing another embodiment of this invention, and Fig. 3 is a conventional switched line phase shifter. It is a perspective view showing an example. In FIGS. 1 and 3, 1 is a semiconductor substrate, 2
is the ground conductor, 3 is the RF switch, 4 is the input/output line,
5 is a FET, 5a is a gate electrode, 5b is a source electrode, 5c is a drain electrode, 6 is an inductor line, 7 is a distributed constant bias circuit, 7a is a high impedance line, 7b is a low impedance line, 7c
is a bias terminal, 8 is a reference line, 9 is a delay line,
10 is an inverter circuit, 11 is a conductive line, 12
is an FET, 13 is a resistor, 14 is a power supply terminal, and 15 is a ground terminal. Further, in FIG. 2, 7 is a lumped constant bias circuit, 7a is a resistor, 7b is a capacitor, 7c is a bias terminal, and 7d is a ground terminal.
Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims

[Scope of utility model registration request]

It consists of an input/output line formed by a strip line on a dielectric substrate, a semiconductor element placed in contact with the input/output line, and a strip line for applying a bias voltage or bias current to the electrode of the semiconductor element. In a switched line phase shifter, the output portions of two RF switches each consisting of a bias circuit are connected by a reference line and a delay line consisting of a strip line.
A bias circuit for applying bias voltage or bias current to the electrodes of two semiconductor elements by connecting the electrodes of two semiconductor elements to which bias voltage or bias current is applied through an inverter circuit composed of semiconductor elements, resistors, etc. A switched line phase shifter characterized by halving the number of phase shifters.