JPH0415324U - - Google Patents
Info
- Publication number
- JPH0415324U JPH0415324U JP5633590U JP5633590U JPH0415324U JP H0415324 U JPH0415324 U JP H0415324U JP 5633590 U JP5633590 U JP 5633590U JP 5633590 U JP5633590 U JP 5633590U JP H0415324 U JPH0415324 U JP H0415324U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- pulse
- signals
- signal processing
- digitized
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000630 rising effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 1
Landscapes
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Description
第１図は、本考案の信号処理回路の一実施例の
構成を示すブロツク図、第２図は、第１図のパル
スエツジ変調回路の一構成例を示すブロツク図、
第３図は、第２図の回路の各部の信号を示す波形
図、第４図は、２次のデルタ・シグマ方式による
Ａ／Ｄ変換回路の構成を示すブロツク図、第５図
は、従来の加算回路の一例の構成を示すブロツク
図である。
１２……デイジタル加算回路、１４……ＰＥＭ
変換回路、１４Ａ，１４Ｃ……ＰＥＭ変換器、１
６……アナログ減算器。
FIG. 1 is a block diagram showing the configuration of an embodiment of the signal processing circuit of the present invention, and FIG. 2 is a block diagram showing an example of the configuration of the pulse edge modulation circuit of FIG. 1.
FIG. 3 is a waveform diagram showing the signals of each part of the circuit in FIG. FIG. 2 is a block diagram showing the configuration of an example of an adder circuit. 12...Digital addition circuit, 14...PEM
Conversion circuit, 14A, 14C...PEM converter, 1
6...Analog subtractor.
Claims (1)
ジタル化された複数の信号をデイジタル加算する
加算回路と、 前記加算回路の出力に応じた立上りおよび立下
りを有するパルスを出力するパルス幅変調回路と
を備える信号処理回路。[Claims for Utility Model Registration] An adder circuit that digitally adds a plurality of signals each digitized by a second-order delta-sigma method, and outputs a pulse having a rising edge and a falling edge depending on the output of the adding circuit. A signal processing circuit comprising a pulse width modulation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5633590U JPH0415324U (en) | 1990-05-28 | 1990-05-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5633590U JPH0415324U (en) | 1990-05-28 | 1990-05-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0415324U true JPH0415324U (en) | 1992-02-07 |
Family
ID=31580067
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5633590U Pending JPH0415324U (en) | 1990-05-28 | 1990-05-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0415324U (en) |
-
1990
- 1990-05-28 JP JP5633590U patent/JPH0415324U/ja active Pending