JPH04157713A - Laminated ceramic capacitor - Google Patents

Laminated ceramic capacitor

Info

Publication number
JPH04157713A
JPH04157713A JP28272590A JP28272590A JPH04157713A JP H04157713 A JPH04157713 A JP H04157713A JP 28272590 A JP28272590 A JP 28272590A JP 28272590 A JP28272590 A JP 28272590A JP H04157713 A JPH04157713 A JP H04157713A
Authority
JP
Japan
Prior art keywords
internal electrodes
electrodes
internal
electrode
melting point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28272590A
Other languages
Japanese (ja)
Inventor
Nagato Omori
長門 大森
Harunobu Sano
晴信 佐野
Yoshiaki Kono
芳明 河野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP28272590A priority Critical patent/JPH04157713A/en
Publication of JPH04157713A publication Critical patent/JPH04157713A/en
Pending legal-status Critical Current

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  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PURPOSE:To obtain a laminated ceramic capacitor whose cost is low and whose manufacturing process is simple by a method wherein an internal electrode is formed of a metal material whose melting point is equal to or lower than the baking temperature of a dielectric ceramic and a semiconductor layer is formed between an edge where the internal electrode has been exposed and an external electrode. CONSTITUTION:At this laminated capacitor, external electrodes 6, plated films 7 of nickel, copper or the like and plated films 8 of solder, tin or the like have been formed, via semiconductor layers 5, on both edges of a laminated dielectric ceramic 1 obtained by laminating a plurality of dielectric ceramics 2 via internal electrodes 3; it is formed as a chip type in a rectangular parallelepiped shape. Since the semiconductor layers are formed between the internal electrodes and the external electrodes in this constitution, the internal electrodes and the external electrodes are connected electrically, and the internal electrodes are shut off from the outside by the semiconductor layers and are in a completely hermetically sealed state. Thereby, even when the capacitor is baked at a temperature which is equal to or higher than the melting point of the internal electrodes, the internal electrodes which have been melted do not flow out to the outside, a cohesion is not caused and only the surface of an electrode material is oxidized.

Description

【発明の詳細な説明】 11上Ω■貝分! 本発明は、内部電極が層状に埋設された積層誘電体セラ
ミックの両端に外部電極が配設きれた積層セラミックコ
ンデンサに関する。
[Detailed description of the invention] 11 ohms ■ shells! The present invention relates to a multilayer ceramic capacitor in which external electrodes are disposed at both ends of a multilayer dielectric ceramic in which internal electrodes are embedded in layers.

従米虫韮璽 積層セラミックコンデンサは各誘電体セラミックの間に
内部電極を層状に埋設して積層誘電体セラミックを形成
し、さらに、この積層誘電体セラミックの両端の内部電
極露出面に外部電極を形成したものが一般的である。
A multilayer ceramic capacitor made by Nihon Mushi has internal electrodes embedded in layers between each dielectric ceramic to form a multilayer dielectric ceramic, and external electrodes are formed on the exposed surfaces of the internal electrodes at both ends of this multilayer dielectric ceramic. Those that did are common.

ところで、この種の積層セラミックコンデンサにあって
は、内部電極の材料として、誘電体セラミックの焼成温
度と同等ないしはそれよりも低い融点を有する金属又は
合金を使用すると、焼成時に内部電極である金属材料が
溶融し、凝集したり、内部電極露出面から外部に流出し
たりすることにより、いわゆる内部電極切れを起こして
しまうか、あるいは内部電極が酸化してしまうため、容
量を取り出すことができないという問題点を有している
。このような理由から、積層セラミックコンデンサの内
部電極材料としては、誘電体セラミックが焼結する温度
よりも高融点でかつ酸化しにくい金属が用いられていた
By the way, in this type of multilayer ceramic capacitor, if a metal or alloy having a melting point equal to or lower than the firing temperature of the dielectric ceramic is used as the material for the internal electrodes, the metal material that is the internal electrodes will melt during firing. The problem is that the capacitance cannot be taken out because the internal electrodes melt, aggregate, or leak out from the exposed surface of the internal electrodes, causing so-called internal electrode breakage, or because the internal electrodes become oxidized. It has points. For these reasons, metals that have a higher melting point than the sintering temperature of dielectric ceramics and are less likely to oxidize have been used as internal electrode materials for multilayer ceramic capacitors.

他方、特開昭63−249319号公報に示されるよう
に、焼成したセラミック薄板を厚膜法により形成した導
体層(導体ペーストあるいは導体接着剤で形成)あるい
はガラス層で接着接合したり、各層のセラミック薄板の
間に空隙を設けることなく、ガラス層をセラミック薄板
間に形成し、比較的低温で溶着できる材料によりセラミ
ック薄板を多層化して重ね接合することで、低融点金属
を内部電極とした積層セラミックコンデンサが提案され
ている。
On the other hand, as shown in Japanese Unexamined Patent Publication No. 63-249319, fired ceramic thin plates are adhesively bonded with a conductor layer (formed with conductor paste or conductor adhesive) or a glass layer formed by a thick film method, or each layer is By forming a glass layer between the thin ceramic plates without creating any gaps between them, and by stacking and bonding the ceramic thin plates in multiple layers using materials that can be welded at relatively low temperatures, we can create a laminated structure with a low-melting point metal as the internal electrode. Ceramic capacitors have been proposed.

明が解決しようとする課 しかしながら、従来の積層セラミックコンデンサでは、
誘電体セラミック層の焼成温度が1200°C以上と高
温であるため、融点が高く、かつ高温で酸化しにくい白
金やパラジウム等が使用されているが、これらの材料は
高価であるため、積層セラミックコンデンサのコストア
ップの原因となっていた。
However, with conventional multilayer ceramic capacitors,
Since the dielectric ceramic layer is fired at a high temperature of 1200°C or higher, materials such as platinum and palladium, which have a high melting point and are difficult to oxidize at high temperatures, are used, but these materials are expensive, so multilayer ceramic This caused an increase in the cost of capacitors.

また、積層セラミックコンデンサの低価格化のために内
部電極の材料を高価な白金、パラジウムから安価なパラ
ジウム−銀、銀、卑金属にする試みがなされている。し
かし、安価なパラジウム−銀、銀、卑金属を内部電極と
するためには、これらの金属の融点よりも低い温度で焼
結可能な誘1体セラミックが必要とされるため、誘電体
セラミックの組成物としては限定されていた。
Furthermore, in order to lower the price of multilayer ceramic capacitors, attempts have been made to change the material of the internal electrodes from expensive platinum and palladium to inexpensive palladium-silver, silver, and base metals. However, in order to use inexpensive palladium-silver, silver, or base metals as internal electrodes, a dielectric ceramic that can be sintered at a temperature lower than the melting point of these metals is required, so the composition of the dielectric ceramic is As a matter of fact, it was limited.

他方、前記特開昭63−249319号公報に開示され
た構造を有する積層セラミックコンデンサは、広範囲に
わたり誘電体セラミック組成物を選択することができ、
低融点の金属を内部電極にすることができる。しかし、
その製造工程が複雑であり、製造コストがかかり、積層
セラミックコンデンサの低価格化の障害となる。
On the other hand, in the multilayer ceramic capacitor having the structure disclosed in JP-A No. 63-249319, a dielectric ceramic composition can be selected from a wide range.
A metal with a low melting point can be used as the internal electrode. but,
The manufacturing process is complicated and the manufacturing cost is high, which is an obstacle to lowering the price of multilayer ceramic capacitors.

それゆえ、本発明の主たる課題は、誘電体セラミックの
焼成温度よりも高い融点をもつ内部電極材料を使用しな
ければならないという問題点を解消し、広範囲にわたり
誘電体セラミック組成物を選択することができる低コス
トで製造工程が簡易な積層セラミックコンデンサを提供
することにある。
Therefore, the main object of the present invention is to solve the problem of having to use an internal electrode material with a melting point higher than the firing temperature of the dielectric ceramic, and to make it possible to select a dielectric ceramic composition over a wide range. The object of the present invention is to provide a multilayer ceramic capacitor that can be manufactured at low cost and with a simple manufacturing process.

課 を解決するための手段 以上の課題を解決するために、本発明に係る積層セラミ
ックコンデンサは、内部電極が層状に埋設された積層誘
電体セラミックの両端面に外部電極が配設された積層セ
ラミックコンデンサにおいて、前記内部電極が誘1体セ
ラミックの焼成温度と同等ないしはそれよりも低い融点
を有する金属材料からなり、前記内部電極が露出した端
面と前記外部電極との間に半導体層が設けられているこ
とを特徴とする。
In order to solve the above problems, the multilayer ceramic capacitor according to the present invention is a multilayer ceramic capacitor in which external electrodes are arranged on both end faces of a multilayer dielectric ceramic in which internal electrodes are buried in layers. In the capacitor, the internal electrode is made of a metal material having a melting point equal to or lower than the firing temperature of the dielectric ceramic, and a semiconductor layer is provided between the end surface where the internal electrode is exposed and the external electrode. It is characterized by the presence of

怪−月 以上の構成により、内部電極と外部電極との間に半導体
層が形成されているので、内外両亙極は電気的には接続
されており、かつ、内部電極は半導体層により外部とは
遮断されて完全に密閉された状態にある。これにより、
内部電極の融点と同等ないしはそれよりも高い温度で焼
成しても、溶融した内部電極が外部へ流出することがな
く、かつ、凝集の発生もなく、電極材料の酸化も表面の
みに抑えられる。従って、積層セラミックコンデンサの
内部における電極切れあるいは外部電極との1気的接続
不良が発生せず、容量低下あるいはmW不良が解消され
る。
Due to the structure described above, a semiconductor layer is formed between the internal electrode and the external electrode, so both the internal and external electrodes are electrically connected, and the internal electrode is connected to the outside by the semiconductor layer. is closed and completely sealed. This results in
Even when fired at a temperature equal to or higher than the melting point of the internal electrode, the molten internal electrode does not flow out, no aggregation occurs, and oxidation of the electrode material is suppressed to only the surface. Therefore, electrode breakage inside the multilayer ceramic capacitor or failure of connection with the external electrode does not occur, and the capacitance drop or mW failure is eliminated.

実施例 以下、本発明の実施例を添付図面に基づいて説明する。Example Embodiments of the present invention will be described below with reference to the accompanying drawings.

本発明に係る積層セラミックコンデンサは、第1図に示
す様に、内部電極3を介在して複数枚の誘電体セラミッ
ク2を積層して得られた積層誘電体セラミック10両端
面に以下に詳述する半導体層5を介して外部電極6及び
ニツケノ呟銅などのメツキ被膜7、半田、錫などのメツ
キ被膜8が形成きれ、直方体形状のチップタイプとされ
ている。
As shown in FIG. 1, the multilayer ceramic capacitor according to the present invention has a multilayer dielectric ceramic 10 obtained by stacking a plurality of dielectric ceramics 2 with internal electrodes 3 interposed between the two end faces. An external electrode 6, a plating film 7 of Nikkeno copper, etc., and a plating film 8 of solder, tin, etc. are formed through the semiconductor layer 5, and the chip type is a rectangular parallelepiped.

次に、製造工程順に説明する。Next, the manufacturing steps will be explained in order.

まず、積層誘電体セラミック1を形成する。この積層誘
1体セラミック1は次のようにして製造される。つまり
、第2図に示すように、材料粉末をスラリー化してシー
ト状に延ばしたit体セラミック2(グリーンシート)
を用意し、その−面に導電ペーストを塗布し内部電極3
となる導電ペースト層を形成する。内部電極3となる導
電ベースト層を有する誘電体セラミック2は必要枚数積
層され、第3図に示す如く、内部電極3を膚しない誘電
体セラミック4にて挾んで圧着し、積層体とする。
First, the laminated dielectric ceramic 1 is formed. This laminated dielectric ceramic 1 is manufactured as follows. In other words, as shown in Figure 2, it is a ceramic 2 (green sheet) made by slurrying material powder and rolling it out into a sheet.
Prepare the internal electrode 3 by applying conductive paste on its negative side.
Form a conductive paste layer. A required number of dielectric ceramics 2 having a conductive base layer which will become the internal electrodes 3 are laminated, and as shown in FIG. 3, the internal electrodes 3 are sandwiched and crimped with dielectric ceramics 4 that do not expose the internal electrodes 3 to form a laminate.

次に、この積層体の両端面に半導体層5を形成する。こ
の半導体層5は、例えば、誘電体セラミックを半導体化
きせる半導体化剤にバインダを混入したペースト、ある
いは誘電体セラミックに含まれるセラミック粉末に前記
半導体化剤を混合したものにバインダを混入したペース
トを塗布し、所定の温度にて焼成することにより形成さ
れる。
Next, semiconductor layers 5 are formed on both end faces of this laminate. This semiconductor layer 5 is made of, for example, a paste in which a binder is mixed with a semiconducting agent that converts the dielectric ceramic into a semiconductor, or a paste in which a binder is mixed in the ceramic powder contained in the dielectric ceramic and the above-mentioned semiconducting agent. It is formed by coating and firing at a predetermined temperature.

続いて、以上の如く焼成された積層誘電体セラミック1
の端面に、外部電極6を形成する。この外部電極6は、
銀等の金属粉末からなる導電性ペーストを塗布した後焼
付けにより形成され、前記半導体層5の表面を覆う。こ
の後、外部電極6上にニッケル、銅などのメツキを施し
、メツキ被膜7を形成する。最後に、このメツキ被膜7
の上に半田、錫などのメツキを施してメツキ被膜8を形
成し、チップ型の積層セラミックコンデンサを得る。
Subsequently, the laminated dielectric ceramic 1 fired as described above is
External electrodes 6 are formed on the end faces of. This external electrode 6 is
It is formed by applying and baking a conductive paste made of metal powder such as silver, and covers the surface of the semiconductor layer 5. Thereafter, plating with nickel, copper, etc. is applied to the external electrodes 6 to form a plating film 7. Finally, this plating film 7
A plating film 8 is formed by plating with solder, tin, etc., to obtain a chip-type multilayer ceramic capacitor.

具体的には、誘電体セラミックの組成材料として、主成
分がBa″ribs :84mo1%、Ca5nOg 
: 10mo1%、Carrys : 6 mo1%か
らなるものlQQwt%(二対し、MnOを1冒t%の
割合で添加した組成番ζ表1番こ示す焼結助剤を20〜
25wt%の割合で添加した混合粉末を用いた。
Specifically, as the composition material of the dielectric ceramic, the main components are Ba"ribs: 84 mo1%, Ca5nOg
: 10 mo1%, Carrys: 6 mo1% lQQwt% (composition number ζ where MnO is added at a ratio of 1 t%)
A mixed powder added at a ratio of 25 wt% was used.

[以下余白コ 前記原料粉末にバインダとしてPVA(ポリビニルアル
コール)を用いると共に、界面活性剤、分散剤及び水を
加えて混練し、スラリーを得た。
[Margin below] Using PVA (polyvinyl alcohol) as a binder, a surfactant, a dispersant, and water were added and kneaded to the raw material powder to obtain a slurry.

続いて、このスラリーをドクターブレード法によりシー
ト状に形成し、厚み35μmのグリーンシートを形成し
た。この後、グリーンシートの一面にA1の導電ペース
トをスクリーン印刷法にて印刷し、第2図に示す内部電
極3となる導電ペースト層を形成した。内部電極3とな
る導電ペースト層を有するグリーンシートは、所要の静
電容量に応じて複数枚が積層きれる。この際、内部電極
3と電気的に接続される一端部2aと、接続されない他
端部2bとが交互に積み重ねられる(第3図参照)。き
らに、この状態で熱圧着されることにより、内部電極3
が端部2a、 2bに露出していない未焼成の積層体が
得られた。
Subsequently, this slurry was formed into a sheet by a doctor blade method to form a green sheet with a thickness of 35 μm. Thereafter, a conductive paste of A1 was printed on one side of the green sheet by screen printing to form a conductive paste layer that would become the internal electrodes 3 shown in FIG. A plurality of green sheets having a conductive paste layer serving as the internal electrodes 3 can be stacked according to the required capacitance. At this time, one end 2a that is electrically connected to the internal electrode 3 and the other end 2b that is not connected are stacked alternately (see FIG. 3). By being thermocompressed in this state, the internal electrode 3
An unfired laminate was obtained in which the edges 2a and 2b were not exposed.

次に、この積層体の両端面に、内部電極3と電気的に接
続される半導体層5を形成する。この半導体層5は、半
導体化剤として10能%のLazosに対してエチルセ
ルロース樹脂、プチルセロソルプ溶剤からなるペースト
を加えて混練し、半導体化剤ペーストを得た。そして、
このペーストを前記積層体の両端面に塗布した。さらに
、この積層体を乾燥した後、空気中においてA1内部電
極3の融点660℃よりも高い850〜900℃で2時
間焼成し、積層体の磁器化と半導体層5の形成を同時に
行なった。これによって、積層体の両端面に半導体化剤
が拡散され、半導体層5と内部電極3とが電気的に接続
された構造の積層誘電体セラミック1が得られた。
Next, semiconductor layers 5 electrically connected to internal electrodes 3 are formed on both end faces of this stacked body. This semiconductor layer 5 was prepared by adding a paste consisting of ethyl cellulose resin and butylcellosolp solvent to 10% Lazos as a semiconductor agent and kneading the mixture to obtain a semiconductor agent paste. and,
This paste was applied to both end surfaces of the laminate. Furthermore, after drying this laminate, it was fired in air at 850 to 900°C, which is higher than the melting point of the A1 internal electrode 3, 660°C, for 2 hours, thereby making the laminate into a ceramic and forming the semiconductor layer 5 at the same time. As a result, the semiconductor forming agent was diffused into both end faces of the laminate, and a laminate dielectric ceramic 1 having a structure in which the semiconductor layer 5 and the internal electrode 3 were electrically connected was obtained.

続いて、前記積層誘電体セラミック1の両端面に外部電
極6を形成する。この外部電極6は、半導体層5を形成
したPii端面に銀ペーストを塗布し、空気中にて80
0℃で焼き付けることにより形成した。この後、この外
部電極6の上にメツキ被膜7を形成する。このメツキ材
としては、硫酸ニッケルあるいは塩化ニッケルとホウ酸
からなるニッケルメッキ液を用意し、バレルメッキ法に
て外部電極6上にニッケルメッキした。最後に、このメ
ツキ被膜7の上にメツキ被膜8を形成した。このメツキ
には、AS浴(アルカノールスルホン酸)からなる半田
メツキ液を用意し、バレルメッキ法にてメツキ被膜7上
に半田メツキした。
Subsequently, external electrodes 6 are formed on both end surfaces of the laminated dielectric ceramic 1. This external electrode 6 is made by applying silver paste to the Pii end face on which the semiconductor layer 5 is formed, and leaving it in the air for 80 minutes.
It was formed by baking at 0°C. Thereafter, a plating film 7 is formed on the external electrode 6. As this plating material, a nickel plating solution consisting of nickel sulfate or nickel chloride and boric acid was prepared, and nickel was plated on the external electrode 6 by barrel plating. Finally, a plating film 8 was formed on this plating film 7. For this plating, a solder plating solution made of an AS bath (alkanol sulfonic acid) was prepared, and the plating film 7 was soldered using a barrel plating method.

この様にして形成された第1図に示す積層セラミックコ
ンデンサは、下記の通りである。
The multilayer ceramic capacitor shown in FIG. 1 formed in this manner is as follows.

外形寸法 幅=      3.2mm長啓:    
  1.6mm 厚み:      1.2mt。
External dimensions Width = 3.2mm long:
1.6mm Thickness: 1.2mt.

セラミック単位厚さ:20μm 有効誘電体総数:19 一層当りの対向電極面積:  1.3mm2本実施例の
積層セラミックコンデンサの電気的特性を知るために従
来品を比較例として同一条件の下に試験を行なった。
Ceramic unit thickness: 20μm Total number of effective dielectrics: 19 Opposing electrode area per layer: 1.3mm2 In order to understand the electrical characteristics of the multilayer ceramic capacitor of this example, a conventional product was used as a comparative example and tested under the same conditions. I did it.

まず、自動ブリッジ式測定器を用い、各試料に1k)l
□ IVrmsの電圧を印加して静電容量(C)及び誘
電損失(tanδ〉を測定した。次に、+20°Cを基
準とした一25〜+85°Cの温度範囲で誘電率の温度
特性を測定した。以上の試験による測定結果を表2に示
す。
First, using an automatic bridge measuring instrument, 1k)l was added to each sample.
□ The capacitance (C) and dielectric loss (tan δ) were measured by applying a voltage of IVrms. Next, the temperature characteristics of the dielectric constant were measured in the temperature range of -25 to +85 °C with +20 °C as the standard. The results of the above tests are shown in Table 2.

乙のように実施例において、従来の積層セラミックコン
デンサは、はとんど特性が得られないのに対し、本発明
例の積層セラミックコンデンサでは、内部電極の融点と
同等ないしはそれよりも高い温度で焼成しても、電気的
特性の十分なものが得られた。
In the example shown in Example B, conventional multilayer ceramic capacitors rarely have good characteristics, whereas the multilayer ceramic capacitor according to the present invention has a temperature that is equal to or higher than the melting point of the internal electrode. Even after firing, sufficient electrical properties were obtained.

即ち、A1内部電極の融点である660°Cよりも高い
850〜900℃で焼成した場合、比較例は静電容量(
C)が全く得られなかった。これは、積層誘電体セラミ
ックの間に埋設されている内部電極3が外部電極6と電
気的に適正に接続されていない、あるいは電極切れを起
こしていることを示すものである。即ち、A1内部電極
の融点である660℃よりも高い温度で焼成したために
焼成時に内部電極3が溶融し、積層セラミックコンデン
サの端部より流出したか、あるいは凝集していることを
裏づけるものである。
That is, when fired at 850 to 900°C, which is higher than the melting point of the A1 internal electrode, 660°C, the comparative example has a capacitance (
C) was not obtained at all. This indicates that the internal electrode 3 buried between the laminated dielectric ceramics is not electrically connected properly to the external electrode 6, or that the electrode is broken. In other words, this confirms that the internal electrode 3 was melted during firing because it was fired at a temperature higher than 660°C, which is the melting point of the A1 internal electrode, and it either flowed out from the end of the multilayer ceramic capacitor or was agglomerated. .

そこで、確認のため、比較例のユニットを樹脂にて固め
、さらに研摩を行ない、光学顕微鏡にて断面を観察した
。その結果、全ての内部電極3の端部において内部電極
の溶出による空隙層が見られた。
Therefore, for confirmation, the unit of the comparative example was hardened with resin, further polished, and the cross section was observed using an optical microscope. As a result, void layers due to elution of the internal electrodes were observed at the ends of all internal electrodes 3.

一方、本発明例は、静電容量(C)が焼成温度850〜
900℃で10nF以上あり、誘電損失(tan&>も
0.9〜1.0%であった。比較例と同様に断面観察を
行なったところ、内部電極3の玉状の凝集が見られず、
また空隙層も見られなかった。これは、内部電極が外部
へ溶出していないことを示すもので、内部電極の融点よ
りも高い温度で焼成した際、内部電極が溶融しても、半
導体層5によって外部への溶出が遮断され、誘電体セラ
ミック2の間に介在する内部電極3は、焼成前と同様の
状態で保持されることが確認された。
On the other hand, in the example of the present invention, the capacitance (C) was at a firing temperature of 850~
It was 10 nF or more at 900°C, and the dielectric loss (tan&> was also 0.9 to 1.0%. When the cross section was observed in the same manner as in the comparative example, no bead-shaped aggregation of the internal electrodes 3 was observed.
Moreover, no void layer was observed. This indicates that the internal electrodes are not eluted to the outside. Even if the internal electrodes melt when fired at a temperature higher than the melting point of the internal electrodes, the semiconductor layer 5 blocks the leaching to the outside. It was confirmed that the internal electrode 3 interposed between the dielectric ceramics 2 was maintained in the same state as before firing.

なお、本発明に係る積層セラミックコンデンサは前記実
施例に限定されるものではなく、その要旨の範囲内で種
々に変更可能である。
Note that the multilayer ceramic capacitor according to the present invention is not limited to the above-mentioned embodiments, and can be variously modified within the scope of the gist.

特に、半導体層5を形成するための半導体化剤は種々の
組成成分のものを用いることができ、誘電体セラミック
材料等も同様である。また、半導体化剤を積層体の両端
面に付着きせる方法は、スパッタリング、気相蒸着、ス
プレー、浸漬等種々の手法が採用可能であり、これらの
手法は外部電極6を形成する際にも採用可能である。
In particular, the semiconductor agent for forming the semiconductor layer 5 can have various compositions, and the same applies to dielectric ceramic materials and the like. In addition, various methods such as sputtering, vapor phase deposition, spraying, and dipping can be used to attach the semiconducting agent to both end surfaces of the laminate, and these methods can also be used when forming the external electrodes 6. It is possible.

発明の効果 以上詳述した様に、本発明によれば、積層誘電体セラミ
ックの両端面と外部電極との間に半導体層を形成したた
め、内部電極の融点よりも高い温度で焼成する際、溶融
した内部電極は半導体層にて外部と遮断され、外部へ流
出することが防止される。従って、積層セラミックコン
デンサの内部における電極切れ、あるいは外部電極との
電気的接続不良が解消される。換言すれば、内部電極と
して融点が必ずしも焼成温度よりも高い材料を使用する
必要はなく、よって融点の低い安価な材料を使用し、低
コストの積層セラミックコンデンサを通常の製作工程に
て得ることが可能となった。
Effects of the Invention As detailed above, according to the present invention, since a semiconductor layer is formed between both end faces of the laminated dielectric ceramic and the external electrode, melting does not occur when firing at a temperature higher than the melting point of the internal electrode. The internal electrodes are isolated from the outside by the semiconductor layer and are prevented from leaking to the outside. Therefore, disconnection of the electrode inside the multilayer ceramic capacitor or poor electrical connection with the external electrode is eliminated. In other words, it is not necessary to use a material with a melting point higher than the firing temperature for the internal electrodes, and therefore it is possible to use an inexpensive material with a low melting point and obtain a low-cost multilayer ceramic capacitor through normal manufacturing processes. It has become possible.

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本発明の実施例を示し、第1図は積層セラミック
コンデンサの中央縦断面図、第2図は積層前の誘電体セ
ラミックの平面図、第3図は第2図のものの誘電体セラ
ミック積層時の分解斜視図である。 1・・・積層誘電体セラミック、2・・・誘電体セラミ
ック、3・・・内部電極、5・・・半導体層、6・・・
外部電極、7・・・メツキ被膜、8・・・メツキ被膜。 特許出願人   株式会社村田製作所 代理人弁理士  森 下 武 − 第1図 第2図
The drawings show embodiments of the present invention; FIG. 1 is a central vertical cross-sectional view of a multilayer ceramic capacitor, FIG. 2 is a plan view of a dielectric ceramic before lamination, and FIG. 3 is a dielectric ceramic laminate similar to that shown in FIG. 2. FIG. DESCRIPTION OF SYMBOLS 1... Laminated dielectric ceramic, 2... Dielectric ceramic, 3... Internal electrode, 5... Semiconductor layer, 6...
External electrode, 7... plating film, 8... plating film. Patent applicant Takeshi Morishita, patent attorney representing Murata Manufacturing Co., Ltd. - Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] 1.内部電極が層状に埋設された積層誘電体セラミック
の両端面に外部電極が配設された積層セラミックコンデ
ンサにおいて、 前記内部電極が誘電体セラミックの焼成温度と同等ない
しはそれよりも低い融点を有する金属材料からなり、 前記内部電極が露出した端面と前記外部電極との間に半
導体層が設けられていること、 を特徴とする積層セラミックコンデンサ。
1. In a multilayer ceramic capacitor in which external electrodes are arranged on both end faces of a multilayer dielectric ceramic in which internal electrodes are embedded in layers, the internal electrodes are made of a metal material having a melting point equal to or lower than the firing temperature of the dielectric ceramic. A multilayer ceramic capacitor comprising: a semiconductor layer provided between the end face where the internal electrode is exposed and the external electrode.
JP28272590A 1990-10-20 1990-10-20 Laminated ceramic capacitor Pending JPH04157713A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28272590A JPH04157713A (en) 1990-10-20 1990-10-20 Laminated ceramic capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28272590A JPH04157713A (en) 1990-10-20 1990-10-20 Laminated ceramic capacitor

Publications (1)

Publication Number Publication Date
JPH04157713A true JPH04157713A (en) 1992-05-29

Family

ID=17656233

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28272590A Pending JPH04157713A (en) 1990-10-20 1990-10-20 Laminated ceramic capacitor

Country Status (1)

Country Link
JP (1) JPH04157713A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0589702A2 (en) 1992-09-24 1994-03-30 Canon Kabushiki Kaisha Image processing method and apparatus
US11361901B2 (en) 2019-06-07 2022-06-14 Murata Manufacturing Co., Ltd. Multilayer ceramic electronic component with glass component, plating layer, and semiconductor layer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0589702A2 (en) 1992-09-24 1994-03-30 Canon Kabushiki Kaisha Image processing method and apparatus
US11361901B2 (en) 2019-06-07 2022-06-14 Murata Manufacturing Co., Ltd. Multilayer ceramic electronic component with glass component, plating layer, and semiconductor layer

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