JPH0416093A - Interface circuit dispersed mount system - Google Patents
Interface circuit dispersed mount systemInfo
- Publication number
- JPH0416093A JPH0416093A JP12028890A JP12028890A JPH0416093A JP H0416093 A JPH0416093 A JP H0416093A JP 12028890 A JP12028890 A JP 12028890A JP 12028890 A JP12028890 A JP 12028890A JP H0416093 A JPH0416093 A JP H0416093A
- Authority
- JP
- Japan
- Prior art keywords
- interface circuit
- shelf
- multiplex transmission
- circuit
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims description 8
- 238000012423 maintenance Methods 0.000 abstract description 3
- 238000007689 inspection Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Landscapes
- Structure Of Telephone Exchanges (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電気通信システムにおける電話局及び電話中継
所に設置される多重伝送装置の構成法に関し、特にイン
タフェース回路の実装方式に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for configuring multiplex transmission equipment installed at telephone offices and telephone relay stations in telecommunications systems, and particularly to a method for mounting interface circuits.
第2図に従来の多重伝送装置の実装方式を示す。 FIG. 2 shows the implementation method of a conventional multiplex transmission device.
第2図に示すように、多重伝送装置1はN個の棚91〜
94により構成されている。この多重伝送装置1におけ
るインタフェース回路実装方式は第3図に示す構成とな
っていた。第3図において、集中クロックインタフェー
ス回路棚60は外部インタフェース10により装置外と
接続されるとともに複数の棚間クロック信号転送線81
〜83によりそれぞれ多重伝送回路棚71〜73と接続
されている。従来のインタフェース回路実装方式の特徴
は第2図に示すN個の棚91〜94のうちの1つの棚を
集中クロックインタフェース回路棚60として用い、残
りの棚を多重伝送回路棚71〜73として用いることで
ある。As shown in FIG. 2, the multiplex transmission device 1 has N shelves 91 to
94. The interface circuit mounting system in this multiplex transmission device 1 had the configuration shown in FIG. In FIG. 3, a centralized clock interface circuit shelf 60 is connected to the outside of the device by an external interface 10, and also has a plurality of inter-shelf clock signal transfer lines 81.
-83 are connected to the multiplex transmission circuit shelves 71-73, respectively. A feature of the conventional interface circuit mounting method is that one of the N shelves 91 to 94 shown in FIG. 2 is used as the centralized clock interface circuit shelf 60, and the remaining shelves are used as the multiplex transmission circuit shelves 71 to 73. That's true.
上述した従来のインタフェース回路実装方式では、クロ
ックイタフェース回路が1つの棚に集中して具備されて
いるため多重伝送回路と接続されるクロック信号転送線
が棚間接続となり信号転送用の回路が必要となるだけで
はなく、クロックインタフェース回路自体に電源回路が
必要になるなめ多重伝送装置の消費電力が大きくなる問
題がある。In the conventional interface circuit mounting method described above, the clock interface circuit is concentrated on one shelf, so the clock signal transfer line connected to the multiplex transmission circuit is connected between shelves, and a circuit for signal transfer is required. Not only that, but the clock interface circuit itself requires a power supply circuit, which causes the problem of increased power consumption of the multiplex transmission device.
また、インタフェース回路は少数の多重伝送回路槽のみ
が実装されている場合にも必要となる。The interface circuit is also required when only a small number of multiplex transmission circuit cells are installed.
いわば初期投資に含まれる回路となること、及び多重伝
送装置全体で1つのシステムとなるため検査や保守に手
数がかかることがらコスト負担が大きい問題がある。There is a problem in that the cost burden is large because the circuit is included in the initial investment, so to speak, and because the entire multiplex transmission device forms one system, inspection and maintenance are time-consuming.
さらに従来のインタフェース回路実装方式では、集中ク
ロックインタフェース回路槽のために1つの棚が使用さ
れるため多重伝送回路槽の実装数が減り、装置全体が物
理的に大形化する問題がある。Furthermore, in the conventional interface circuit mounting method, one shelf is used for the centralized clock interface circuit tank, which reduces the number of multiplex transmission circuit tanks to be mounted, and there is a problem that the entire device becomes physically large.
本発明のインタフェース回路分散実装方式は複数の棚を
実装して成る多重伝送装置において、装置外と外部イン
タフェースにより接続される分散化インタフェース回路
とこの分散化インタフェース回路に棚内信号転送線によ
り接続される多重伝送回路とを有する多重伝送システム
棚を複数個実装した構成である。The interface circuit distributed mounting method of the present invention, in a multiplex transmission device including a plurality of shelves, includes a distributed interface circuit connected to the outside of the device by an external interface, and a distributed interface circuit connected to the distributed interface circuit by an intra-shelf signal transfer line. This is a configuration in which a plurality of multiplex transmission system shelves each having a multiplex transmission circuit are mounted.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
本発明の一実施例を示す第1図を参照すると、多重伝送
装置1は全く同一のクロックインタフェース回路付多重
伝送システム棚21〜23がら構成される。クロックイ
ンタフェース回路付多重伝送システム棚21〜23のそ
れぞれは装置外と外部インタフェース10〜13によっ
て接続される分散化クロックインタフェース回路31〜
33と、分散化クロックインタフェース回H@31〜3
3と棚内クロック信号転送線51〜53によって接続さ
れる多重伝送回路41〜43とを備える。この構成によ
り、独立な集中クロックインタフェース回路槽は不要と
なり、多重伝送装置は一種類の棚のみによる構成をとる
ことが可能になる。Referring to FIG. 1 showing an embodiment of the present invention, a multiplex transmission apparatus 1 is composed of multiplex transmission system shelves 21 to 23 with identical clock interface circuits. Each of the multiplex transmission system with clock interface circuit shelves 21 to 23 has decentralized clock interface circuits 31 to 31 connected to the outside of the device by external interfaces 10 to 13.
33 and distributed clock interface times H@31-3
3 and multiplex transmission circuits 41-43 connected by intra-shelf clock signal transfer lines 51-53. This configuration eliminates the need for an independent centralized clock interface circuit box, and allows the multiplex transmission device to be configured with only one type of shelf.
なお、上記実施例においては、タロツク信号のインタフ
ェース回路の分散実装について述べたが、制御信号及び
警報信号などのインタフェース回路にも同様に実施でき
る。In the above embodiment, the distributed implementation of the interface circuit for tarok signals has been described, but the present invention can be similarly implemented for interface circuits for control signals, alarm signals, and the like.
以上説明したように本発明によれば、インタフェース回
路と多重伝送回路との接続に簡便な棚内信号線を使用で
きること、及びインタフェース回路に対する専用電源が
不要になることがら装置の消費電力の低減化が図れる。As explained above, according to the present invention, a simple in-shelf signal line can be used to connect the interface circuit and the multiplex transmission circuit, and a dedicated power supply for the interface circuit is not required, thereby reducing the power consumption of the device. can be achieved.
また、装置が全て同一の棚で構成されるため、検査、保
守が棚単位となり簡易化されること及び装置としての初
期投資分が少なくなることにより装置の経済化が図れる
。In addition, since all the devices are constructed of the same shelf, inspection and maintenance can be simplified on a shelf-by-shelf basis, and the initial investment for the device is reduced, making the device more economical.
さらに、集中インタフェース回路槽が不要となるため、
装置を小型化できる。Furthermore, since there is no need for a centralized interface circuit tank,
The device can be made smaller.
絡付多重伝送システム棚、31〜33・・・分散化クロ
ックインタフェース回路、41〜43・・・多重伝送回
路、51〜53・・・棚内クロック信号転送線。Intertwined multiple transmission system shelf, 31-33...Distributed clock interface circuit, 41-43...Multiplex transmission circuit, 51-53...Intra-shelf clock signal transfer line.
Claims (1)
と外部インタフェースにより接続される分散化インタフ
ェース回路とこの分散化インタフェース回路に棚内信号
転送線により接続される多重伝送回路とを有する多重伝
送システム棚を複数個実装したことを特徴とするインタ
フェース回路分散実装方式。A multiplex transmission device comprising a plurality of shelves, which has a decentralized interface circuit connected to the outside of the device by an external interface, and a multiplex transmission circuit connected to the decentralized interface circuit by an intra-shelf signal transfer line. An interface circuit distributed mounting method characterized by mounting multiple system shelves.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12028890A JPH0416093A (en) | 1990-05-10 | 1990-05-10 | Interface circuit dispersed mount system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12028890A JPH0416093A (en) | 1990-05-10 | 1990-05-10 | Interface circuit dispersed mount system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0416093A true JPH0416093A (en) | 1992-01-21 |
Family
ID=14782534
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12028890A Pending JPH0416093A (en) | 1990-05-10 | 1990-05-10 | Interface circuit dispersed mount system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0416093A (en) |
-
1990
- 1990-05-10 JP JP12028890A patent/JPH0416093A/en active Pending
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