JPH04170067A - Manufacture of c-mos transistor - Google Patents

Abstract

PURPOSE:To facilitate manufacture of a C-MOS transistor on an economical insulator such as a soda lime glass substrate by a method wherein crystalline semiconductor layers and low resistance n-type and p-type semiconductor layers are formed on the insulator by an ion implantation method. CONSTITUTION:Polycrystalline silicon films 2 and 3 are formed on an insulator 17 which is composed of a soda lime glass substrate and a silicon oxide film deposited on its surface. In order to activate phosphorus and boron which are contained in the polycrystalline silicon films 2 and 3 by ion implantation and phosphorus contained in n-type amorphous silicon films 18 and 19, silicon ions 20 are implanted over the whole surface. By this process, the sheet resistivity of the polycrystalline silicon film 2 into which phosphorus ions 10 are implanted is reduced from 10<7>OMEGA/square to 100OMEGA/square and the sheet resistivity of the polycrystalline silicon film 3 into which boron ions 8 are implanted is also reduced from 10<7>OMEGA/square to 300OMEGA/square and source region 11 and drain region 12 which are low resistance n-type silicon layers and source region 13 and drain region 14 which are low resistance p-type silicon layers are formed. With this constitution, a C-MOS transistor can be manufactured by employing an economical insulator such as the soda lime glass substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a CMOS transistor on an insulator, and particularly to a method for manufacturing a CMOS transistor in which a low-resistance semiconductor layer is formed.

[Prior Art] Conventionally, a manufacturing method as shown in FIG. 3 has been known for forming a CMOS transistor on an insulator. First, as shown in (a), a polycrystalline silicon film is formed on an insulator 1, and patterns of polycrystalline silicon films 2 and 3 are formed in regions that will become n- and p-channel MOS transistors in the future. Silicon dioxide (Si0
2) 114 is formed to form a pattern of an n-type polycrystalline silicon film that will become gate regions 5 and 6 in the future. (b
), the area other than the area that will become a p-channel MOS transistor in the future is covered with a photoresist 7, boron (B) ions 8 are implanted over the entire surface, and then the photoresist 7 is removed. As shown in (C), the area other than the area that will become an n-channel MO transistor in the future is covered with photoresist 9.
After covering the entire surface with phosphorus (P) ions 10 and implanting them, the photoresist 9 is removed. As shown in (d), the ion-implanted phosphorus and boron are activated by annealing in an electric furnace at a temperature of 600° C. or higher, and the source region 11, drain region 12, which is a low-resistance n-type silicon layer, and Source region 1 which is a low resistance n-type silicon layer
3. Form the drain region 14.

Furthermore, as shown in (e), silicon dioxide [1
Aluminum (AI) A:
The extraction electrode 16 is formed at this point. Then, a heat treatment of about 400° C. is performed to complete the basic process of manufacturing a CMOS (CMOS) transistor on an insulator. In addition, n channel M
(2) to the polycrystalline silicon films 2 and 3 in order to control the threshold voltage Vth of the OS) transistor and the p-channel MOS transistor. In some cases, impurity elements are added for control purposes.

[Problems to be Solved by the Invention] However, in the conventional manufacturing method described above, in order to form a low-resistance n-type and n-type silicon layer, it is necessary to use an n-type impurity element such as phosphorus and a p-type impurity element such as boron. After ion implantation, electric furnace annealing at 600° C. or higher is required to activate the implanted impurity elements. For this reason, the insulators that can be used are limited to silicon dioxide films formed by thermally oxidizing the surface of single crystal silicon, or insulating materials with high softening points such as quartz glass.Insulators such as soda lime glass, which is an inexpensive insulator, are The present invention was made to solve the above problems, and it is possible to activate the n-type impurity element and the p-type impurity element in the semiconductor layer at a lower temperature than before to create a low-resistance semiconductor layer. An object of the present invention is to provide a method for manufacturing a CMOS transistor that can obtain the following characteristics.

[Means for Solving the Problem] The method for manufacturing a CMOS transistor according to claim (1) is a method for manufacturing a complementary MO8 transistor using a semiconductor film formed on an insulator, which includes an impurity element. 1st
The method for manufacturing a CMOS transistor according to claim (2), characterized in that the semiconductor layer of the conductive type and the semiconductor layer of the second conductive type are made to have low resistance by ion implantation simultaneously or separately. The method of manufacturing a CMOS transistor according to claim (3), characterized in that the addition is carried out by the ion implantation method, characterized by heating the substrate at a temperature below the softening point of the insulator during the ion implantation. shall be.

In the present invention, an ion implantation method is used to activate the n-type impurity element and the p-type impurity element in the semiconductor film at a lower temperature than before to obtain a low-resistance semiconductor layer.

The ion species to be implanted are preferably constituent elements of the semiconductor film or elements that do not have an adverse effect on the semiconductor film. For silicon semiconductor films, rare gases can be exemplified in addition to silicon, and for compound semiconductors, constituent elements (for example, GaAs semiconductors include Ga and As), rare gases can be exemplified. For example, in a silicon semiconductor film, elements that react with silicon to form compounds, such as oxygen and nitrogen, and
Elements that deteriorate the characteristics of the silicon semiconductor film, such as heavy metal elements, are not preferred.

In addition, the acceleration energy and implantation amount of ions can be adjusted as necessary depending on the desired implantation depth, MW of the semiconductor layer, etc., but usually each acceleration energy is 1 keV to 5 keV.
MeV, injection 111X1014 ~ lX101' pieces/
cm2 is preferred. Here, it is preferable to set the depth of ion implantation so that the ions are implanted at a position deeper than the semiconductor film, but it is also possible to reduce the depth of ion implantation and implant ions only into the surface layer of the semiconductor layer. The effects of the present invention appear up to the depth at which ions are implanted. In addition, it is preferable to implant ions until the impurity element is activated and the semiconductor film is reduced in resistance to the desired resistance at.If the amount is less than this, the activation of the impurity element is insufficient. It is difficult to see the effects of the invention.

In the above, it has been explained that a low-resistance semiconductor film is formed by activating impurity elements contained in a semiconductor layer in advance by ion implantation, but nIJl or p! [! The impurity element may be added and activated by ion implantation alone. For example, a low-resistance n-type silicon layer or 2g12972 layer may be formed by ion-implanting phosphorus or boron into a non-doped silicon semiconductor film and only by implanting ions.

Furthermore, during ion implantation, the substrate may be heated at a temperature below the softening point of the insulator serving as the substrate.

As the insulator used in the present invention, in addition to the conventionally used silicon dioxide film formed by thermally oxidizing the surface of single crystal silicon and quartz glass, any insulator can be used. In particular, soda Since lime glass is inexpensive, it is also preferable as a side dish.

[Function] The present invention explains why when manufacturing a semiconductor device on an insulator using a conventional manufacturing method, an insulator with a high softening point is used and an insulator with a low softening point such as glass is not used. However, the temperature when activating the n-type and p-type impurity elements in the semiconductor is 6
This was done in view of the fact that the temperature is higher than 00℃, and according to the present invention, the n-type and p-type impurity elements are activated by ion implantation, so the n-type impurity element can be activated without using heat treatment.
! ! ! and a p-type semiconductor layer can be formed.

[Example] The present invention will be described in more detail with reference to Examples below.

Embodiment 1 FIG. 1 is a sectional view showing a method of manufacturing an 0MO8 transistor according to Embodiment 1 of the present invention.

As shown in (a), 1100 nm of an amorphous silicon film, which will become a semiconductor film, is deposited by sputtering or the like on an insulator 17 in which a 1 μm thick silicon dioxide film is deposited on the surface of soda lime glass containing 13% Na2O. , 10 μA/cm with an acceleration energy of 100 keV on the entire surface of silicon ions.
The amorphous silicon film is polycrystallized by implanting lXl017/cm2 ions at a beam current density of 2, and then polycrystalline silicon M2 and M3 are deposited in the regions that will become n- and p-channel MOS transistors in the future using photolithography. After forming a pattern, a silicon dioxide film 4 of 1100 nm, which will become a gate insulating layer, is deposited by CVD or the like at a substrate heating temperature of 400°C.
Furthermore, after depositing an n-type amorphous silicon film containing 1% phosphorus to a thickness of 300 nm by sputtering or the like, photolithography is used to deposit the n-type amorphous silicon film 18, which will become a gate region in the future.
and 19 patterns were formed. As shown in (b), the area other than the area that will become a p-channel MOS transistor in the future is covered with a 1 μm thick photoresist, and boron ions 8 are applied to the entire surface with an acceleration energy of 40 keV at lX101.
After ion implantation, the photoresist 7 is removed. With this acceleration energy, boron ions 8 are implanted into the polycrystalline silicon M3 through the silicon dioxide film 4. At the same time, the boron ions 8 are implanted into the polycrystalline silicon M3 through the silicon dioxide film 4. Silicon film 19
Boron ions 8 are also implanted into the silicon dioxide film 4 and the polycrystalline silicon M3 immediately below the n-type pressed crystalline silicon film 18. As shown in (C), the area other than the area that will become an n-channel MO8) transistor in the future is covered with a photoresist 9, and phosphorus ions 10 are applied to the entire surface with an acceleration energy of 130 keV at 5 x 10''/a.
After m2 ion implantation, the photoresist 8 is removed.

At this acceleration energy, phosphorus ions 10 are implanted into polycrystalline silicon M2 through silicon dioxide H4. At the same time, phosphorus ions 10 are implanted into the n-type pressed crystalline silicon film 18, but the n-type pressed crystalline silicon y41
Ions are not implanted into the silicon dioxide film 4 and the polycrystalline silicon film 2 immediately below the silicon dioxide film 8. As shown in (d), silicon ions 20 are applied to the entire surface in order to activate the phosphorus and boron ion-implanted into the polycrystalline silicon WX2 and WX3 and the phosphorus contained in the n-type pressed crystalline silicon film 18 and 19. IX 1017/cm2 ions were implanted with an acceleration energy of 180 keV and a beam current density of 5 μA/cm2. By this ion implantation of silicon ions 20,
Polycrystalline silicon film 2 implanted with phosphorus ions 10
The sheet resistance of the polycrystalline silicon film 3 decreased from 10'Ω/hole to 1000/hole, and the sheet resistance of the polycrystalline silicon film 3 implanted with boron ions 8 also decreased from 107Ω/hole to 300Ω/hole, making it a low-resistance film. Source region 1 which is an n-type silicon layer
1. A drain region 12, a source region 13, and a drain region 14, which are low-resistance p-type silicon layers, were formed.

Further, the sheet resistance of n-type amorphous silicon 2M18 and 19 was also reduced from 10,707 to 50Ω/hole, and gate regions 5 and 6 could be formed. Furthermore, as shown in (e), silicon dioxide [15] was applied to the entire surface at a substrate heating temperature of 400°C.
Deposited to 300 nm using CVD method, etc., to form an n-channel MOS
) Source region 11, drain region 12 and p-channel MOS of transistor After contact holes were formed on source region 13 and drain region 14 of transistor, lead electrode 16 was formed using aluminum. and 400
CMOS on the insulator 17 after heat treatment at about °C.
) completed the manufacture of transistors.

After that, we measured the electrical characteristics of the CMOS transistor and found that the CMOS transistor on the soda lime glass described in this example
The OS transistor had the same characteristics as a 6MO5) transistor manufactured by a conventional method on quartz glass by heat treatment at 800°C.

Embodiment 2 In this embodiment, an enhancement MO8) transistor will be described as an example of a CMOS transistor using n- and p-channel MOS transistors with controlled threshold voltages.

FIG. 2 is a sectional view showing a method of manufacturing a CMOS transistor according to a second embodiment of the present invention.

As shown in (a), 1100 nm of an amorphous silicon film, which will become a semiconductor film, is deposited by sputtering or the like on an insulator 17 in which a 1 μm thick silicon dioxide film is deposited on the surface of soda lime glass containing 13% Na2O. Using photolithography, patterns of amorphous silicon 1I21 and 22 are formed in regions that will become n- and p-channel MOS transistors in the future.

As shown in (b), after covering the area other than the area that will become the future n-channel MO8) transistor with a photoresist 23 with a film thickness of 1 μm, boron ions 24 are applied to the entire surface at 10 keV to control the threshold voltage of the n-channel MO8) transistor. After implanting IXI□ts/cm2 ions with acceleration energy,
Photoresist 23 is removed. As shown in (C), after covering the area other than the area that will become the future p-channel MO8) transistor with a photoresist 25 with a film thickness of 1 μm, phosphorus ions 26 are accelerated to 30 keV over the entire surface to control the threshold voltage of the p-channel MO8) transistor. Energy is lXl0”
After implanting ions/cm2, photoresist 2
Remove 5. As shown in (d), silicon ions 27 are deposited on the entire surface at 10μ with an acceleration energy of 100k eV.
1xtot' pieces/c at a beam current density of A/am2
m” ion implantation to form amorphous silicon wA21 and 2
Polycrystallization of 2 and activation of implanted boron and phosphorous are performed to form p-type and n all-polycrystalline silicon ions 29 with low impurity concentrations. After this, polycrystalline silicon wA28 and 29 were used as polycrystalline silicon films 2 and 3 of Example 1, and FIGS. 1('a) to (e) of Example 1 were used.
Similarly to the steps in Figure 2 (e) to (i), perform the steps in (l),
As shown in FIG. 2(i), manufacturing of a CMOS transistor using n- and p-channel enhancement MOS transistors was completed.

After that, when the electrical characteristics of the CMO8) transistor were measured, it was found that the CMO8) transistor on the soda lime glass described in this example
MOS transistors are made by forming low impurity concentration n-type and p-type polycrystalline silicon films for threshold voltage control on quartz glass by heat treatment at 800°C, and by forming n-type and p-type polycrystalline silicon films by heat treatment at 800°C. Characteristics equivalent to those of a CMOS transistor manufactured by using a low-resistance silicon layer were obtained.

In the embodiment of the present invention, the heating temperature of the substrate during ion implantation is 400° C. or lower, and the entire process can be performed at a temperature of 400° C. or lower.

Although the embodiments of the present invention have been described using a silicon semiconductor as the semiconductor film, it is obvious that the present invention can also be applied to compound semiconductors such as GaAs. Further, in this embodiment, a CMOS transistor has been described, but it is clear that the present invention can be used to manufacture transistors other than CMOS transistors, such as bipolar transistors, which have n- and p-type semiconductor layers.

[Effects of the Invention] According to the present invention, a crystalline semiconductor layer and low-resistance n-type and p-type semiconductor layers can be formed on an insulator by ion implantation. CMO8
) transistors can be manufactured.

[Brief explanation of drawings]

1 and 2 are cross-sectional views showing a method of manufacturing CMO8) transistors according to Examples 1# and 2 of the present invention, respectively, and FIG. 3 is a cross-sectional view showing a method of manufacturing a conventional CMO3) transistor. In the figure, 1 and 17 are insulators, 2 and 3 are polycrystalline silicon films, 4 and 15 are silicon dioxide films, 5 and 6
are gate regions, 7.9.23 and 25 are photoresists, 8 and 24 are boron ions, 10 and 26 are phosphorus ions, 11 and 12 are n-channel MO8) transistor source and drain regions, 13 and 14
are p-channel MO8) transistor source and drain regions, 16 is an extraction electrode, 18# and 19 are n-type amorphous silicon films, 20 and 27 are silicon ions,
21 and 22 are amorphous silicon films, 28 is a p-type polycrystalline silicon film with a low impurity concentration, and 2nd is an n-type polycrystalline silicon film with a low impurity concentration. Patent applicant: Nippon Sheet Glass Co., Ltd. @l1il TTTTTTTT~24 Figure 2

Claims (3)

[Claims] (1) Complementary MOS using a semiconductor film formed on an insulator
A method for manufacturing a CMOS transistor, characterized in that a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type containing an impurity element are made to have low resistance by ion implantation simultaneously or separately. Method. (2) The method for manufacturing a CMOS transistor according to claim 1, wherein the impurity element is added by the ion implantation method. (3) The method of manufacturing a CMOS transistor according to claim 1 or 2, wherein the substrate is heated at a temperature below the softening point of the insulator during the ion implantation.