JPH04175075A - video camera equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video camera device that can be used for home use, broadcasting, monitoring, and industrial use such as medical care and testing.

[Conventional technology]

Conventionally, the signal processing section of a video camera was an analog system, but in recent years, with the rapid spread of VH5 and 8mm VTRs for general users, development of compact, lightweight, and low-cost VTR-integrated video camera devices has progressed. It is being As a means to achieve these goals, digitization of signal processing units is progressing.

FIG. 2 is a block diagram showing the basic configuration of a video camera in which a conventional analog signal processing section is digitized.

In FIG. 2, when the sensor 1 receives the optical signal 11,
For each horizontal readout scanning period (hereinafter, one horizontal scanning period is abbreviated as IH), an analog pixel signal 12 consisting of alternately repeating different color signals is synchronized with a readout clock frequency (hereinafter referred to as sensor clock fs). Output. The operation of the sensor 1 is performed by a sensor drive timing generation circuit (hereinafter referred to as "sensor drive timing generation circuit").

(referred to as TG) 5. The analog pixel signal 12 is A/D converted by an analog/digital conversion circuit (hereinafter abbreviated as A/D) 2 to become a digital pixel signal 13. The digital signal processing circuit 3 receives a digital pixel signal 13 and a synchronization signal 20 from a synchronization signal generation circuit (hereinafter referred to as SSG) 8.
When supplied with the control signal 23 and the control signal 18, it generates a luminance signal 14 to which a synchronization signal is added and a color signal 15 to which a synchronization signal is added. These signals 14 and 15 are D/A converted by a digital/analog conversion circuit (hereinafter abbreviated as D/A) 4, and are converted into an analog luminance signal 16 to which a synchronizing signal is added, and an analog luminance signal to which a synchronizing signal is added. The color signal becomes 17.

Below, control signals 18 and 5SG generated in TG5
The synchronization signal 20 and control signal 23 generated at 8 will be explained. First, 5SG6 has an oscillation frequency of nfs
When a signal of frequency nfsc is supplied as a clock from the oscillator 61 of c (n is an integer, fsc is the frequency of the color subcarrier), in order to generate a signal for sensor driving,
A chestnut horizontal synchronization signal (hereinafter referred to as CHD) and a vertical synchronization signal (hereinafter referred to as VD) are generated, and these two signals 19 are supplied to the TG5. The TG5 generates a sensor clock fs from the signal supplied from the oscillator 51 and the CHD. On the other hand, 5SG8 uses nfsc as a clock to generate synchronization signals 20 such as a composite sync signal (hereinafter referred to as C3YNC), a composite blanking signal (hereinafter referred to as CBLK), and a burst flag signal (hereinafter referred to as BF). occurs. And the digital signal processing circuit 3 is
A brightness signal and a color difference signal are generated using the sensor clock fs as a clock, a synchronization signal 20 is added to these two signals, a brightness signal 14 is output, and the color difference signal is further modulated by a control signal 23 to output one color signal 15. do.

Note that related devices of this type include, for example, Japanese Patent Publication No. 63-45153.

[Problems to be Solved by the Invention] In the above conventional technology, when converting the signal processing section of a video camera device from an analog system to a digital system, the luminance signal is synchronized with the sensor clock fs, and the synchronization signal such as C3YNC is synchronized with the nfsc. Despite being synchronized, no consideration was given to synchronizing the luminance signal and the synchronization signal when adding the synchronization signal to the luminance signal. FIG. 3 is a timing chart of C3YNC before being added to the sensor clock fs and the luminance signal, and C3YNC after being added. In FIG. 3, the rise IOA of the sensor clock 101 and C3Y
If the falling edge 106 of NC102 is the same, in some cases, C3YNC102 is latched at the rising edge 104, and even after being added to the luminance signal, it becomes a signal similar to C3YNC102, but it is not latched at the rising edge 104 and the rising edge 105 If latched with
3YNC becomes signal 103. In this case, C3YNC1
The difference in the falling timing of 02 and 5YNC103 is 1/fs.1 For example, if the number of pixels in the H direction of the sensor is 550, press 1/fs and IH1550 = 115ns.
It is. If this is the case.

Jitter occurs in the output image that can be detected by human vision.

Furthermore, in the past, since the horizontal readout clock frequency of the sensor was fixed, it was not possible to support sensors with a different clock frequency, resulting in a lack of versatility.

An object of the present invention is to provide a digital signal processing circuit that does not generate jitter in an output image, and further provides a programmable S
An object of the present invention is to provide a video camera device which can accommodate sensors of various specifications by providing an SG and controlling it by a microcomputer, thereby making the timing of a synchronizing signal variable.

[Means to solve the problem]

The first means employs the first or second means below as a means for preventing the jitter, and the third means is adopted as a means for making multi-sensor compatible.
A synchronization signal consisting of an nfsc section that generates a horizontal synchronization signal and a vertical synchronization signal for the camera using the SC signal as a clock, and an fs section that generates a synchronization signal for the television using the sensor clock fs generated by the TG as a clock. It is equipped with a generation circuit.

Further, the second means includes a signal switching circuit that alternately supplies a luminance signal and a television synchronization signal to the D/A, and a clock having a frequency of nfsc and a sensor clock fs as clocks of the D/A. This configuration includes a clock switching circuit that alternately supplies clocks.

Next, the third means depends on the sensor clock fs,
A programmable SSG that can change the timing of the television synchronization signal generated in the fs section in order to be compatible with various sensors without having to
The configuration includes a microcomputer that controls this.

[Operation] In the first means, when a clock of frequency nfsc is supplied, the nfsc section performs timing generation processing using a counter or the like, and generates a horizontal synchronization signal (CHD) and a vertical synchronization signal (VD) for the camera. and supplies these two signals to the TG. The TG generates a sensor clock fs using a signal synchronized with the CHD, and supplies several types of control signals such as the sensor clock fs to the digital signal processing circuit and the fs section in the SSG. The digital signal processing circuit performs signal processing using the sensor clock fs as a clock, and generates a luminance signal and a color difference signal. On the other hand, the fs section also uses the sensor clock fs as a clock to generate a synchronization signal such as a composite sync signal for television. Therefore, since the brightness signal and the synchronization signal are synchronized with the sensor clock fg, the brightness signal and the synchronization signal are synchronized. Therefore, in the digital signal processing circuit, when a synchronization signal is added to a luminance signal, a large timing difference does not occur, so no jitter occurs.

In the second means, the signal switching circuit is switched to the synchronizing signal side at a point in time (point A) when the luminance signal level is constant during the horizontal retrace period and before entering the horizontal blanking period, and the clock switching circuit Switch to the nfsc side (input the synchronization signal).

The nfsc is supplied as a clock to the D/A conversion circuit.

Next to the analog signal, the synchronizing signal is also output during the horizontal retrace period. ) At a point in time (point B) when the luminance signal level is constant after coming out of the horizontal blanking period, connect the signal switching circuit and clock switching circuit to the opposite side, and output an analog luminance signal through the same processing as above. let Therefore, at the points A and B, even if the luminance signal and the synchronization signal are not synchronized, no jitter occurs because the luminance signal level is constant.

Next, in the third means, timing data is sent from the microcomputer and control signals such as sensor clock fs are sent from the TG.
n When the vertical synchronization signal is supplied from the fsc section, the fs section causes the state holding circuit to hold the timing data.
A horizontal synchronization signal is generated by processing the value of the counter clocked by the sensor clock fs and the timing data held in the state holding circuit, and the horizontal synchronization signal and nf are processed.
By synthesizing the vertical synchronizing signals supplied from the sc section, a synchronizing signal is generated.
If the timing data supplied to the s section is made to match the specifications of the sensor in use, a synchronization signal applied to that sensor can be generated, making multi-sensor support possible.

〔Example〕

A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the basic configuration of a video camera device according to a first embodiment. This is the sensor l and the anal opening.
digital/digital conversion circuit (A/D) 2, digital signal processing port J13, digital/analog conversion circuit (D
/A) 4 and sensor drive timing generation circuit (TG) 5
, an oscillation circuit 51 , a synchronization signal generation circuit (SSG) 6 , and an oscillation circuit 61 .

The operation of the video camera device having the above configuration will be explained below. When the sensor 1 receives the optical signal 11, it outputs an analog pixel signal 12 consisting of repeating alternately different color signals in synchronization with a sensor clock having a frequency fs every horizontal scanning period (IH).

The operation of the sensor 1 is controlled by a control signal 18 from the TG5. When supplied with an analog pixel signal 12 from the sensor 1, the A/D 2 converts the analog pixel signal 12 into a digital pixel signal 13, and supplies the digital pixel signal 13 to the digital signal processing circuit 3. A/
Digital pixel signal 13 from D2 and control signal 18 from TG5.

When supplied with the synchronization signal 2o and the control signal 23 from the 5SG6, the digital signal processing circuit 3 converts the luminance signal 14 to which the synchronization signal has been added and the color signal 15 to which the synchronization signal has been added.
These two signals 14 and 15 are supplied to the D/A 4. A luminance signal 14 to which a synchronization signal is added from the digital signal processing circuit 3, and a color signal 15 to which a synchronization signal is added.
, the D/A4 outputs those two signals 14 and 15.
is converted into an analog signal, and a luminance signal 16 to which an analog synchronization signal is added and a color signal to which an analog synchronization signal is added are output. Note that the 5SG6 generates the synchronization signal 20 from the control signal 18 supplied from the TG5. Also,
TG5 generates control signal 18 from synchronization signal 19 supplied from 5SG6 and reference signal 50 supplied from oscillation circuit 51.

FIG. 4 is a block diagram showing the configuration of 5SG6 in more detail. In FIG. 4, the 5SG6 consists of an nfsc section 62 and an fs section 63, and the nfsc section 62 further includes a horizontal synchronizing signal generation circuit 621 and a vertical synchronization signal generation circuit 6.
22, and the fs section is a horizontal synchronizing signal generating circuit 63.
3 and a synchronization signal generation circuit 635. Below, 5SG
The operation of No. 6 will be explained.

First, in the nfsc section 62 , when the signal 60 of the frequency nfsc is supplied from the oscillation circuit 61 , the horizontal synchronization signal generation circuit 621 generates the horizontal synchronization signal 623 and supplies these to the vertical synchronization signal generation circuit 622 . When the horizontal synchronization signal 623 is supplied from the horizontal synchronization signal generation port N621, the vertical synchronization signal generation circuit 622 generates the vertical synchronization signal 625, and these signals are sent to the synchronization signal generation circuit 63 in the fs section.
Supply to 5. In addition, the n fsc section receives the horizontal synchronization signal 62.
3, a signal (CHD) 624 necessary to generate a signal to horizontally drive sensor 1, and a vertical synchronization signal 625
Of these, the signal (VD) 625 necessary to generate the signal for vertically driving the sensor 1 is used as the control signal 19 in the TG5.
supply to When the control signal 19 is supplied from the 5SG6, the TG5 outputs the reference signal 50 supplied from the oscillation circuit 51.
The frequency-divided signal and the CHD are phase-locked, and a control signal 18 such as a sensor clock having a frequency fs is generated from the reference signal 50, and the control signal 18 is supplied to the fs section 63 of the 5SG6. When supplied with the control signal 18, the horizontal synchronization signal generation circuit 633 generates a horizontal synchronization signal 638 synchronized with the sensor clock fs, and supplies the horizontal synchronization signal 638 to the synchronization signal generation circuit 635. When the vertical synchronization signal 625 is supplied from the vertical synchronization signal generation circuit 622 and the horizontal synchronization signal 638 is supplied from the horizontal synchronization signal generation circuit 633,
The synchronization signal generation circuit 635 generates the synchronization signal 20 (C5YNC
, CBLK, BF) and supplies the synchronizing signal 20 to the digital signal processing circuit 3. Here, the horizontal synchronization signal 638 and the vertical synchronization signal 625 are the sensor clock fs
Since it is synchronized with the sensor clock f, the synchronization signal 20 is also synchronized with the sensor clock f.
This means that it is synchronized with s.

FIG. 5 is a block diagram showing the configuration of the digital signal processing circuit 3 in more detail. In FIG. 5, the digital signal processing circuit 3 includes a Y/C separation circuit 31, a Y process circuit 32, a C process circuit 33, a C3YNC addition circuit 34, a BF addition circuit 35, and a modulation circuit 36. The operation of the digital signal processing circuit 3 will be explained below.

When the digital pixel signal 13 is supplied from the A/D 2,
The Y/C separation circuit 31 generates a first pixel signal 301 and a second pixel signal 302, and supplies these two signals to a Y process circuit 32 and a C process circuit 33, respectively. Y/
When supplied with the first pixel signal 301 and the second pixel signal 302 from the C separation circuit N31, the Y process circuit 32 generates a luminance signal 303 and supplies it to the C3YNC addition circuit 34. Further, when the first pixel signal 301 and the second pixel signal 302 are supplied from the Y/C separation circuit 31, the C process circuit 33 generates a color difference signal 304, and sends this to the BF.
It is supplied to the additional time JI135.

Note that the Y/C separation circuit 31. Y process circuit 32 and C
The process circuit 33 receives a control signal 18 from the TG5.
and is synchronized with the sensor clock fs. Therefore, the luminance signal 303 and the color difference signal 304 are also each synchronized with the sensor clock fs. The synchronization signal 20 supplied from C3Y
NC305, CBLK306, and BF307(7)3
Consists of signals. Luminance signal 303 from Y process circuit 32
but.

When C3YNC 305 and CBLK 306 are supplied from 5SG6, C3YNC addition circuit 34 generates luminance signal 14 to which a synchronization signal is added.

On the other hand, a color difference signal 304 is output from the C process circuit 33.

When the BF 305 and CBLK 306 are supplied from the 5SG 6, the BF addition circuit 35 generates a color difference signal 308 to which a synchronization signal has been added, and supplies this to the modulation circuit 36. B
Color difference signal 30 to which a synchronization signal is added from the F addition circuit 35
8, when the control signal 23 is supplied from the 5SG6, the modulation circuit 36 generates the color signal 15 to which a synchronization signal is added. The luminance signal 14 and chrominance signal 15 to which the synchronization signal has been added are converted into analog signals by the D/A 4 and become analog luminance signals 16 and chrominance signals 17.

From the above, according to this embodiment, the signal processing is controlled by the sensor clock, and the synchronization signal is also generated from the sensor clock, so the digital luminance signal and the synchronization signal are synchronized, so the two signals are synthesized. This has the effect of preventing jitter.

Next, a second embodiment of the present invention will be explained using the drawings.
The basic configuration of the video camera device of this embodiment is almost the same as that shown in FIG. 1, except that the 5SG6 in FIG. 1 is replaced with a programmable 5SG65, and a microcomma is provided to control it.

Figure 6 shows the programmable 5SG65 and the microcomputer 7.
FIG. 2 is a block diagram more specifically showing the configuration of FIG. In FIG. 6, 5SG65 has an n fsc section 62 and an fs section 6.
The fs section 64 consists of a counter 631, a latch circuit 632, a horizontal synchronization signal generation circuit 634, and a synchronization signal generation circuit 635. However, the configuration and operation of the nfsc section 62 inter-section two signal generation circuit 635 are similar to those of the 5SG6.

FIG. 7 is a diagram showing an example of the configuration of each block in the fs section 64. In FIG. 7, the latch circuit 632 consists of a latch circuit 632a and a latch circuit 632b, and the horizontal synchronization signal generation circuit 634 consists of a comparison circuit 634a.
and a pulse generating circuit 634b.

Here, the signal 22 is timing data supplied from the microcomputer 7, and includes timing data 22a and address 2.
Consists of 2b. Moreover, the signal 639 and the signal 640 are the output signals of the comparison port J1634a, and the signal 638 is the horizontal synchronization signal. Further, FIG. 8 is a timing diagram in the process of generating the horizontal synchronization signal 638. The operations of the 5SG65 and the microcomputer 7 will be described below with reference to FIGS. 6, 7, and 8.

In FIG. 6, the microcomputer 7 supplies the latch circuit 632 with first timing data 22 for generating a synchronization signal adapted to the specifications of the sensor 1;
holds the timing data 22a. However, the seventh
v! Which of the latch circuits 632a and 632b in i is to hold the timing data 22a is determined by the address 22b. Here, as an example, it is assumed that the latch circuit 632a holds the value a, and the latch circuit 631b holds the value (a + b). When the control signal 18 is supplied from the TG 5, the counter 631 counts the sensor clock fs as a clock, and supplies the counter value 636 to the comparison circuit 634a in the horizontal synchronization signal generation circuit 634.

Timing data 637a and 63 from latch circuit 632
7b and the counter value 636 from the counter 631, the comparison circuit 634a checks whether the counter value 636 matches the timing data 637a or 637b, and if they do not match, outputs 1, and if they match, outputs 0. do. In other words, the comparator circuit 634a increases the signal 639 and signal 640 in FIG. Said signals 639 and 64
When supplied with 0, the pulse generation circuit 634b generates a horizontal synchronization signal 638 shown in FIG. 8, and supplies the horizontal synchronization signal 638 to the synchronization signal generation circuit 635. and,
The vertical synchronization signal 625 is output from the vertical synchronization signal generation circuit 622, and the horizontal synchronization signal 638 is output from the horizontal synchronization signal generation circuit 634.
When the synchronization signal generation circuit 635 is supplied with the synchronization signal C
3YNC, CBLK and BF are generated, and these three synchronizing signals 2o are supplied to the digital signal processing circuit 3. The subsequent operation is similar to that shown in the first embodiment.

As described above, in the second embodiment, the configuration of the fs section 64 is as follows.
Although only those shown in the figure are listed, in practice, the latch circuit 632 and the horizontal synchronization signal generation circuit 6 in FIG.
By providing a plurality of devices configured similarly to 34, a plurality of types of horizontal synchronization signals can be generated. Also, the circuit 632 is not limited to a latch circuit, but may be any circuit as long as it has the function of holding a state.

As described above, according to this embodiment, by providing a programmable SSG and a microcomputer to control it, the timing of the horizontal synchronization signal can be made variable, so a synchronization signal adapted to the specifications of the sensor used can be generated, and a multi It has the effect of being compatible with sensors.

Next, a third embodiment of the present invention will be described. The basic configuration of the video camera device of this embodiment is essentially the same as the configuration shown in FIG. 1, except for the parts shown in FIG. 9, and the operations of the respective blocks are also the same. In FIG. 9, the video camera device of this embodiment is provided with a programmable TG 9 and a microcomputer 7 for controlling the programmable TG 9. Timing data 22 from my comma, 5
When the synchronization signal 19 is supplied from the SG6, the programmable TG9 in the second embodiment
A method similar to that performed in the fs section 64 of the G65 is used to generate control signals with the required timing.

As described above, according to this embodiment, the sensor drive pulse and the control signal for signal processing can be changed in accordance with the sensor and system configuration.

Next, a fourth embodiment of the present invention will be described. FIG. 10 is a block diagram showing the basic configuration of the video camera device of this embodiment. This is sensor 1.

It consists of an A/D 2, a digital signal processing circuit 3, a D/A 4, a TG 52, a programmable 5S066, a control circuit 10, and a two-oscillation circuit 51.

The operation of the video camera device having the above configuration will be explained below. However, sensor 1. A/D2. Digital signal processing circuit 3. Since the operation of the D/A 4 is similar to that of the video camera device of the first embodiment, the operation of the circuits other than those described above will be particularly explained here. First, the oscillation circuit 51 supplies a reference signal of 5° to the TG 52. When the reference signal 50 is supplied from the oscillation circuit 51, the TG 52 outputs the reference signal 50.
By frequency dividing, a control signal 191 such as the sensor clock fs and a sensor drive signal 181 for driving the sensor 1 are generated, and each is sent to the programmable 5SG6.
6 and sensor 1. The programmable 5SG66 is equipped with a circuit similar to the fs section 64 in FIG.
, control signal 19 such as sensor clock fs from TG52
1, it generates a synchronization signal 20 synchronized with the sensor clock fs and a control signal 25 by the same operation as the fs section 64, and supplies them to the digital signal processing circuit 3 and the control circuit 10, respectively. Programmable 5SG6
6, the control circuit 10 supplies a control signal 26 such as a clock to the A/D 2, and supplies a control signal 27 such as a clock fs to the digital signal processing circuit 3.

Thereafter, the video camera device of this embodiment again operates in the same manner as the video camera device of the first embodiment, as described above, and outputs an analog luminance signal and color signal to which a synchronization signal has been added.

From the above, according to this embodiment, by providing the programmable 5SG6°6 which can generate synchronization signals with different timings depending on data supplied from the outside, it is possible to support multi-sensors.

Next, a fifth embodiment of the present invention will be described.The basic configuration of the video camera apparatus of this embodiment is the same as that shown in FIG. 10, in which a microcomputer 7 and an input terminal 71 for rewriting data are provided. In FIG. 10, the microcomputer 7 inputs data 72 from an input terminal 71, temporarily holds this data, and further transfers the data 72 to timing data 22.
The timing data held in the programmable 5SG 66 is rewritten. (However, the data 72 is not limited to the timing data 22, and furthermore, the microcomputer 7 is not limited to the above-mentioned operation, and can also control other circuits as necessary from the data 72.

In addition, as a sixth embodiment, as shown in FIG. 13, the data 72 is stored in the ROM 73 by having a configuration in which a ROM 73 is provided in FIG.
It can also be supplied to the microcomputer 7 from the OM73.

From the above, according to the fifth and sixth embodiments, the ROM that stores the microcomma and the data 72 to be supplied to the microcomputer 7
73 is provided, and the timing data 22 supplied to the programmable 5S066 and the programmable 5SG66 controlled by the microcomputer 7 can generate a synchronization signal 2o suitable for the sensor 1, which has the effect of supporting multi-sensors. Another advantage is that setup at the time of starting up the video camera device can be performed automatically.

Further, as a seventh embodiment, the configuration shown in FIG. 13 is changed to the configuration shown in FIG. 14, and data 72 is stored in the ROM 73.
Even if similar data is stored and the timing data 22, which is a part of the data stored in the ROM 73, is directly supplied to the programmable 66, the fifth and sixth
The same effects as in the embodiment can be obtained.

Next, an eighth embodiment of the present invention will be described using the drawings.

The basic configuration of the video camera device of this embodiment is almost the same as that shown in FIG. 10, but differs in the points shown in FIG. 15. 1st
In Figure 5, the microcomputer 70 stores several types of timing data for each system, and has a programmable RO.
Codes and control data assigned to each system are stored in M74. The input terminal 76 also supplies system selection data 78 to the microcomputer 70 from the outside. When the microcomputer 7o is supplied with the system selection data 78, it reads the selection data 78 from the programmable ROM 74.
The system data 77 consisting of the code and control data specified by is read out, and the timing data 22 specified by the code from among various timing data stored in the microcomputer 70 is supplied to the programmable 5SG 66, and the control data is The signal is supplied to the control circuit 10. Other operations are similar to those of the video camera device of the fourth embodiment.

From the above, according to this embodiment, the system selection data 78
By simply supplying the video camera from the input terminal 76, the video camera device can be automatically set to a state where it can operate normally.
This has the effect of increasing work efficiency in the manufacturing process.

Next, an eighth embodiment of the present invention will be described using the drawings.

The basic configuration of the video camera device of this embodiment is almost the same as that shown in FIG. 2, and the digital signal processing circuit is the same as that shown in FIG. 5, but the luminance signal processing section in a portion 37 surrounded by a dotted line is different. FIG. 11 is a diagram showing a D/A converter for a luminance signal and a synchronization signal in a video camera device according to a sixth embodiment. The D/A converter includes a signal switch 371 and a clock switch 372. (Furthermore, FIG. 12 is a diagram showing a luminance signal to which a synchronization signal has been added.) The basic operation of the video camera device of this embodiment is the conventional one shown in FIG. Since the operation is almost the same as that of the video camera device, only the operation of the D/A converter will be described below.

First, in the section A-B in Fig. 12, the signal switch 3
71 connects the terminal 374 and the terminal 375, and sends the synchronization signal 2o
is supplied to D/A4, and the clock switch 372 is connected to terminal 3.
77 and a terminal 378 are connected, and a clock of frequency n fsc is supplied to the clock 24 of the D/A 4. At this time, D
/A4 is the synchronization signal 2 using the nfsc clock as the clock.
Converts 0 to an analog signal and outputs it. Next, at time B in FIG. 12, the signal switch 371 switches to terminal 3.
73 and supplies the luminance data 303 to the D/A 4, and the clock switch 372 switches to the terminal 376 and supplies the sensor clock of frequency fs, which is one of the control signals 18, to the clock 24 of the D/A 4. do. At this time, the D/A 4 converts the luminance signal 303 into an analog signal using the sensor clock fs as a clock and outputs the analog signal. This operation continues in the B-A' interval until the next time A', at which time the signal switch 371 and the clock switch 372 are connected to opposite terminals, and the A-B interval is connected. A similar operation is performed, and the above operation is repeated thereafter. In Fig. 12, sections C, D, and C' include switch switching points A, B, A', and B'.
, D' all have a constant luminance signal level.

From the above, according to this embodiment, the luminance signal and the synchronization signal D
/A conversion is performed when the level of the luminance signal is constant on both sides of the horizontal blanking period, so even if the luminance signal and synchronization signal are not synchronized, the output will not be affected and jitter will occur. do not.

As mentioned above, the first to sixth embodiments are not limited to the NTSC system.
The effect can be realized in all color television systems such as PAL system and SECAM system, and the timing diagram is not limited to what is described.

〔Effect of the invention〕

According to the present invention, the synchronization signal generation circuit is configured so that the synchronization signal generation circuit is
(K is a number that depends on the color television) A section that generates a horizontal synchronization signal and a vertical synchronization signal using a signal with double the frequency as a clock, and a section that uses the horizontal readout clock of the sensor as a clock and adds it to the luminance signal and color difference signal. The luminance signal and the synchronization signal can be synchronized by having a configuration consisting of a section that generates a synchronization signal, and by using a configuration in which the luminance signal before adding the synchronization signal is generated using the horizontal readout clock of the sensor as a clock. Therefore, it is possible to prevent jitter caused by digitizing signal processing, and the effect of higher image quality can be obtained.

Further, by providing a circuit that switches the D/A conversion of the luminance signal and the synchronization signal when the luminance level on either side of the horizontal blanking period is constant, an image without jitter can be obtained.

Furthermore, by providing a programmable synchronization signal generation circuit, a sensor drive timing generation circuit, and a microcomputer to control these, multi-sensor support becomes possible.
This has the effect of increasing versatility and lowering the price.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of a first embodiment of a video camera device according to the present invention, FIG. 2 is a block diagram showing the basic configuration of a conventional video camera device, and FIG. 3 is a block diagram showing the basic configuration of a conventional video camera device. Sync signal timing diagram,
Part 4 is a block diagram showing the basic configuration of the synchronizing signal generation circuit in Figure 1, Figure 5 is a block diagram showing the basic configuration of the digital signal processing circuit in Figure 1, and Figure 6 is a block diagram showing the basic configuration of the digital signal processing circuit in Figure 1.
FIG. 7 is a block diagram showing an example of the fs section in FIG. 6, FIG. 8 is a timing diagram of the programmable synchronization signal generation circuit, and FIG. FIG. 10 is a block diagram showing the basic configuration of the fourth embodiment; FIG. 11 is a block diagram showing the basic configuration of the embodiment shown in FIG. 8; FIG. 13 is a diagram showing a luminance signal to which a synchronization signal is added, and FIGS. It is a block diagram showing i in the basic configuration ♂ of the sixth and seventh embodiments. 1...Sensor, 2...A/D conversion circuit. 3...Digital signal processing circuit. 4...D/A conversion circuit. 5.52...Sensor drive timing generation circuit. 6...Synchronization signal generation circuit. 65.66...Programmable synchronization signal generation circuit. 7.70...Microcomputer. 8...Synchronization signal generation circuit. 9...Programmable sensor drive timing generation circuit. 10... Control circuit, 51.61... Oscillation circuit. 621.623...Horizontal synchronization signal generation circuit. 622...Vertical synchronization signal generation circuit. 631...Counter, 632...Memory. 634...Pulse generation circuit. 635...Synchronization signal generation circuit. 31...Y/C separation circuit, 32...Y process circuit. 33...C process circuit. 34...Composite sync signal addition circuit. 35...Burst flag signal addition circuit. 36...Modulation circuit. 632a, b...Latch circuit. 634a... Comparison circuit. 634b...Horizontal synchronization signal generation circuit. 371...Signal switch. 372...Clock switch. 73...ROM. 74...Programmable ROM. 1st ff1la'& Ida 17 11min mK rw spear 2 countries conventional pig - 3 basic composition closing 3rd request〉 Sacrotsuku and tricks゛Sotosinfu's Fimi〉g 50%t award given 9. Synchronous signal generation circuit L ----
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Claims (1)

[Claims] 1. In a video camera device using a solid-state imaging device (1) and in which signal processing is digitalized, inputting a first clock whose frequency depends on the color television system used, The first one generates the horizontal synchronization signal and vertical synchronization signal.
a synchronization signal generating section (62); generating a synchronization signal by inputting a second clock synchronized with the horizontal readout clock of the solid-state imaging device (1) synchronized with the signal phase-locked to the horizontal synchronization signal; A video camera device comprising: a second synchronization signal generation section (63); and a synchronization signal generation circuit (6) comprising: a second synchronization signal generation section (63); 2. In a video camera device that uses a solid-state imaging device (1) and has digitalized signal processing, a first synchronization system that generates a horizontal synchronization signal and a vertical synchronization signal by inputting a first clock that uses a frequency. a signal generator (62); a counter (631) which receives as input a second clock synchronized with the horizontal readout clock of the solid-state imaging device (1) which is synchronized with a signal phase-locked to the horizontal synchronization signal; and a synchronization signal. a latch circuit (632) for holding timing data; and a pulse generation circuit (634) for generating a horizontal synchronization signal by comparing the value of the counter (631) with the timing data held in the latch circuit.
and a synchronization signal generation circuit that generates a synchronization signal by combining the vertical synchronization signal generated from the first synchronization signal generation section (62) and the horizontal synchronization signal generated from the pulse generation circuit (634). a second synchronization signal generation section (64) consisting of; and a programmable synchronization signal generation circuit (65) consisting of;
) and; further, a microcomputer (7) that controls rewriting of timing data held in the latch circuit (632).
A video camera device characterized by having; 3. According to claim 1, a programmable sensor drive timing generation circuit (9) that generates a control signal such as a drive pulse for the imaging device (1) and makes the control signal variable; Timing generation circuit (9
); and a microcomputer (7) for controlling the timing of the control signal generated by the video camera apparatus. 4. In a video camera device that uses a solid-state imaging device (1) and has digital signal processing, generating a synchronization signal that is synchronized with the horizontal readout clock of the solid-state imaging device (1) and can be rewritten from the outside. A video camera device comprising: a programmable synchronization signal generation circuit (66). 5. In claim 4, a ROM (73) that stores data such as timing data.
and; an input terminal (72) for inputting data stored in the ROM (73); and an input terminal (72) for temporarily holding the data and transmitting timing data of the data to a programmable synchronization signal generation circuit (6).
6) A video camera device comprising: a microcomputer (7) for supplying power to the video camera; 6. The video camera device according to claim 4, further comprising a ROM (73) in which the timing data is stored and which supplies the timing data to the programmable synchronization signal generation circuit (66). 7. In claim 4, a microcomputer (70) stores timing data for several types of video camera systems in advance and supplies the timing data to the programmable synchronization signal generation circuit (66); a code assigned to each of the systems; and a programmable ROM (74) in which control data set for each system is stored; and data for selecting the code and control data supplied from the programmable ROM (74) to the microcomputer (70). , an input terminal (76) for supplying data to a microcomputer (70) from the outside; and a video camera device. 8. In a video camera device that uses a solid-state imaging device (1) and has digitalized signal processing, a D/A conversion circuit (4) that converts digital brightness signals, synchronization signals, etc. into analog; and a horizontal retrace period. and when the brightness level is constant before and after the horizontal blanking period, the brightness signal and the synchronization signal supplied to the D/A conversion circuit (4) are switched, and the selected signal is switched. a switching circuit (371) that supplies the D/A conversion circuit (4) as an input signal;
) and; the frequency is Kfsc (K: a number that depends on the color television system, for example, an integer such as K = 4 for the NTSC system,
fsc: color subcarrier frequency) and a clock whose frequency is equal to the horizontal readout clock of the solid-state imaging device (1), are switched at the same timing as the switching circuit (371), and the D/A conversion circuit ( 4) A switching circuit (372) for supplying a clock as a clock; and a video camera device.