JPH0417586B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for converting an analog image signal obtained by scanning and reading a document into a binary signal indicating white or black in a facsimile machine or the like.

BACKGROUND TECHNOLOGY In a facsimile transmission document, its image is read by a photoelectric conversion element such as a CCD.
It is output as an analog image signal whose level changes depending on the density of the image. This image signal is also compared with the slice level signal to be converted into a binary signal indicating white or black, which is further coded and sent over the line. The slice level signal is usually obtained by integrating the image signal as shown in Japanese Patent Application Laid-Open No. 149570/1982. When the image signal is VS shown in FIG. 1a, the slice level signal becomes Sx shown in x in the figure.

Problems to be Solved by the Invention In the conventional slice level signal Sx described above, a slope portion shown by y occurs in the signal waveform, so the binary signal sliced in this portion y is not faithful to the original image signal VS. , a white image part may be determined to be black, or a black part may be determined and output. It is an object of the present invention to solve these problems and provide a binarization method that can reliably detect changes in the level of an image signal.

Means for Solving the Problems The present invention divides an image signal into a plurality of blocks, integrates each block, and uses the integrated value in each block as a slice level.

Effect According to the present invention, the integration of the image signal is performed independently for each block, and each integrated value is used as the slice level of the block, so the slice level within each block is substantially constant. Since it does not have the above-mentioned slope portion accompanying the rise or fall of the level, changes in the level of the image signal can be detected reliably.

Embodiment FIG. 2 shows a circuit for implementing the present invention. An image signal outputted via a CCD and a sample-and-hold circuit (not shown) is amplified by an amplifier 1 and then supplied to a first comparator 2. Furthermore, before being introduced into the amplifier 1, the image signal is branched and guided to an integrator 3, further digitized by an AD converter 4, and supplied to a second comparator 5. A predetermined reference black level signal SG, which will be described later, is supplied to the other input terminal of the comparator 5, and the comparison output with the image signal VS is stored in the memory 6 for one line. Therefore, the image signal in the memory 6 is output with a delay of one line, and after being converted into analog by the DA converter 7,
The signal is input to the first comparator 2. If the output of amplifier 1 is the nth line image signal, DA converter 7
The output is a slice level signal corresponding to the image signal of the n-1th line, and the comparator 2 outputs the comparison output between the two as a binary signal indicating white or black.

FIG. 3 shows details of the integrator 3. 8 is an inverting amplifier circuit, 9 is a Miller integration circuit, and 10 is a level switching circuit. CS1 is the level release signal shown in Figure 1C, and one pulse (P1) is generated every time an oscillator (not shown) issues m clock pulses.
is emitted. CS2 is a level capture signal,
Immediately before the pulse (P1) is emitted, one pulse (P2) is emitted without temporally overlapping with the pulse (P1). When the pulse (P1) of the level release signal CS1 is issued, the switch (SW1) closes and the input of the integrating circuit 9 appears as it is as the output. Therefore, the output of the integrating circuit 9 drops to a predetermined level every time the pulse (P1) is emitted, and as shown in FIG.
becomes. Pulse of level acquisition signal CS2 (P2)
When is issued, the switch (SW2) of the level switching circuit 10 is closed and the output of the integrating circuit 9 is supplied to the AD converter 4. This output is maintained at a constant level by the capacitor C while the switch (SW2) is open, so that the output becomes the stepped slice level signal SL1 delayed by one block as shown in Figure 1e. . This signal SL1 is AD
After being imported into converter 4 and digitized,
In order to ensure that the black signal portion (bp) of the original image signal VS can be sliced, the comparator 5 compares it with the reference black level signal SG, and as shown in FIG. will be “bottomed up”. Memory 6 is a RAM or a shift register. When using the RAM, the read timing is set so that the output from the DA converter 7 is delayed by one line from the output from the amplifier 1. Generally, in an image, the correlation between adjacent pixels is extremely large, so that an image signal of one line and an image signal of an adjacent line exhibit almost the same waveform.
Therefore, comparator 2 actually receives the image signal of the nth line.
VS is compared with the slice level SL2 created from the image signal of the n-1th line, but there are almost no problems due to line differences, and comparator 2
outputs the binary signal BS shown in FIG. 1g.

FIG. 4 shows another embodiment of the invention, in which the same devices as in FIG. 2 are given the same reference numerals.
In this example, the output of the integrator 3 described above is directly input to the second comparator 5a, and is supplied to the first comparator 2 without going through the output memory of the comparator 5a. The output of the amplifier 1 is also supplied to a delay circuit 11, where it is delayed by the time interval t of one block and output. According to the device of this example, since the analog delay circuit 11 is used, the price is higher than that of the device of the first embodiment described above. Since the formed slice level can be simultaneously supplied to the comparator 2, there is an advantage that the above-mentioned problem due to the difference in lines does not occur.

According to the T.4 standard in G3 of CCITT,
The number of pixels per main scanning line of an A4 size document is
When we conducted an experiment using a manuscript that is considered to be a standard 1728-bit image, we found that a suitable slice level signal can be obtained when one block of the time interval t is set to have a pixel count of 32 bits. I can do it.

Effects of the Invention According to the present invention, a slice level that does not have an unclear waveform level can be formed, so an image signal can always be sliced at an appropriate level, and a binary signal that faithfully corresponds to level changes of an image signal can be generated. can be obtained.

[Brief explanation of drawings]

FIG. 1 is a graph showing the method of the present invention in comparison with a conventional method, FIG. 2 is a circuit diagram for implementing the present invention, and FIG. 3 is a circuit diagram showing details of an integrator.
FIG. 4 is a diagram showing another circuit for implementing the invention. VS...Picture signal, SL1, SL2...Slice level signal.

Claims (1)

[Claims] 1. In a method of converting an image signal whose level changes depending on the density of the image into a binary signal by comparing it with a slice level, each line of the image signal is divided into a plurality of blocks, and each line is integrated for each block. A method for binarizing an image signal, characterized by forming slice levels.