JPH04182858A - Shared memory management system - Google Patents

Abstract

PURPOSE:To prevent a decrease in performance by performing other processes by a processor in a queuing state until an accessor is permitted. CONSTITUTION:When addition to a queue area 62 ends, a processor 11 releases a memory bus 2 which is locked and makes a return. Thus, the processor 11 after the return can freely perform other processes thereafter. When there is a queue, queue operation is performed, a value for identifying a processor or task is taken out of the head of the queue area 62 to identify a processor 1n to be placed in operation, and an interruption is generated and sent to the processor 1n through a signal line 7 to inform the processor 1n that a shared memory 3 is released.

Description

[Detailed description of the invention] [Industrial application field]

This invention provides a shared memory management method that uses semaphore control to exclude references and updates to the shared data from other processors until the updating of shared data shared by multiple processors or tasks is completed. It is related to.

[Conventional technology]

FIG. 4 is a block diagram showing a conventional shared memory management method disclosed in, for example, Japanese Patent Laid-Open No. 62-200449. In the figure, 11 to 1□ are a plurality of processors, 2 is a memory bus to which each of these processors 11 to 17 is connected, and 3 is connected to this memory bus 2 and shared by each of the processors II to 1°. This is shared memory. 41-4
5I to 5 is shared data stored in this shared memory 3 and shared by each of the processors 11 to 17;
m is each shared data 41 to 4. This is a semaphore provided in correspondence with the shared data 41 to 41 for exclusively controlling access to the associated shared data 41 to 41. Next, the operation will be explained. Here, FIG. 5 is a transition diagram of the contents of the semaphore to explain its operation. Now, processor 1□ is using shared data 4□ in shared memory 3.
When attempting to update the shared data 41, the processor 1□ first reads the contents of the semaphore 5 to check the value of the semaphore 5 associated with the shared data 41. FIG. 5(a) shows the read contents of semaphore 5□. At this time, the semaphore 5. If bit D7, which is the exclusive control bit of
), the bit D7 is updated to "1", and the processor number of the processor 1□ is added to the bits DO to D6 as a value for identifying the processor or task, and written to the semaphore 5I. In this case, an instruction dedicated to semaphore operation (for example, a Test & Set instruction) possessed by the processor is used. The shaded portions in FIGS. 5(b) and 5(c) are values for identifying this processor or task. After writing the updated value shown in FIG. 5(C) to the semaphore 51, the processor 1□ starts accessing the shared data 41. When the access to the shared data 41 is completed, the processor 1□ returns the contents of the semaphore 5I to the one shown in FIG. 5(a) where the exclusive control bit D7 is 0''. If processor 17 attempts to access the shared data 3I that processor 1□ is accessing while □ has control of the semaphore,
Exclusive control is performed as follows. That is, processor 1. When l reads the contents of semaphore 5゜ and checks its exclusive control bit, its value has been updated to "1" by processor 1□, so reading and writing of this semaphore 51 continues until it is returned to "0". Continue the check operation. After the access to the shared data 41 by the processor 1□ is completed, the semaphore 5. When the exclusive control bit of processor 1.l becomes "0," processor 1.l acquires the semaphore control right in the same way as processor 1, and starts accessing shared data 4.

[Problem to be solved by the invention]

Since the conventional shared memory management system is configured as described above, one processor 1. In a situation where two or more processors 1□ to 17 attempt to access the shared memory 3 while processors 1 to 17 are accessing the shared memory 3, the processors 11 to IR that were accessing the shared memory 3 terminate the access. In this case, which of the plurality of processors II to 1.1 attempting to access the shared memory 3 is permitted to access the shared memory 3 depends solely on that processor II to 11.1. The operation timing of multiple processors 1. ~1o
waits for access to shared memory 3, memory bus 2
Not only do memory bus 2 become unnecessarily occupied due to frequent accesses to system performance, but also processors l+~1ゎ waiting to access shared memory 3 wait until they finish accessing shared memory 3. Other processing cannot be performed,
There were also problems such as a decrease in the processing performance of the processors l, to lw themselves. This invention was made to solve the above-mentioned problems, and it is possible to determine which processor will be granted access next among multiple processors waiting to access shared memory. The purpose of the present invention is to provide a shared memory management method that does not require frequent accesses and allows a waiting processor to execute other processing until access is granted.

[Means to solve the problem]

The shared memory management method according to the present invention adds a queue area to a semaphore to manage waiting for access to shared data, allows each processor to operate the semaphore in a bus-locked state, and shares data in a bus-locked state. A function that accesses data, performs a bus lock at the end of access to shared data, determines the next processor to access shared memory from the contents of the semaphore queue area, and interrupts the shared memory by interrupting that processor. It has a function to notify the release of.

[Effect]

Each processor in this invention operates the semaphore in a state where access to the shared memory from other processors is prohibited by the hash lock, and accesses the shared data with the bus lock released, and When access to the data is completed, the bus is locked again and the semaphore queue area is referenced, and if there is a processor or task waiting,
By determining which processor should access the shared memory next based on the contents of the queue area, and notifying that processor of the release of the shared memory using an interrupt,
It is possible to determine which processor will be granted access next among multiple processors waiting to access the shared memory, preventing frequent accesses to the memory bus, and waiting processors to perform other processes until access is granted. To realize a shared memory management method that can perform

【Example】

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1□ to 1. , is a processor, 2 is a memory bus, 3 is a shared memory, 41-4. is shared data,
The detailed explanation will be omitted since it is the same as or corresponds to the conventional part shown in FIG. 4 with the same symbol. In addition, 61 is shared data 4. ~4. ．． Exclusive control management area 62 corresponds to conventional semaphores 51 to 51 for exclusively controlling access to shared data 41 to 4□
This is a queue area that manages waiting for access to 61 to 6. are different from conventional semaphores 51 to 5. in that they also include this queue area 62. This is a different semaphore. 7
is each processor l, ~1. l is another processor 1□~1
．． , an interrupt signal line that notifies the , , of the occurrence of an interrupt; in this case, it is made up of multiple lines. Next, the operation will be explained. Here, FIG. 2 is a transition diagram of the contents of the semaphore to explain its operation, and the third
The figure is a flowchart showing the processing procedure. Now, if a certain processor, for example processor l, attempts to access the shared data 42 in the shared memory 3,
The processor 11 connects the memory bus 2 in step STI.
Apply hashlock to the other processors 1□ to 1. , access to the shared memory 3 is prohibited. next,
Shared data 4 to be accessed in step ST2
Exclusive control management area 6 of semaphore 6 □ associated with □
1 is read out, and the content of its exclusive control bit D7 is determined in step ST3. As a result, if the exclusive control bit D is "'0" as shown in FIG. In step ST4, to indicate that the shared data 42 is being accessed, the second
As shown in Figure (t), the exclusive control bit of the exclusive control management area 61 of the semaphore 62 is set to "1". Thereafter, the processor 1 releases the bus lock in step ST5, and further accesses the shared data 4□ in step ST6. On the other hand, as a result of the determination in step ST3, semaphore 6□
As shown in FIG. 2(t), the exclusive control bit of
``'', the processor 11 performs step 5T.
At step 12, it adds its own processor number and priority to the queue area 62 of semaphore 6□. At this time, the additional position is as shown in Fig. 2 (C) and (d).
The priorities are compared and determined according to the ranking. Note that as a method of adding to the queue area 62, a first-in, first-out method may be adopted in which the first one is given priority. In that case, writing the priority becomes unnecessary. When this addition to the queue area 62 is completed, the processor II releases the bus-locked memory bus 2 in step 5T13 and returns. The processor 11 that has returned in this manner can then freely execute other processing. When the access to the shared data 4□ ends in step ST6, the processor 1□ advances the process to step ST7 to pass-lock the memory bus 2 again. Thereafter, in step ST8, the queue area 62 of the semaphore 6□ of the shared data 4□ is referred to, and the presence or absence of a waiting processor or task is checked. As a result, if there is no meeting, the process goes to step 5T.
Proceed to step 14 and set the exclusive control management area 6 of the semaphore 6□.
The exclusive control bits D, , 1 are set to 0°' and the process returns. As a result, the semaphore 6□ returns to the state shown in FIG. 2(a), which indicates that the common data 4□ is not accessed. Furthermore, if there is a waiting, the process is passed to step ST9, where a queue operation is executed, and a value for identifying a processor or task, such as a processor number, is retrieved from the head of the queue area 62 of the semaphore 6□. The status of semaphore 6□ at this time is shown in FIGS. 2(d) and (e). Processor 1. is the processor to operate next based on the retrieved value, for example, processor 1. , and the =
Pig processor 1. . Generates an interrupt for. This interrupt is sent to the processor 1□ via the interrupt signal line 7, and indicates that the shared memory 3 has been released. Tell l. Thereafter, the processor 11 releases the hash lock of the memory bus 2 in step 5T11 and returns. on the other hand,
The processor 1n that has received the interrupt accesses the shared data 4□ and releases the semaphore by executing the processing from step ST6 onwards.

【Effect of the invention】

As described above, according to the present invention, a semaphore has a queue area that manages waiting for access to shared data, the semaphore is operated in a hashlocked state, and the shared data is accessed in a bus-locked state. When the access to the shared data is completed, the hashlock is performed again and the queue area of the semaphore is referenced. , based on the contents of the N area, determines which processor should access the shared memory next, and notifies that processor of the release of the shared memory using an interrupt, so the processor waits for access to the shared memory. It is possible to determine which of the multiple processors in the queue will be granted access next, and also prevents the memory bus from being occupied and prevents frequent accesses to the memory bus. Since the processor can perform other processing until access is granted, a shared memory management method that does not degrade system performance can be achieved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a shared memory management system according to an embodiment of the present invention, FIG. 2 is a transition diagram of semaphore contents to explain its operation, FIG. 3 is a flowchart showing the processing procedure, and FIG. FIG. 4 is a block diagram showing a conventional shared memory management system, and FIG. 5 is a transition diagram of semaphore contents to explain its operation. 1, ~1. ．． 2 is a processor, 2 is a memory bus, 3 is a shared memory, 41 to 4□ are shared data, 6I to 6 are semaphores, 61 is an exclusive control management area, 62 is a queue area, and 7 is an interrupt signal line. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. (2 other people) 2: Suribus 61...6m: T Maho at: 8M
e '1? It! 'II' f! W % < 62, Q Zeng I Wei 7, Animal 1, N signal line Fig. 6 Fig. 4

Claims (1)

[Claims] shared data shared by multiple processors or tasks;
and a shared memory management method in which a plurality of processors are connected via a memory bus to a shared memory storing a semaphore corresponding to the shared data, and access of each processor to the shared data is exclusively controlled by the semaphore. In the semaphore, the semaphore has an exclusive control management area for exclusive control of access to the shared data and a queue area for managing waiting for access to the shared data, and each processor The semaphore is operated in a state where access from other processors to the shared memory is prohibited, and the shared data is accessed with the bus lock released, and when the access to the shared data is completed, With the bus locked again, the queue area of the semaphore is referenced, and if there are any processors or tasks, the next processor to access the shared memory is determined based on the contents of the queue area. ,
A shared memory management method characterized by notifying the processor of the release of shared memory using an interrupt.