JPH04182989A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To improve the yield of nondefective articles by providing a fuse element between a power source wiring for memory cells and a main power source wiring and controlling a decoder circuit for word lines by the potential of the power source wiring for memory cells. CONSTITUTION:The fuse element F21 is inserted between the cell VCC line and the main VCC line. The fuse element in the X decoder corresponding to the defective word line is cut in this case. Namely, the potential of the cell VCC line is lowered down to the GND potential by a resistance element R12 when the fuse element F21 is cut and, therefore, the p channel transistor QP21 in the X decoder 101 turns on and the n channel transistor WN24 turns off. Consequently, a node 11 is fixed to the VCC potential at all times regardless of the level of the predecoder output and, therefore, the word lines WLi, WLi+1 are fixed to the GND potential at all times regardless of the levels of Ao', -Ao'. Since the main VCC line and the cell VCC line can be electrically separated by the cutting of the fuse element F21 in this way, the defective article can be converted to nondefective article current wise.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory that improves a method for relieving defects using a redundant circuit.

[Conventional technology]

With the increase in the capacity of semiconductor memories, semiconductor memories of 1 mechanical hint class or higher are now on the market, but in general, these large capacity memories are equipped with redundant circuits. We are aiming to improve the yield of good products.

An example of a semiconductor memory equipped with a conventional redundant circuit will be described with reference to the drawings. FIG. 8 shows a circuit diagram of a main part of a conventional example.

In FIG. 8, cell 102. X decoder 801. The circuits of the redundant word line driver 103 are shown in FIGS. 3 and 9, respectively.
As shown in FIG. As can be seen from FIG. 3, the unit memory cell of the semiconductor memory of this conventional example consists of four N-channel transistors QN: 1llQ N321 Q N31
1 Q N31 and two resistance elements R3,.

This is a flip-flop circuit composed of R3□, that is, a static RAM memory cell. Generally, in order to keep the power consumption sufficiently low, the resistive element R3,.

R3° is a very high resistance value, for example 1 teraohm (1
It is formed of non-doped polysilicon so as to have a resistance of about 0 to the 12th power ohm. The cell 102 has a plurality of word lines WLI, WL2゜...WL,...
...and multiple hit line pairs BL1/Hyakuryo =.

BL2・Hyakuryo],..., BL,・Hyakuryoko,...
・It is placed at the intersection of In the operating mode of the semiconductor memory, only one word line WL1 is at "H" level, and only one bit selection phase, the output Y of Y decoder 104, is at L level.
``level selects only one cell 102 and allows data to be input to or output from the cell.

The semiconductor memory of this conventional example includes a redundant word line driver 103 . Redundant word line SWL.

It is equipped with a group of 102 cells connected to 3 W L 2 and a redundant X-decoder (not shown in FIG. 8), and uses the redundant circuit to remove defective cells caused by dust, pattern distortion, etc. during the diffusion process. A defective product can be made into a good product by replacing it with a cell. This replacement work involves cutting the fuse elements in the redundant X-decoder and the X-decoder as appropriate, corresponding to the address position of the word line containing the defective cell (defective word line) detected during the wafer probing test after the diffusion process. It is executed by Generally, cutting is performed with a laser beam. here,
Only the fuse element of the X decoder driving the defective word line is cut off. When the fuse element Fil is cut as shown in FIG. 9, the node 81 becomes ■ due to the normally-on transistor Q p a a. o potential. Therefore, the defective word line WL,.

W L , + is the lowest input signal A of the address. ′,
and its complementary signal is always 'L' regardless of the level of 7.
” level. That is, the redundant word line 5WLI,
When 5WL2 becomes “H” level, the defective word line also becomes “H” level.
``This is done to prevent malfunctions due to multiple selections.

Incidentally, FIG. 5 shows an example of the layout of the memory cell. As shown in the figure, in order to achieve high density, cell V is generally used. The C line and the cell GND line are wired in layers using different polysilicon layers (or polycide layers, or silicide layers).

[Problem to be solved by the invention]

In this conventional semiconductor memory, when the polysilicon layer for cell VCC and the polysilicon layer for cell GND are short-circuited or conductive due to leakage due to dust etc. during the formation of the interlayer insulating film, the word line containing the defective part is There is a problem in that even if a redundant word line is replaced and the product becomes operationally good, it becomes a defective product because of the large power consumption current flowing between VCo and GND. In particular, this type of cell V is used for products that require a power supply current consumption standard of about 10 microamperes or less in standby mode. Short-circuit defects between the 0 line and the cell GND line have become a serious problem, and have caused a significant decrease in the yield of non-defective products.

[Means to solve the problem]

The semiconductor memory of the present invention is configured such that a fuse element is provided between the memory cell power supply wiring and the main power supply wiring, and the word line decoder circuit is controlled by the potential of the memory cell power supply wiring. Alternatively, in the above configuration, a resistance element of 1 gigahm or more is provided between the memory cell power supply wiring and the GND wiring. In other words, in the semiconductor memory of the present invention, a fuse element is provided between the gate electrode of the bit line load P-channel (N-channel) transistor and the GND wiring (power supply wiring), and the bit line decoder is controlled by the potential of the gate electrode. It is configured to control the circuit. Alternatively, in the above configuration, the gate electrode and the power supply wiring (GN
A resistance element of 1 gigaohm or more is provided between the wires (D wiring).

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of a main part of a semiconductor memory according to an embodiment of the present invention, and FIG. 2 is an X decoder 101 of the semiconductor memory according to this embodiment.
The circuit diagrams are shown respectively.

The semiconductor memory of this embodiment is a semiconductor memory in which the X decoder 801 in the conventional example described above is replaced with the X decoder 101. As shown in Figure 2, cell ■. 0 line and main V. A fuse element F21 is inserted between the 0 wires.

As in the conventional example described above, the fuse element in the X decoder corresponding to the defective word line is cut. When fuse element F21 is cut, cell V. 0 line is connected to GN by resistor element R21
Since the voltage is lowered to the D potential, the P channel transistors QP2 . is turned on, and N-channel transistor QN24 is turned off. As a result, node 11 is always ■, regardless of the level of the predecoder output. Since the potential is fixed at 0, the word lines WL, , WL, +.

is always GND regardless of the level of A o ', K7
fixed at potential. That is, the X-decoder of this embodiment, like the conventional X-decoder described above, can fix the word line to the GND potential by cutting the fuse element. Furthermore, in this embodiment, the main V is disconnected by cutting the fuse element F21. . Line and cell V. Since the 0 wire can be electrically isolated, the cell V. Abnormal power supply current caused by a short circuit between the C line and the cell GND line can be cut off, and a defective product can be changed into a non-defective product in terms of current.

In FIG. 2, the resistance element R21 is formed of non-doped polysilicon so as to have a resistance of about 10 kilohms, for example. Setting such a high resistance value is because most of the normal power supply current consumption in standby mode (for example, 5 microamperes) is the current consumption of the entire memory cell (for example, in the case of a 1 mechabit semiconductor memory, the cell This is to make the current consumption 1,000,000 times the current consumption of the 102 resistive elements R31 and R32. Generally, by forming the resistance element R21 in the X decoder using the same process as the resistance element of the memory cell, a resistance value of about 10 kΩ can be sufficiently achieved.

As described above, the semiconductor memory of this embodiment can be made good in terms of current by replacing the defective part due to the short circuit between the cell VCC line and the cell GND line and at the same time cutting off the abnormal current path. It has some remarkable features.

A second embodiment of the invention is shown in FIG.

This embodiment has a redundant bit line S in addition to the first embodiment described above.
EL, SEL and their peripheral circuits, P-channel transistor QPlfi for bit line load, fuse element F61 for gate potential control of QPI□. This is a semiconductor memory to which a resistive element R61 and the like are added.

Generally, short circuits between the word line polysilicon layer and the bit line aluminum layer occur due to dust during the formation of the interlayer insulating film during the diffusion process. Normally-on P-channel transistor Q p r' + (Q p l
2) and the N-channel transistor Q585 in FIG.
Or via QN8□, Vco-Qpll (Qpl)
→BL([)-WL-QN, 5 or QN,,-GND
An abnormal current was flowing through the path. Therefore, even if a bit line containing a defective portion (defective bit line) is replaced with a redundant bit line and becomes operationally good, it remains a defective product in terms of current specifications.

In the semiconductor memory of this embodiment, a fuse element F61 is provided between the gate electrode of the bit line load P-channel transistor QPI,' (QP12) and the GND wiring. Also, with this gate electrode. . A resistance element R61 is provided between the wiring and the resistance element R61, and the resistance value thereof is set to, for example, about 10 gigaohms. Therefore, when the fuse is not blown, this gate potential becomes almost the GND potential, so as in the conventional example described above, the P-channel transistor Qp++ (Qp
+□) is in a normally on state, and its operation is similar to the conventional example.

Next, when fuse element F61 corresponding to the defective bit line is cut, P channel transistor QPI, (QP12
) is pulled up to VCC potential by resistance element Rs+. As a result, the line load P-channel transistor QPl.

(Q, 1□) is turned off, cutting off an abnormal current path caused by a short-circuit failure between the bit line and the word line. - On the other hand, P-channel transistor QPII (Q p
When the gate electrode of the inverter IN becomes the VCC potential, the output of the inverter IN becomes the GND potential, and the X decoder 60
The output of 1 (NAND circuit) becomes the ■oo potential regardless of the level of the pre-Y decoder output, and as a result, the Y
Switch transistor QP16+Q p l + l
Q Ni + + Q N l 2 are all turned off, operationally inactivating the number of defective bits. Therefore, when the redundant bit lines SEL and SBL selected by the redundant Y decoder output are selected, the defective bit line is also selected to prevent malfunction from occurring.

As described above, the semiconductor memory of this embodiment has not only an abnormal current path due to a short circuit between the cell VCC line and the cell GND line, but also
This has the effect of further improving the yield of non-defective products by also blocking abnormal current paths due to short circuits between bit lines and word lines.

A third embodiment of the invention is shown in FIG.

This embodiment shows a case where the second embodiment described above is applied to an 8-bit Ota type semiconductor memory.

In the case of an 8-bit input/output type, one Y-tecoder 70 is used for eight bit line pairs BL-BL, as shown in FIG.
1, so as shown in the figure, the fuse element Fa1. Resistance element R is also connected to eight bit line pairs BL-B.
It is good to provide one in common for each L. Therefore, the number of elements can be significantly reduced compared to the second embodiment described above.

Other operations and effects are similar to those of the second embodiment described above.

〔Effect of the invention〕

As explained above, the present invention provides a V for memory cells. 0 wiring and main V. By providing a fuse element between the 0 wiring, or between the gate electrode of the bit line load transistor and the GND wiring, and cutting the fuse element in accordance with the defective location, the V for the cell. By blocking abnormal current paths caused by defects such as short circuits between the 0 line and cell GND lines, or short circuits between bit lines and word lines, the yield of non-defective products can be significantly increased by converting products with defective current specifications into non-defective products. This has the effect of providing an improved semiconductor memory.

Note that each of the above embodiments is an example in which the present invention is applied to a static RAM, but the present invention also applies to a dynamic RAM.
It can also be applied to M, programmable ROM, etc. others,
It goes without saying that various examples of application that satisfy the gist of the present invention are possible.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a main part of a semiconductor memory according to a first embodiment of the present invention, FIG. 2 is a circuit diagram of its X decoder, FIG. 3 is a circuit diagram of its memory cell, and FIG. 4 is its redundant circuit diagram. A circuit diagram of the X decoder, FIG. 5 is a layout diagram of its memory cells, FIG. 6 is a main circuit diagram showing a semiconductor memory according to a second embodiment of the present invention, and FIG. 7 is a third embodiment of the present invention. FIG. 8 is a circuit diagram of a main part showing an example semiconductor memory, FIG. 8 is a circuit diagram of a main part showing a conventional semiconductor memory, and FIG. 9 is a circuit diagram of an X decoder thereof. 101.801...X decoder, 102...
・Memory cell, 103...Redundant word line driver, 104.601,701...Y decoder,
105...Data input driver, 106...
...Data sense amplifier, IN, □, IN6. ．． IN,
. , INN13INy2...Inverter. Agent Patent Attorney Oto Uchihara Figure 2 Figure 3 Figure 4 Figure 5
/4θ 1shi-J Figure 7

Claims (5)

[Claims] (1) A fuse element is provided between the memory cell power supply wiring and the main power supply wiring, and depending on the potential of the memory cell power supply wiring,
A semiconductor memory configured to control a word line decoder circuit. (2) 1 between the memory cell power supply wiring and the GND wiring.
characterized by providing a resistance element of kiloohm or more,
A semiconductor memory according to claim (1). (3) A fuse element is provided between the gate electrode of the bit line load P-channel (N-channel) transistor and the GND wiring (power supply wiring), and the bit line decoder circuit is controlled by the potential of the gate electrode. A semiconductor memory characterized by: (4) The semiconductor memory according to claim (3), characterized in that a resistance element of 1 kilohm or more is provided between the gate electrode and the power supply wiring (GND wiring). (5) By cutting the fuse element corresponding to the defective word line or defective bit line detected in the wafer probing test after the diffusion process with a laser beam, the defective word line or defective bit line is removed. 5. The semiconductor memory according to claim 1, wherein the semiconductor memory is inactivated.