JPH04186894A - Manufacture of printed wiring board - Google Patents

Manufacture of printed wiring board

Info

Publication number
JPH04186894A
JPH04186894A JP31695290A JP31695290A JPH04186894A JP H04186894 A JPH04186894 A JP H04186894A JP 31695290 A JP31695290 A JP 31695290A JP 31695290 A JP31695290 A JP 31695290A JP H04186894 A JPH04186894 A JP H04186894A
Authority
JP
Japan
Prior art keywords
hole
photosensitive
layer
dry film
ink
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31695290A
Other languages
Japanese (ja)
Inventor
Masahiro Katada
片田 政弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Toppan Circuit Solutions Toyama Inc
Original Assignee
NEC Toppan Circuit Solutions Toyama Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Toppan Circuit Solutions Toyama Inc filed Critical NEC Toppan Circuit Solutions Toyama Inc
Priority to JP31695290A priority Critical patent/JPH04186894A/en
Publication of JPH04186894A publication Critical patent/JPH04186894A/en
Pending legal-status Critical Current

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  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)

Abstract

PURPOSE:To obtain a highly reliable high-density printed wiring board by forming a photosensitive resin film and photosensitive dry film layer on an insulating substrate after filling up a copper-plated hole with hole filling ink and exposing a prescribed wiring pattern by using a mask film brought into contact with the dry film layer, and then, etching a conductor layer after selectively removing the unexposed parts of the photosensitive resin film and photosensitive dry film layer. CONSTITUTION:After a hole is bored through an insulating substrate 2, a conductor layer 1 is formed and the through hole is filled up with hole filling ink 3 to both surfaces of the substrate 2. Then, after hardening the ink by irradiating the ink with ultraviolet rays and removing the ink 3 adhering to the conductor layer 1, a photosensitive resin film 5 is formed by applying and drying a liquefied photosensitive resin and a dry film layer 6 is formed by thermocompression bonding a dry film. Thereafter, etching resist films 6b and 6c are formed by exposing and developing a prescribed wiring circuit pattern through a mask film 4 and the exposed part of the conductor layer 1 is removed by etching by using the layers 6b and 6c as etching masks.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は印刷配線板の製造方法に関し、特に高密度の配
線回路を有するスルーホール印刷配線板の製造方法に関
する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a printed wiring board, and more particularly to a method for manufacturing a through-hole printed wiring board having a high-density wiring circuit.

〔従来の技術〕[Conventional technology]

一般に、スルーホール印刷配線板(以下、T/HPWB
と称す。)の製造には、第2図(a)〜(f)の如く、
テンティング工法が多く用いられており、この方法に依
れば、第2図(a)の如く、絶縁基板2上に銅めっき層
を含む導体層1とスルーホール1aを形成した絶縁基板
2上に第2図(b)の如く感光性ドライフィルム層(以
下、ドライフィルム層と称す。)6を貼付し、この上か
ら第2図(c)の如く、マスクフィルム4を介して所定
の配線回路のパターンを紫外線で焼き付ける。
Generally, through-hole printed wiring board (hereinafter referred to as T/HPWB)
It is called. ) As shown in Figure 2 (a) to (f),
The tenting method is often used, and according to this method, as shown in FIG. A photosensitive dry film layer (hereinafter referred to as a dry film layer) 6 is pasted on the film as shown in FIG. Burn the circuit pattern with ultraviolet light.

次に、現像液で不要部分のドライフィルム層6を除去し
第2図(d)のエツチングレジスト層6a。
Next, unnecessary portions of the dry film layer 6 are removed using a developer to form the etching resist layer 6a as shown in FIG. 2(d).

6bを得る。Get 6b.

更に、露出した導体層1をエツチング除去し第2図(e
)の配線回路1bとした後、最後にエツチングレジスト
層6a、6bを剥離除去して第2図(DのT/HPWB
を得るものである。
Furthermore, the exposed conductor layer 1 is removed by etching as shown in FIG.
), and finally the etching resist layers 6a and 6b are peeled off to form the wiring circuit 1b in FIG.
This is what you get.

又、第3図に示す如き穴埋め工法では、第3図(a)の
絶縁基板2上に銅めっき層を含む導体層1とスルーホー
ル1aを形成した絶縁基板2のスルーホール1aの内部
に第3図(b)のように穴うめインク3を充填、硬化さ
せ、絶縁基板2表面にドライフィルム層6を貼付し、こ
の上から第3図(d)の如く、マスクフィルム4を介し
て所定の配線パターンを紫外線で焼き付ける。
In addition, in the hole filling method as shown in FIG. 3, a conductor layer 1 including a copper plating layer and a through hole 1a are formed on the insulating substrate 2 of FIG. 3(a). As shown in FIG. 3(b), the hole-filling ink 3 is filled and cured, and a dry film layer 6 is pasted on the surface of the insulating substrate 2, and as shown in FIG. Burn the wiring pattern with ultraviolet light.

次に、現像液で不要部分のドライフィルム層6を除去し
第3図(e)のエツチングレジスト層6b。
Next, unnecessary portions of the dry film layer 6 are removed using a developer to form the etching resist layer 6b shown in FIG. 3(e).

6cを得る。Get 6c.

更に、露出した導体層1をエツチング除去し第3図Cf
)の配線回路1bとした後、最後にエツチングレジスト
層6b、6cおよび穴うめインク3を剥離除去して第3
図(g)のT/HPWBを得るものである。
Furthermore, the exposed conductor layer 1 is removed by etching as shown in FIG.
), and finally, the etching resist layers 6b, 6c and the hole-filling ink 3 are peeled off to form the third wiring circuit 1b.
The T/HPWB shown in Figure (g) is obtained.

尚、この工法では、ドライフィルム層6によるエツチン
グレジスト層6b、6cの代わりに、スクリーン印刷に
よって形成された画像をエツチングレジスト層6b、6
cとして用いることもできる。
In addition, in this method, instead of the etching resist layers 6b and 6c formed by the dry film layer 6, images formed by screen printing are used as the etching resist layers 6b and 6c.
It can also be used as c.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、テンティング工法の場合、エツチングレジスト
層を第2図(d)のエツチングレジスト層6aのような
テンティング状態としてスルーホール内部をエツチング
液から保護することが必要なため、スルーホールをドラ
イフィルム層で完全にカバーしていなければならず、第
2図(f)の大の直径よりも大きなスルーホールランド
(以下、T/Hランドと称す)lcを確保することが必
要であった。また、大径スルーホールでは、エツチング
工程でのスプレィ圧力等によりエツチングレジストが亀
裂や浮きを生じ、スルーホールlaとT/Hランド1c
の接続部やスルーホールランドの銅を保護できないとい
う問題点があった。
However, in the case of the tenting method, it is necessary to protect the inside of the through hole from the etching solution by putting the etching resist layer in a tenting state like the etching resist layer 6a in FIG. 2(d), so the through hole is covered with a dry film. It was necessary to completely cover the through-hole land (hereinafter referred to as T/H land) lc with a larger diameter than the large diameter shown in FIG. 2(f). In addition, in large-diameter through holes, the etching resist may crack or lift due to spray pressure etc. during the etching process, causing through holes la and T/H lands 1c.
There was a problem in that it was not possible to protect the copper connections and through-hole lands.

更に、近年、配線回路1bが高密度化するに伴い、前記
T/Hランド1cの縮小化が進み、テンティング工法に
よるスルーホール1a形成が困難になるという問題点が
あった。
Furthermore, in recent years, as the wiring circuit 1b has become denser, the T/H land 1c has become smaller, making it difficult to form the through hole 1a by the tenting method.

一方、穴埋め工法は、銅めっき後、第3図(b)のよう
にスルーホール内部を穴うめインク3で充填するため、
T/Hランドサイズを穴の直径と同程度まで縮小できる
利点があるものの、第3図(b)の導体層1上の表面の
きず、だこんによる凹部ラドライフィルム層がカバーし
きれない為、エツチング工程で断線を生じ易く高密度配
線回路を有するT/HPWBの製造方法としては適切な
方法とは云えなかった。また、第3図(b )、 (c
 )に於て、スルーホール内の穴うめインク3と密着不
良が生じた場合、エツチング工程で、スプレィ圧力等に
より、エツチングレジスト層が亀裂や浮きを生じ、スル
ーホールと配線回路の接続部やスルーホール内の銅を保
護できないという問題点があった。
On the other hand, in the hole-filling method, after copper plating, the inside of the through-hole is filled with hole-filling ink 3 as shown in Figure 3(b).
Although there is an advantage that the T/H land size can be reduced to the same level as the hole diameter, the recesses due to surface scratches and dents on the conductor layer 1 shown in Fig. 3(b) cannot be covered by the Radry film layer. However, this method was not suitable for manufacturing T/HPWBs having high-density wiring circuits because wire breakage was likely to occur during the etching process. In addition, Fig. 3 (b), (c
), if poor adhesion occurs with the hole-filling ink 3 in the through-hole, the etching resist layer will crack or lift due to spray pressure etc. during the etching process, and the connection between the through-hole and the wiring circuit or the through-hole will be damaged. There was a problem that the copper inside the hole could not be protected.

本発明の目的は、高密度配線回路を有する印刷配線板の
製造方法を提供することにある。
An object of the present invention is to provide a method for manufacturing a printed wiring board having a high-density wiring circuit.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の印刷配線板の製造方法は、銅張絶縁基板に穴を
穿設する工程と、前記絶縁基板の穴及び前記絶縁基板表
面に銅めっき層を形成する工程と、前記銅めっき層が形
成された穴及び前記絶縁基板上に穴うめインクを塗布し
、前記銅めっき層が形成された穴内に穴うめインクを充
填する工程と、前記穴うめインクを熱硬化又はUV硬化
後、前記絶縁基板表面上の前記穴うめインクを研磨除去
し前記銅めっき層を露出する工程と、前記銅めっき層の
表面に、感光性液状樹脂を塗布した後乾燥し感光性樹脂
塗膜を形成する工程と、前記感光性樹脂塗膜の上に感光
性ドライフィルム層を熱圧iする工程と、前記感光性ド
ライフィルム層上にマスクフィルムを当接し所定の配線
回路のパターンを露光した後、現像により未露光部分の
前記感光性ドライフィルム層と前記感光性樹脂塗膜(感
光性液状樹脂を塗布・乾燥した塗膜)を選択的に除去す
る工程と、現像により露出した網部分をエツチングで除
去する工程と、更に、残存する前記感光性ドライフィル
ム層と前記感光性樹脂塗膜及び前記穴内の前記穴うめイ
ンクを除去する工程とを含んで配線回路が得られる。
The method for manufacturing a printed wiring board of the present invention includes the steps of: drilling a hole in a copper-clad insulating substrate; forming a copper plating layer on the hole in the insulating substrate and on the surface of the insulating substrate; and forming the copper plating layer. a step of applying hole-filling ink to the hole formed and on the insulating substrate, and filling the hole-filling ink into the hole in which the copper plating layer is formed; and after curing the hole-filling ink by heat or UV curing, a step of polishing away the hole-filling ink on the surface to expose the copper plating layer; a step of applying a photosensitive liquid resin to the surface of the copper plating layer and then drying it to form a photosensitive resin coating; A step of heat-pressing a photosensitive dry film layer on the photosensitive resin coating film, and a step of contacting a mask film on the photosensitive dry film layer to expose a predetermined wiring circuit pattern, and then developing it so that it is not exposed to light. a step of selectively removing the photosensitive dry film layer and the photosensitive resin coating film (a coating film obtained by coating and drying a photosensitive liquid resin) of the portion, and a step of removing by etching the mesh portion exposed by development. Further, a wiring circuit is obtained, further comprising the step of removing the remaining photosensitive dry film layer, the photosensitive resin coating, and the hole-filling ink in the holes.

〔実施例〕〔Example〕

以下に、本発明の実施例について図面を参照して説明す
る。
Embodiments of the present invention will be described below with reference to the drawings.

第1図(a)〜(i)は本発明の一実施例の製造方法を
説明する工程順に示した断面図である。
FIGS. 1(a) to 1(i) are cross-sectional views showing the steps of a manufacturing method according to an embodiment of the present invention.

まず、第1図(a)の如く、絶縁基板2に穴を穿孔した
後、導体層1を形成する。絶縁基板2の材質としては、
例えばガラス布基材エポキシ樹脂板や、ガラス基材ポリ
イミド樹脂板を使用できる。
First, as shown in FIG. 1(a), a hole is bored in an insulating substrate 2, and then a conductor layer 1 is formed. The material of the insulating substrate 2 is as follows:
For example, a glass cloth-based epoxy resin plate or a glass-based polyimide resin plate can be used.

次に、第1図(b)の如く、絶縁基板2の表面全体との
スルーホール内に穴うめインク3を充填し、絶縁基板2
の両面に1〜IOJ/cnの紫外線を照射して硬化させ
る。穴うめインク3に熱硬化型のものを用いる場合には
、穴うめインク3を硬化させる為、温度80〜140℃
で30〜120分間乾燥し硬化させる。
Next, as shown in FIG. 1(b), hole-filling ink 3 is filled in the through holes between the entire surface of the insulating substrate 2, and the insulating substrate 2 is
Both surfaces are irradiated with ultraviolet rays of 1 to IOJ/cn to be cured. When using a thermosetting type of hole-filling ink 3, the temperature is 80 to 140℃ to cure the hole-filling ink 3.
Dry and cure for 30 to 120 minutes.

次いで、第1図(c)の如く、導電層lの上に付着した
穴うめインク3を、パフまたはサンドペーパー等の研磨
材を用いて除去し、銅表面を露出させる。
Next, as shown in FIG. 1(c), the hole-filling ink 3 adhering to the conductive layer 1 is removed using an abrasive material such as a puff or sandpaper to expose the copper surface.

次に、第1図(d)の如く感光性液状樹脂をローラーコ
ート法で塗布し、50〜150℃で乾燥して、感光性樹
脂塗膜5を形成する。
Next, as shown in FIG. 1(d), a photosensitive liquid resin is applied by a roller coating method and dried at 50 to 150°C to form a photosensitive resin coating 5.

次に、第1図(e)の如く、ドライフィルムを温度80
〜120℃で熱圧着し、ドライフィルム層6を形成する
。
Next, as shown in Figure 1(e), the dry film was heated to 80°C.
The dry film layer 6 is formed by thermocompression bonding at ~120°C.

更に、第1図(f)の如く、マスクフィルム4を介して
、露光により所定の配線回路のパターンを焼付ける。
Furthermore, as shown in FIG. 1(f), a predetermined wiring circuit pattern is printed through the mask film 4 by exposure.

次に、第1図(g)の如く、炭酸ソーダ水溶液などの現
像液で現像し、エラチンブレジス)J16b。
Next, as shown in FIG. 1(g), it was developed with a developer such as an aqueous solution of sodium carbonate to obtain Eratin Breath J16b.

6cを形成する。Form 6c.

次に、第1図(h)の如く、エツチングレジスト層6b
、6cをエツチングマスクとして、導電層1の露出した
部分をエツチング除去する。
Next, as shown in FIG. 1(h), an etching resist layer 6b is formed.
, 6c as an etching mask, the exposed portion of the conductive layer 1 is etched away.

最後に、第1図(りの如くエツチングレジスト層6b、
6c、感光性樹脂塗膜5及び穴うめインク3を、薬品等
を用いて除去して、T/HPWBを得るものである。
Finally, as shown in FIG. 1, the etching resist layer 6b,
6c, the photosensitive resin coating 5 and the hole-filling ink 3 are removed using chemicals or the like to obtain T/HPWB.

尚、第1図(d)においては、ローラーコート法の他、
スプレィコート法やカーテンコート法を用いることがで
きる。
In addition, in Fig. 1(d), in addition to the roller coating method,
A spray coating method or a curtain coating method can be used.

〔発明の効果〕〔Effect of the invention〕

以上の説明から明らかなように、本発明によれば、銅め
っき穴に穴うめインクを充填し、更に、絶縁基板表面上
に感光性樹脂塗膜、感光性ドライフィルム層を形成し、
マスクフィルムを当接し、所定の配線パターンを露光の
後、未露光部分の感光性樹脂塗膜と感光性ドライフィル
ム層を選択的に除去して導体層のエツチングを行うこと
により、(イ)テンティンダニ法では不可能であったT
/Hランド幅縮小が可能となる、(ロ)大径スルーホー
ルでも、エツチング工程でのスプレィ圧力等に充分耐え
ることによりスルーホールとランドの接続部やスルーホ
ール内の銅を保護できる、(ハ)表面のきす、だこんに
よる凹部を感光性樹脂塗膜により平滑にできる為、エツ
チング工程での断線を大幅に低減できる、(ニ)スルー
ホール内に充填した穴うめインクと感光性樹脂塗膜との
密着力によりスルーホールとランドの接続部やスルーホ
ール内の導電層を充分保護できる等の効果があり、これ
により信頼性の高い高密度印刷配線板の製造が可能とな
る。
As is clear from the above description, according to the present invention, copper plating holes are filled with hole-filling ink, and a photosensitive resin coating and a photosensitive dry film layer are further formed on the surface of the insulating substrate.
After exposing a predetermined wiring pattern to light using a mask film, etching the conductor layer by selectively removing the photosensitive resin coating and photosensitive dry film layer in the unexposed areas allows (a) Tentin mites to be removed. T that was impossible under the law
/H The land width can be reduced. (B) Even large diameter through holes can protect the connection between the through hole and the land and the copper inside the through hole by sufficiently withstanding spray pressure etc. during the etching process. ) Since the concave parts caused by scratches and dents on the surface can be smoothed with the photosensitive resin coating, disconnections during the etching process can be significantly reduced. (d) Hole-filling ink and photosensitive resin coating filled in the through holes. The adhesion between the through-hole and the land has the effect of sufficiently protecting the connection between the through-hole and the land and the conductive layer inside the through-hole, thereby making it possible to manufacture highly reliable high-density printed wiring boards.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(i)は本発明の一実施例の製造方法を
説明する工程順に示した断面図、第2図(a)〜(f)
は従来のテンティング工法による印刷配線板の製造方法
の一例を説明する工程順に示し印刷配線板の製造方法の
一例を説明する工程順に示した断面図である。 1・・・・・・導体層、1a・・・・・・スルーホール
、1b・・・・・・配線回路、1c・・・・・・スルー
ホールランド、2・・・・・・絶縁基板、3・・・・・
・穴うめインク、4・・・・・・マスクフィルム、5・
・・・・・感光性樹脂塗膜、6・・・・・・ドライフィ
ルム層、6a・・・・・・テンティング状態のエツチン
グレジスト層、6b・・・・・・配線回路部分のエツチ
ングレジスト層、6c・・・・・・スルーホール上のエ
ツチングレジスト層。 代理人 弁理士  内 原   音 第1 m l    j    j    L   、1    
jfタト彰丸tttit 第 2 図 / 第26 第3図
FIGS. 1(a) to (i) are cross-sectional views showing the manufacturing method of an embodiment of the present invention in the order of steps, and FIGS. 2(a) to (f)
1A and 1B are cross-sectional views illustrating an example of a method for manufacturing a printed wiring board using a conventional tenting method in the order of steps; FIG. 1...Conductor layer, 1a...Through hole, 1b...Wiring circuit, 1c...Through hole land, 2...Insulating substrate , 3...
・Hole filling ink, 4...Mask film, 5.
... Photosensitive resin coating film, 6 ... Dry film layer, 6a ... Etching resist layer in tenting state, 6b ... Etching resist of wiring circuit part Layer 6c... Etching resist layer on the through hole. Agent Patent Attorney Uchihara Oto No. 1 ml j j L, 1
jf Tato Shomaru tttit Figure 2/ Figure 26 Figure 3

Claims (1)

【特許請求の範囲】[Claims]  銅張絶縁基板に穴を穿設する工程と、前記絶縁基板の
穴及び前記絶縁基板表面に銅めっき層を形成する工程と
、前記銅めっき層が形成された穴及び前記絶縁基板上に
穴うめインクを塗布し、前記銅めっき層が形成された穴
内に穴うめインクを充填する工程と、前記穴うめインク
を熱硬化又はUV硬化後、前記絶縁基板表面上の前記穴
うめインクを研磨除去し前記銅めっき層を露出する工程
と、前記銅めっき層の表面に、感光性液状樹脂を塗布し
た後乾燥し感光性樹脂塗膜を形成する工程と、前記感光
性樹脂塗膜の上に感光性ドライフィルム層を熱圧着する
工程と、前記感光性ドライフィルム層上にマスクフイル
ムを当接し所定の配線回路のパターンを露光した後、現
像により未露光部分の前記感光性ドライフィルム層と前
記感光性樹脂塗膜(感光性液状樹脂を塗布・乾燥した塗
膜)を選択的に除去する工程と、現像により露出した銅
部分をエッチングで除去する工程と、更に、残存する前
記感光性ドライフィルム層と前記感光性樹脂塗膜及び前
記穴内の前記穴うめインクを除去する工程とを含んで配
線回路を得ることを特徴とする印刷配線板の製造方法。
a step of drilling a hole in a copper-clad insulating substrate, a step of forming a copper plating layer on the hole of the insulating substrate and the surface of the insulating substrate, and filling the hole in which the copper plating layer is formed and the hole on the insulating substrate. A step of applying ink and filling the hole-filling ink into the hole in which the copper plating layer is formed, and after curing the hole-filling ink with heat or UV curing, polishing and removing the hole-filling ink on the surface of the insulating substrate. a step of exposing the copper plating layer, a step of applying a photosensitive liquid resin to the surface of the copper plating layer and drying it to form a photosensitive resin coating, and applying a photosensitive liquid resin on the photosensitive resin coating film. A process of thermocompression bonding a dry film layer, and a mask film is brought into contact with the photosensitive dry film layer and a predetermined wiring circuit pattern is exposed to light, and then the unexposed portions of the photosensitive dry film layer and the photosensitive film are developed. A step of selectively removing the resin coating film (a coating film formed by coating and drying a photosensitive liquid resin), a step of etching away the copper portion exposed by development, and a step of removing the remaining photosensitive dry film layer. A method for manufacturing a printed wiring board, comprising the step of removing the photosensitive resin coating film and the hole-filling ink in the holes to obtain a wiring circuit.
JP31695290A 1990-11-21 1990-11-21 Manufacture of printed wiring board Pending JPH04186894A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31695290A JPH04186894A (en) 1990-11-21 1990-11-21 Manufacture of printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31695290A JPH04186894A (en) 1990-11-21 1990-11-21 Manufacture of printed wiring board

Publications (1)

Publication Number Publication Date
JPH04186894A true JPH04186894A (en) 1992-07-03

Family

ID=18082767

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31695290A Pending JPH04186894A (en) 1990-11-21 1990-11-21 Manufacture of printed wiring board

Country Status (1)

Country Link
JP (1) JPH04186894A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100601486B1 (en) * 2004-12-21 2006-07-18 삼성전기주식회사 Chip embedded printed circuit board and its manufacturing method
JP2008109144A (en) * 2007-11-05 2008-05-08 Toshiba Corp Circuit board manufacturing method and circuit board inspection method
CN106686903A (en) * 2017-01-19 2017-05-17 广州美维电子有限公司 Treatment process of PTH (Plating Through Hole) plate
CN114885505A (en) * 2022-05-30 2022-08-09 圆周率半导体(南通)有限公司 Novel method for replacing back drilling by etching

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100601486B1 (en) * 2004-12-21 2006-07-18 삼성전기주식회사 Chip embedded printed circuit board and its manufacturing method
JP2008109144A (en) * 2007-11-05 2008-05-08 Toshiba Corp Circuit board manufacturing method and circuit board inspection method
CN106686903A (en) * 2017-01-19 2017-05-17 广州美维电子有限公司 Treatment process of PTH (Plating Through Hole) plate
CN114885505A (en) * 2022-05-30 2022-08-09 圆周率半导体(南通)有限公司 Novel method for replacing back drilling by etching
CN114885505B (en) * 2022-05-30 2023-08-18 圆周率半导体(南通)有限公司 Novel method for replacing back drill by etching

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