JPH0418789A - Manufacture of printed wiring board - Google Patents

Manufacture of printed wiring board

Info

Publication number
JPH0418789A
JPH0418789A JP12127390A JP12127390A JPH0418789A JP H0418789 A JPH0418789 A JP H0418789A JP 12127390 A JP12127390 A JP 12127390A JP 12127390 A JP12127390 A JP 12127390A JP H0418789 A JPH0418789 A JP H0418789A
Authority
JP
Japan
Prior art keywords
layer
copper
tin plating
etching
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12127390A
Other languages
Japanese (ja)
Inventor
Akira Kabumoto
昭 株本
Kenichi Otani
健一 大谷
Toshio Mugishima
利夫 麦島
Osamu Seki
関 収
Eiichi Taguchi
栄一 田口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Furukawa Electric Co Ltd
Original Assignee
Furukawa Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Furukawa Electric Co Ltd filed Critical Furukawa Electric Co Ltd
Priority to JP12127390A priority Critical patent/JPH0418789A/en
Publication of JPH0418789A publication Critical patent/JPH0418789A/en
Pending legal-status Critical Current

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  • Parts Printed On Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE:To enable a chrome layer to be etched and concurrently a tin plating layer to be formed by the use of an electroless tin plating solution so as to simplify a manufacturing process by a method wherein a copper circuit is formed on the chrome layer provided onto the surface of an insulating layer, then the disused part of the chrome layer is removed with an electroless tin plating solution, and concurrently a tin plating layer is provided onto the surface of the copper circuit. CONSTITUTION:A chrome layer 2 and a copper layer 1 are formed on a polyimide film 3 (insulating layer) as thick as 3nm and 10mum respectively through a magnetron sputtering method to form a board used for a flexible wiring board, and a photoresist 4 of required pattern is provided onto the surface of the copper layer 1. In succession, the copper layer 1 is etched with a copper etching solution kept at a temperature of 40 deg.C to form a copper circuit la. Then, the photoresist is removed with acetone, then a tin plating layer 5 is formed as thick as 0.3-0.6mum on the surface of the copper circuit la by the use of an electroless tin plating solution kept at a temperature of 60 deg.C, and concurrently the chrome layer 2 is etched.

Description

【発明の詳細な説明】 [産業上の利用分野] この発明は、高密度実只′可能なプリント配線板を効率
良く製造する方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for efficiently manufacturing a high-density printed wiring board.

[従来の技!xIli ] 高密度実装に対応するためのフレギシブルブリンl、配
線板には、絶縁層と銅層の音名性を向4−させるために
下地層としてクロム層を設けた基板材料が好ま17<用
いられる。
[Traditional technique! [xIli] For flexible wiring boards to support high-density packaging, it is preferable to use a substrate material with a chromium layer as an underlayer to improve the tonal properties of the insulating layer and copper layer17 <Used.

従来、かかるプリント配線板は、ま−4′銅層をエツチ
ングして銅回路を形成し、続い゛C1下地層としてのク
ロム層をW用のエラチングイ夜を用いて銅回路に沿−)
でエツチングした後、更に、’I’−fll付は性を向
■−させる等の目的で、銅回路表面に錫メッキ層を設け
るという3段階の主要なT稈を経ることにより製造さ1
1ている。
Conventionally, such printed wiring boards are produced by etching a first copper layer to form a copper circuit, and then etching a chromium layer as a C1 underlayer along the copper circuit using an etching process for W.
After etching, 'I'-flll attachment is manufactured by going through three main steps of forming a tin plating layer on the surface of the copper circuit for the purpose of improving the properties.
There are 1.

この1)京、クロム層の工・ンチングン夜どし−こけ、
酸・1′1[の工・ソチング液(0,1−3mat/、
Qの塩酸水溶液便宜上、これをA液とする)、或は硝酸
第2セリウムアンモニウム115gと70零の過塩素酸
30m1を水10100Oに溶解させた毛ツヂングir
l (便宜1−1これをB ン1とする)、或はアルカ
リ+11の工・ソチング液(フェリシアン化カリウム1
40gと水酸化す[・リウム90.りを水10100O
に溶解させたエツチング液(便宜−ヒ、これをC液とす
る)テ・γを使用し2゛Cいる。
This 1) Kyoto, chromium layer work, Nchingun night moss,
Acid, 1'1 [processing, soting solution (0,1-3mat/,
Hydrochloric acid aqueous solution of Q (For convenience, this will be referred to as Solution A), or Mao Zzingir, which is prepared by dissolving 115 g of ceric ammonium nitrate and 30 ml of 70% perchloric acid in 10,100O of water.
(For convenience 1-1, refer to this as B 1), or alkali + 11 processing/soching solution (potassium ferricyanide 1
40g and 90g of hydroxide. Water 10100O
An etching solution (for convenience, this will be referred to as solution C) dissolved in water at 2°C is used.

[発明か解決しよつどする課題] しかしながら、■−記のような従来の製造方法において
は、Aン夜あるし\は87夜をクロム層の工・ンチンダ
液として用いた場合、クロム層の膜厚が5nmよりも薄
いと、クロムの酸化膜か形成されるためか、完全にクロ
ム層が除去てきないという現象が認めらねるという問題
があった。一方、C液をエツチング液として用いた場合
には、クロム層の膜厚に関係なくエツチングが可能であ
るものの、C液はジアン系の溶媒であるため廃液の問題
を考慮すると、環境衛生ト、好ましくないという問題か
ある。
[Problem to be solved by the invention] However, in the conventional manufacturing method as described in ■--, when A and A are used as the coating solution for the chromium layer, If the film thickness is less than 5 nm, there is a problem in that the chromium layer is not completely removed, probably because a chromium oxide film is formed. On the other hand, when liquid C is used as an etching liquid, etching is possible regardless of the thickness of the chromium layer. There is a problem with not liking it.

また、生産性・経済性の向−Fを図るために工程の削減
を考えた場合、銅層とクロム層を同じエツチング液で同
時にエツチングできねば、より合理的であるが、現在の
ところ銅層どクロム層の両方をエツチングできるエツチ
ング液は開発されていない一ト、仮に、そのようなエツ
チング液があったとしても、クロム層をエツチングして
いる間に、先にエツチングが完了している銅層も更にエ
ツチングされることとなるため、銅回路がオーバーエツ
チングさねてしまい、パターン精度(エツチングファク
ターやビッヂ1″^度等)に悪影響を及はずといった問
題か生してしまう。
Furthermore, when considering the reduction of processes in order to improve productivity and economy, it would be more rational if the copper layer and chromium layer could be etched at the same time with the same etching solution, but currently the copper layer No etching solution has been developed that can etch both the copper layer and the chromium layer. Even if such an etching solution were available, while etching the chromium layer, the etching solution would be Since the layer is further etched, the copper circuit may be over-etched, causing problems such as adversely affecting pattern accuracy (etching factor, bit width, etc.).

この発明は、かかる、のに鑑みてなされたものであり、
下地層としてクロム層を有する高密度微細回路を効率良
く形成することかてきるプリンI・配線板の製造方法を
提供することを目的とするものである。
This invention was made in view of the above,
The object of the present invention is to provide a method for manufacturing a printed circuit board and a wiring board that can efficiently form a high-density fine circuit having a chromium layer as an underlayer.

[課題を解決するための手段コ 本発明ては、クロム層−銅層一錫メッキ層の積層構造を
有する回路を絶縁層十に形成するプリント配線板の製造
方法において、前記絶縁層表面に設るづられたクロム層
−Fに銅回路を形成し、その後、無電解錫メッキ液を用
いて、前記クロム層の不要部分をエツチングにより除去
すると同時に、前記銅回路表面に錫メッキ層を設りるこ
とににって、上記の課題を達成している。
[Means for Solving the Problems] The present invention provides a method for manufacturing a printed wiring board in which a circuit having a laminated structure of a chromium layer, a copper layer, and a tin plating layer is formed on ten insulating layers. A copper circuit is formed on the rolled chromium layer-F, and then an unnecessary portion of the chromium layer is removed by etching using an electroless tin plating solution, and at the same time, a tin plating layer is provided on the surface of the copper circuit. In particular, the above tasks have been achieved.

[作用コ 本発明においては、従来はエツチング液としては考えら
れていなかった無電解錫メッキ液(一般に、塩化第2錫
を主成分とし、他に硫黄化合物やフッ化化合物等を含有
)を用いてクロム層のエツチングを行なっている。即ち
、本発明では、銅層とクロl\層を同しン夜て工・ンチ
ングすることにより工程を削減するのではなく、まず銅
回路を形成した後、従来は2工程で行なわれていたクロ
ム層のエツチングと錫メッキとを1工程で同時に行なう
ことににす、合理化を図っている。また、本発明ては、
上述したように銅層とクロム層か別々V形成され、無電
解錫メッキ液によっては銅層のエツチングは進行しない
から、クロム層のエツチングに起因する銅層のオーバー
エツチングか起らない。
[Operations] In the present invention, an electroless tin plating solution (generally containing stannic chloride as a main component and also containing sulfur compounds, fluoride compounds, etc.), which has not been considered as an etching solution in the past, is used. The chromium layer is then etched. That is, in the present invention, instead of reducing the number of steps by forming and etching the copper layer and the chlorine layer at the same time, the copper circuit is formed first, and then the process is performed in two steps. Etching of the chromium layer and tin plating are carried out simultaneously in one process in an effort to streamline the process. In addition, the present invention
As described above, the copper layer and the chromium layer are formed separately, and the etching of the copper layer does not proceed depending on the electroless tin plating solution, so that over-etching of the copper layer due to etching of the chromium layer does not occur.

本発明クロム層の膜厚は、05〜1100nの範囲であ
れば(通常の下地層の膜厚範囲を充分包含する)特に問
題はないか、高精度のエツチングを行なう」二では05
〜5nmの膜厚とすることが望ましい。使用する無電解
錫メッキ液としては、塩化第2錫を主成分とする酸性系
のメッキ液がより好ましい。
If the thickness of the chromium layer of the present invention is in the range of 0.5 to 1100 nm (which sufficiently covers the thickness range of a normal underlayer), there will be no particular problem, or high-precision etching can be performed.
It is desirable that the film thickness be ~5 nm. As the electroless tin plating solution to be used, an acidic plating solution containing stannic chloride as a main component is more preferable.

方、銅層の膜厚及び回路形成方法は、特に限定されるも
のてはなく、サブトラクト法たけてなく、セミアデイテ
ィブ法等て銅回路を形成しても良い。
On the other hand, the thickness of the copper layer and the method of forming the circuit are not particularly limited, and the copper circuit may be formed by a semi-additive method instead of the subtract method.

また、高密度微細回路を形成する場合の絶縁層としては
、ポリイミドフィルム、フッ素括イH旨フィルム(いわ
ゆるテフロンフィルム)、ボリエヂレンフィルム、ポリ
プロピレンフィルム等か好ましく用いられるか、中でも
#iだζ性、耐薬品性1寸法安定性等の点からポリイミ
ドフィルムか特に好ましい。
In addition, as an insulating layer when forming a high-density microcircuit, polyimide film, fluorine film (so-called Teflon film), polyethylene film, polypropylene film, etc. are preferably used, among which #i is used. A polyimide film is particularly preferable from the viewpoints of properties, chemical resistance, one-dimensional stability, and the like.

[実施例] 実施例 第1図(a)〜(c)は本発明第1実施例の製造J。[Example] Example FIGS. 1(a) to 1(c) show production J of the first embodiment of the present invention.

程を枚式的に示した断面図である。FIG.

まず、ポリイミドフィルム3(絶縁層)土にクロム15
3nm 2及び銅層lOμm1をマグネトロンスパッタ
リングにより形成せしめてフレキシブルプリント配線板
用の基板を作製し、第1図(a)のように、銅層1表面
に所望のパターン形状の711−レジスト1を設けた。
First, add chromium 15 to polyimide film 3 (insulating layer) soil.
A substrate for a flexible printed wiring board was prepared by forming a copper layer of 3 nm 2 and a copper layer of 10 μm 1 by magnetron sputtering, and as shown in FIG. Ta.

続いて、温度40℃の銅エツチング液(塩化第2鉄水溶
液)にて銅層1をエツチングし、第1図(b)のJ:う
に銅回路1aを形成した。次ぐ、アセトンによりフォト
レジストを除去した後(第1図(b) ) 、 60℃
の無電解錫メッキ液(エンプレート−TlN421スペ
シヤル メルデックス社製)を用いて、銅回路1a表面
に03〜06μmの錫メッキ層5を設けると同時に、ク
ロム層2のエツチング(銅回路1aかエツチングレジス
トとなる)を1−]ない、第1図(C)のようなフレキ
シブルプリント配線板を得た。
Subsequently, the copper layer 1 was etched with a copper etching solution (ferric chloride aqueous solution) at a temperature of 40° C. to form a copper circuit 1a shown in FIG. 1(b). Next, after removing the photoresist with acetone (Fig. 1(b)), the temperature was 60°C.
Using an electroless tin plating solution (Enplate-TlN421 Special, manufactured by Meldex), a tin plating layer 5 of 03 to 06 μm is provided on the surface of the copper circuit 1a, and at the same time, the chromium layer 2 is etched (the copper circuit 1a is etched). A flexible printed wiring board as shown in FIG. 1(C) without 1-] (which becomes a resist) was obtained.

そし゛C5作製したフレキシブルプリント配線板サンプ
ルについてパターン間の絶縁抵抗値を測定したところ、
下地層としてのクロム層を設すないもの(パターン手法
等の仕様は実施例1に同じ)と同等の価を示した。
Then, when we measured the insulation resistance value between patterns for the flexible printed wiring board sample prepared by C5, we found that
It showed the same value as the one without the chromium layer as the underlayer (the specifications such as the patterning method were the same as in Example 1).

実施例、2 まず、ポリイミドフィルム(絶縁層)上にクロム層3n
m及び銅層0.1 μmをマグネトロンスパッタリング
により形成ゼしめ、更にその一1mに10μmの銅層を
電解銅メッキ法により形成したフレキシブルプリント配
線板用の基板を作製した。
Example 2 First, 3n layers of chromium were formed on the polyimide film (insulating layer).
A substrate for a flexible printed wiring board was prepared by forming a copper layer of 1 m and a copper layer of 0.1 μm in thickness by magnetron sputtering, and then forming a 10 μm copper layer on the other 1 m by electrolytic copper plating.

この基板の銅層表面−にに所望のパターン形状のフォト
レシスI・を設けた後、温度40℃の銅エツチング液(
塩化第2鉄水溶液)にて銅層をエツチングし、銅回路を
形成した。次に、アセトンによりフォトレジストを除去
した後、80℃の!!!!電解錫メッキを夜(エンプレ
ート−TIN421スペシャルメルテックス社製)を用
いて、銅回路表面に03〜06μmの錫メッキ層を設け
ると同時に、クロム層のエツチングを行なった。
After providing a photoresis I in a desired pattern on the surface of the copper layer of this substrate, a copper etching solution (
The copper layer was etched with a ferric chloride aqueous solution to form a copper circuit. Next, after removing the photoresist with acetone, the temperature is 80°C! ! ! ! Using electrolytic tin plating (Enplate-TIN421 manufactured by Special Meltex Co., Ltd.), a tin plating layer of 03 to 06 μm was provided on the surface of the copper circuit, and at the same time, the chromium layer was etched.

そして、作製したフレキシブルプリント配線板サンプル
についてパターン間の絶縁抵抗値を測定したところ、下
地層としてのクロム層を設り2tいもの(パターン寸法
等の仕様は実施例2に同し)と同等の値を示した。
When the insulation resistance value between the patterns was measured for the produced flexible printed wiring board sample, it was found that the insulation resistance value between the patterns was equivalent to that of the 2t one with a chromium layer as the base layer (the specifications such as pattern dimensions are the same as in Example 2). The value was shown.

実施例 3 まず、ポリイミドフィルム(絶縁層)上にクロム層3n
m及び銅層01μmをマグネトリンスバッタリングによ
り形成せしめてフレキシブルプリント配線板用の基板を
作製した。この基板の銅層表面上に所望のパターン形状
のく回路となる部分を露出させるいわゆる逆パターン)
のフォトレジストを設番プ、電解銅メッキ法により総厚
lOμmとなるまで回路と1する部分に銅メッキを施し
た。その9表、アセトンによりフォトレジストを1≦余
去し、40℃の銅エツチング液(塩化第2鉄水溶液)に
て銅層全体を02μmたけフラッシュエツチングし、初
めにマグネトロンスパッタリングで形成した銅層の不要
部分を完全に取り除いた。更に、60℃の無電解錫メッ
キ液(エンブレーh −T I N 421スペシヤル
 メルテックス社製)を用いて、銅回路表面に03〜0
6μmの錫メッキ層を設けると同局に、クロム層のエツ
チングを行なった。
Example 3 First, a 3n chromium layer was placed on the polyimide film (insulating layer).
A substrate for a flexible printed wiring board was prepared by forming a copper layer of 01 μm in thickness and a copper layer of 01 μm in thickness by magnetrin sputtering. A so-called reverse pattern that exposes the part of the copper layer of the board that will become the circuit of the desired pattern shape)
A photoresist was prepared, and copper plating was applied to the portions corresponding to the circuit by electrolytic copper plating until the total thickness was 10 μm. In Table 9, the photoresist was removed by 1≦ with acetone, and the entire copper layer was flash-etched to a depth of 02 μm using a copper etching solution (ferric chloride aqueous solution) at 40°C. Completely removed unnecessary parts. Furthermore, using an electroless tin plating solution (ENBLEH-TIN421 Special made by Meltex Co., Ltd.) at 60°C, 03 to 0 was applied to the surface of the copper circuit.
After a 6 μm tin plating layer was provided, a chromium layer was etched on the same surface.

そして、作製したフレキシブルプリント配線板サンプル
についてパターン間の絶縁抵抗(mを測定したところ、
下地層としてのクロム層を設けないもの(パターン寸法
等の仕様は実施例3に同じ)と同等の値を示した。
Then, the insulation resistance (m) between the patterns was measured for the prepared flexible printed wiring board sample.
It showed the same value as the one without the chromium layer as the base layer (specifications such as pattern dimensions are the same as in Example 3).

比較例 第2図(a)〜(d)は比較例による製造工程を模式的
に示した断面図である。
Comparative Example FIGS. 2(a) to 2(d) are cross-sectional views schematically showing manufacturing steps according to a comparative example.

ます、ポリイミドフィルム103(絶縁層)十にクロム
層3nm ]、 02及び銅層to/1m 101をマ
グネトロンスパッタリングにより形成ゼしめてフレキシ
ブルプリント配線板用の基板を作製し、第1図(a)の
ように、銅層101表面に所望のバタン形状のフォトレ
ジスト104を設けた。続いて、温度40℃の銅エツチ
ング液(塩化第2鉄水溶液)にて銅層10】をエツチン
グし、第1図(b)のように銅回路101aを形成した
。次に、アセトンによりフォトレジストを除去した後(
第1図(b) ) 、 40℃のクロムエツチング7夜
(フェリシアン化カリウム140gと水酸化す[・リウ
ム90gを水1000m11.:溶解させたもの)によ
り、第2図(C)のようにクロム層+02をエツチング
(銅回路10]aかエツチングレジストとなる)した。
First, a polyimide film 103 (insulating layer), a chromium layer 3 nm thick, 02, and a copper layer 1 m thick 101 were formed by magnetron sputtering to prepare a substrate for a flexible printed wiring board, as shown in Figure 1 (a). Next, a photoresist 104 having a desired batten shape was provided on the surface of the copper layer 101. Subsequently, the copper layer 10 was etched using a copper etching solution (ferric chloride aqueous solution) at a temperature of 40.degree. C. to form a copper circuit 101a as shown in FIG. 1(b). Then, after removing the photoresist by acetone (
Figure 1 (b)), chromium etching at 40°C for 7 nights (140 g of potassium ferricyanide and 90 g of hydroxide, dissolved in 1000 ml of water), the chromium layer was etched as shown in Figure 2 (C). +02 was etched (the copper circuit 10]a became an etching resist).

その後、60℃の無電解錫メッキ液(エンブレー1・T
lN421スペシヤル メルテックス社製)を用いて、
銅回路101a表面に0.3〜06μmの錫メツ穴層1
05を設り、第1図(d)のよう12フL・キシプルプ
リント配線板を得た。
After that, 60℃ electroless tin plating solution (ENBRAY 1・T
Using IN421 Special (manufactured by Meltex),
Tin hole layer 1 with a thickness of 0.3 to 06 μm on the surface of the copper circuit 101a
05 was installed, and a 12-frame L xyple printed wiring board as shown in FIG. 1(d) was obtained.

この比較例の方法は、−見、実施例の方法に比へC、ク
ロム層のエッヂング工程(第2図(C))が1丁゛稈増
えたたりのように見えるが、実際にはクロム層のエッヂ
ング工程に阻隔して水洗丁稈乾・繰下稈及び排水処理の
問題等かあり、本発明による製造jj法に比べて、生産
性・経済性の面で著しく劣るものである。
In the method of this comparative example, it appears that the chromium layer edging step (Fig. 2 (C)) is increased by one inch compared to the method of the example, but in reality, the chromium layer edging process (Fig. 2 (C)) is increased by one inch. In addition to the layer edging process, there are problems with washing and drying the culm, dropping the culm, and treating wastewater, making it significantly inferior in terms of productivity and economy compared to the production method according to the present invention.

なお、−17記の実施例では、フ:A]・レジストを用
いたフレキシフルプリント配線板の製造方法について説
明したか、本発明の方法はリジットプリント配線板にも
適用可能であることは言うまでもなく、パターン密度に
よっては印刷法等の方法で銅回路のエツチングレジスト
を形成してT)良い。
In addition, in the example described in -17, the method for manufacturing a flexible printed wiring board using a resist is explained, and it goes without saying that the method of the present invention can also be applied to a rigid printed wiring board. However, depending on the pattern density, an etching resist for the copper circuit may be formed by a method such as printing.

[発明の効果] 以上のJ:うに、本発明においては、無電解錫メッキ液
を用いてクロム層のエツチングと錫メッキを同時に行な
うので、製造工程の簡素化を図ることができるとともに
、クロム専用のエツチング液の排水処理に伴う環境汚染
等の問題も解消される。
[Effects of the Invention] Above J: In the present invention, etching and tin plating of the chromium layer are simultaneously performed using an electroless tin plating solution. Problems such as environmental pollution caused by wastewater treatment of etching solution can also be solved.

即ち、本発明によりは、クロム層−銅層一錫メッキ層の
積層構造をなす、;;j密度微細回路をイ]するプリン
ト配線板の製造におりる生産性・経済性の大幅な向上を
図ることかijJ能であり、例λはl−SI等を表面実
装する際に用いられるTAB(TapeautOmat
ed bonding)用のフレキシフルプリント配線
板を効率抑く製造することかできる。
That is, according to the present invention, it is possible to significantly improve the productivity and economy in manufacturing printed wiring boards that have a laminated structure of a chromium layer, a copper layer, and a tin plating layer. For example, λ is TAB (Tape Automat) used when surface mounting l-SI etc.
It is possible to efficiently manufacture a flexible printed wiring board for ED bonding.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a) −(c)は本発明第1実施例の製造−[
稈をね式的に示した断面図、第2図(a) = Cd)
 ill比較例の製造工程を扱式的jζ示した断面図で
ある。 [主要部分の符号の説明] 1・・・・・・銅層 1a・・・銅回路 2・・・・・・クロム層 3・・・・・・ポリイミドフィルム 4・・・・・・フォトレジスト 5・・・・・・錫メッキ層 】 2
FIGS. 1(a) to 1(c) show the manufacture of the first embodiment of the present invention.
A schematic cross-sectional view of the culm, Figure 2 (a) = Cd)
FIG. 3 is a cross-sectional view schematically showing the manufacturing process of a comparative example. [Explanation of symbols of main parts] 1... Copper layer 1a... Copper circuit 2... Chrome layer 3... Polyimide film 4... Photoresist 5...Tin plating layer] 2

Claims (1)

【特許請求の範囲】  クロム層−銅層−錫メッキ層の積層構造を有する回路
を絶縁層上に形成するプリント配線板の製造方法におい
て、 前記絶縁層表面に設けられたクロム層上に銅回路を形成
し、その後、無電解錫メッキ液を用いて、前記クロム層
の不要部分をエッチングにより除去すると同時に、前記
銅回路表面に錫メッキ層を設けることを特徴とするプリ
ント配線板の製造方法。
[Claims] A method for manufacturing a printed wiring board in which a circuit having a laminated structure of a chromium layer, a copper layer, and a tin plating layer is formed on an insulating layer, wherein a copper circuit is formed on a chromium layer provided on the surface of the insulating layer. , and then removing unnecessary portions of the chromium layer by etching using an electroless tin plating solution, and at the same time providing a tin plating layer on the surface of the copper circuit.
JP12127390A 1990-05-14 1990-05-14 Manufacture of printed wiring board Pending JPH0418789A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12127390A JPH0418789A (en) 1990-05-14 1990-05-14 Manufacture of printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12127390A JPH0418789A (en) 1990-05-14 1990-05-14 Manufacture of printed wiring board

Publications (1)

Publication Number Publication Date
JPH0418789A true JPH0418789A (en) 1992-01-22

Family

ID=14807174

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12127390A Pending JPH0418789A (en) 1990-05-14 1990-05-14 Manufacture of printed wiring board

Country Status (1)

Country Link
JP (1) JPH0418789A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100495184B1 (en) * 2002-12-02 2005-06-14 엘지마이크론 주식회사 A tape substrate and tin plating method of the tape substrate
KR100511965B1 (en) * 2002-12-13 2005-09-02 엘지전자 주식회사 A tin plating method of the tape substrate
EP1592290A1 (en) * 2004-04-30 2005-11-02 Nitto Denko Corporation Wired circuit board and production method thereof
US8100987B2 (en) 2004-03-16 2012-01-24 Jane D. Middleton Cleaning fluid and methods
US20170303404A1 (en) * 2016-04-13 2017-10-19 Shunsin Technology (Zhong Shan) Limited Manufacturing method for circuit board based on copper ceramic substrate

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100495184B1 (en) * 2002-12-02 2005-06-14 엘지마이크론 주식회사 A tape substrate and tin plating method of the tape substrate
KR100511965B1 (en) * 2002-12-13 2005-09-02 엘지전자 주식회사 A tin plating method of the tape substrate
US8100987B2 (en) 2004-03-16 2012-01-24 Jane D. Middleton Cleaning fluid and methods
EP1592290A1 (en) * 2004-04-30 2005-11-02 Nitto Denko Corporation Wired circuit board and production method thereof
US20170303404A1 (en) * 2016-04-13 2017-10-19 Shunsin Technology (Zhong Shan) Limited Manufacturing method for circuit board based on copper ceramic substrate
CN107295755A (en) * 2016-04-13 2017-10-24 讯芯电子科技(中山)有限公司 Manufacturing method of copper-clad ceramic substrate
US10383236B2 (en) * 2016-04-13 2019-08-13 Shunsin Technology (Zhong Shan) Limited Manufacturing method for circuit board based on copper ceramic substrate

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