JPH04192562A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To make a contact resistance small, to be hardly discontinued and to prevent a leakage current from being caused by providing the following: a contact layer which is composed of a metal, a specific metal alloy or a specific metal compound and whose orientation property is small; and an interconnection layer which has been formed on the contact layer and which is composed of a metal. CONSTITUTION:A contact window is opened on an n<+> type impurity region 12. For example, an a-Ge layer 14 as a conductive indeterminate-form layer is formed on a p- type silicon substrate 11 inside the contact window. For example, an alpha-W contact layer 15 as a contact layer whose orientation property is small is formed on the a-Ge layer 14 inside the contact window. An Al interconnection layer 16 which has been patterned to be a prescribed shape is formed on a silicon oxide film 13 and on the alpha-W contact layer 15; the film quality of the contact layer 15 is made highly dense; the resistance of the contact layer 15 is made small. Thereby, it is possible to obtain the interconnection layer whose contact resistance is small, which is hard to discontinue and which prevents a leakage current from being caused.

Description

[Detailed Description of the Invention] [Summary] Regarding the semiconductor device 1, an object of the present invention is to provide a semiconductor device having a wiring layer with low contact resistance, resistance to disconnection, and prevention of leakage current. From a group ■-■ group, group 11-V, or group ■ element formed on the base layer through a base layer made of metal and a contact window opened in an insulating layer provided on the base layer. a conductive amorphous film, a metal formed on the amorphous film, or a group III, IV spread or V
The contact layer has a low orientation contact layer made of a metal alloy or metal compound with a group element, and a wiring layer made of metal formed on the contact layer.

Further, a contact window formed on a base layer made of a semiconductor or metal and a contact window opened in an insulating layer provided on the base layer may be formed on the base layer. It is configured to have a conductive amorphous film made of a group (1) element, and a wiring layer with low orientation made of metal formed on the amorphous film.

[Industrial application fields] The present invention relates to a semiconductor device and a method for manufacturing the same.

Semiconductor devices in recent years are increasingly required to have high integration, high speed operation, and high reliability, as symbolized by VLSI devices. Therefore, in wiring technology for semiconductor devices, there is a need to further reduce the resistance of the wiring layer itself and the contact resistance, to prevent disconnection even at high current density, and to prevent or reduce leakage current.

[Prior Art] A conventional semiconductor device using AM aluminum as a wiring layer will be described with reference to FIG.

For example, an n-type impurity region 32 is formed on the surface of a p-type silicon substrate 31. Also, p-type silicon substrate 31
A silicon oxide film 33 is formed on the n+ type impurity region 32, and a contact window is opened on the n+ type impurity region 32. An Al wiring layer 34 is formed to connect to the n+ type impurity region 32 through this contact window.

However, in the conventional AI wiring described above, the aspect ratio of the contact window (the ratio of the depth of the contact window to the opening diameter) increases as semiconductor devices become smaller. For this reason, as shown in FIG. 5, insufficient coverage occurs at the step portion, and the Al wiring layer 34 may be locally thinned. Therefore, the current density increases in this thinned part, accelerating electromigration and increasing A.
This may cause disconnection of the l wiring layer 34.

In addition, AI in the A1 wiring layer 34 and St (silicon) in the n-type impurity region 32 locally react to generate alloy pits, and as a result, if the junction depth of the n+-type impurity region 32 is shallow, the junction Destruction may occur and leakage may occur.

In order to solve these problems, a wiring layer made of W (tungsten) is used instead of the A1 wiring layer, and a contact made of W, Ti (titanium), TiN (titanium nitride), etc. is used in the contact window. It has been proposed to reduce the aspect ratio of the contact window and to act as a barrier between the AI wiring layer and the underlying silicon layer by forming a layer.

For example, as shown in FIG.
W is deposited in the contact window on the n“ type impurity region 32 using the ical vapor deposition method.
A contact layer 35 is formed. Then, an Al wiring layer 36 is formed connected to this W contact layer 35.

In this way, by reducing the aspect ratio of the contact window with the W contact layer 35 and preventing local thinning of the Al wiring layer 36 formed through the contact window, occurrence of disconnection due to electromigration is prevented. It also serves as a barrier layer between the Al wiring layer 36 and the n-type impurity region 32 to suppress local reactions and prevent the generation of leakage current.

[Problems to be Solved by the Invention] However, the W contact layer 35 as shown in FIG.
There are also some problems with the wiring method using .

First, when growing the W contact layer 35 on the n-type impurity region 32 on the surface of the P-type silicon substrate 31, the so-called β-front is usually formed in a columnar shape due to the influence of the crystal lattice of the underlying Si.

For example, when the W contact layer 35 is grown using a reaction system of WF6-31H4-H2, W oriented in the plane spacing of the underlying Si, that is, β-front, may be formed. This is β
- This is because the front has the same structure as 81. Based on selected area X-ray diffraction images, the present inventor discovered that the W formed on the St substrate
It was confirmed that the contact layer 35 had an St orientation.

Further, β-pre is also generated on the p-type impurity region on the surface of the n-type silicon substrate.

When such a β-front is formed into a columnar structure, the entire W contact layer 35 becomes porous, so its resistance value is several to several tens of times higher than that of the so-called α-W, which has a small orientation. Become. Therefore, the W contact layer 35 made of β-front has a high resistance, and therefore becomes a cause of high contact resistance.

Furthermore, if the W contact j135 has a β-pre-columnar structure, the barrier property that suppresses the local reaction between the A1 wiring layer 36 and the n+ type impurity region 32 deteriorates, preventing the generation of leakage current. There was a problem that the effectiveness of the method was reduced.

Furthermore, since β-pre has an actual formation rate 3 to 5 times faster than α-W, it is difficult to control its film formation. Moreover, in actual film formation, α-W growth and β-pre-growth occur together, making it even more difficult to control the film formation. Therefore, there is a problem in that it is difficult to form the W contact layer 35 to a desired thickness with good controllability.

Furthermore, when forming the W contact layer 35, usually
This is carried out by a CVD method or the like using a metal halide, but at this time, the underlying Si is eroded, as shown by the reaction formula: 2WF6+3Si→2W3SiF4. Due to this erosion, if the junction depth of the n" type impurity region 32 is shallow, there is a problem that junction breakdown occurs and leakage current is generated.

The above-mentioned problems occur not only when the underlayer is made of a semiconductor such as Si, but also when it is made of a metal such as AI, if there are sites similar to the St coating surface. Moreover, the same thing occurs not only when the contact layer is made of W, but also when it is made of TiN, etc., for example.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a semiconductor device having a wiring layer that has low contact resistance, is less likely to be disconnected, and prevents leakage current, and a method for manufacturing the same.

[Means for solving the problem 1 The above problem is solved by forming a contact window formed on the base layer through a base layer made of a semiconductor or metal and a contact window opened in an insulating layer provided on the base layer. 1-IV group, ■-v
or a conductive amorphous film made of a group III or IV element, and a metal formed on the amorphous film, or a metal and a group III or IV element.
This is achieved by a semiconductor device characterized by having a contact layer with low orientation made of a metal alloy or metal compound with a group V element, and a wiring layer made of a metal formed on the contact layer. Ru.

In addition, through a base layer made of a semiconductor or metal and a contact window opened in an insulating layer provided on the base layer, This is achieved by a semiconductor device characterized by having a conductive amorphous film made of a group (1) element, and a wiring layer with low orientation made of a metal formed on the amorphous film.

Furthermore, the above-mentioned problem includes a step of forming an insulating layer on a base layer made of a semiconductor or a metal, and then opening a contact window in the insulating layer at a predetermined position; - a step of forming an electrically conductive amorphous film made of a group ■, a group ■-V, or a group A process of forming a contact layer made of a metal alloy or a metal compound with low orientation, and a process of depositing a metal layer on the entire surface and then patterning it into a predetermined shape to form a wiring layer connected to the contact layer. This is achieved by a method of manufacturing a semiconductor device characterized by the following.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the irregularly shaped film and the contact layer are sequentially and selectively formed on the base layer within the contact window. achieved by.

Further, in the above manufacturing method, after the irregularly shaped film, the contact layer and the wiring layer are sequentially formed on the entire surface, the laminated wiring layer, the contact layer and the irregularly shaped film are formed into a predetermined shape. This is achieved by a method for manufacturing a semiconductor device characterized by patterning.

Further, in the above manufacturing method, after forming the irregularly shaped film, the contact layer is continuously formed on the irregularly shaped film without exposing the irregularly shaped film to the atmosphere. This is achieved by the manufacturing method.

Furthermore, after forming an insulating layer on the base layer made of semiconductor or metal, a step of opening a contact window in the insulating layer at a predetermined position, and forming an I on the base layer in the contact window.
A step of forming a conductive amorphous film made of a group II-IV, group IV-V, or group II element, and a step of depositing a metal layer with a small orientation on the entire surface, and then patterning it into a predetermined shape to form the non-conductive film. This is achieved by the method of manufacturing a semiconductor device according to claim 2, further comprising the step of forming a wiring layer connected to the regular film.

The present invention is also achieved by the method of manufacturing a semiconductor device according to claim 2, characterized in that in the above manufacturing method, the amorphous film is selectively formed on the base layer within the contact window.

Further, in the above manufacturing method, the irregularly shaped film and the wiring layer are sequentially formed on the entire surface, and then the stacked wiring layer and the irregularly shaped film are patterned into a predetermined shape. This is achieved by the method for manufacturing a semiconductor device according to item 2.

The present invention is also achieved by the above-described manufacturing method of a semiconductor device, characterized in that the irregularly shaped film is selectively formed on the base layer within the contact window.

[Operation] That is, in the present invention, by providing an irregularly shaped film on the base layer, the contact layer formed on the irregularly shaped film can be formed as a layer with small orientation. Therefore, not only can this contact layer be grown with good control, but also the film quality of the contact layer can be made to have a high density. Thereby, the resistance of the contact layer can be reduced, and the barrier properties that prevent the reaction between the metal of the wiring layer and the underlying layer can be improved.

In addition, the presence of this contact layer makes it possible to reduce the aspect ratio of the contact window, which prevents local thinning of the wiring layer at stepped portions and prevents disconnections due to electro-microwave. I can do it.

Furthermore, in forming the contact layer, even if a metal halide is used, the presence of the amorphous film prevents the underlying layer from being eroded, thereby preventing the generation of leakage current due to erosion of the underlying layer. I can do it.

[Example] The present invention will be specifically described below based on an illustrative example.

FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

For example, a + type impurity region 1 with a junction depth Xj = 0.1 to 0.2 pm is formed on the (100) surface of a P- type silicon substrate 11.
2 is formed. Further, a silicon oxide film 13 is formed as an insulating layer on the p- type silicon substrate 11 and the n-type impurity region 12, and a contact window is opened on the n+-type impurity region 12.

On the p-type silicon substrate 11 within the contact window, a conductive amorphous layer having a thickness of 10 nm, for example, a-G
An e (amorphous germanium) layer 14 is formed. Also, a-G e M 14 in the contact window
For example, α-
A W contact layer 15 is formed. The thickness of this α-W contact layer 15 is arbitrary, but silicon oxide M1
It is desirable that the contact window be embedded with a thickness approximately equal to that of No. 3.

And silicon oxide Jl! 13 and the α-W contact layer 15, an AI wiring layer 16 patterned in a predetermined shape is formed, and the α-W contact layer 15 and the a-G
It is connected to the n-type impurity region 12 via eMl 14.

In this case, in order to improve the microclision resistance of the A1 wiring layer 16 or to prevent a direct reaction between the AI wiring layer 16 and the α-W contact layer 15 which is a metal layer below it, a layer made of TiN, for example, is used. A barrier metal layer may be provided between the AI wiring layer 16 and the α-W contact layer 15.

Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be explained using process diagrams in FIG. 2.

A junction depth X is formed on the (Zoo) surface of the P-type silicon substrate 11.
An n-type impurity region 12 with j=0.1 to 0.2 μm is formed. First, a silicon oxide film 1 as an insulating layer is placed on a p- type silicon substrate 11 and an n+ type impurity region 12.
form 3. Subsequently, the silicon oxide film 13 on the n+ type impurity region 12 is selectively etched to open a contact window 17 (see FIG. 2(a)).

Next, pretreatment cleaning of the surface of the n+ type impurity region 12 is performed. For example, after treatment with a 100:1 HF solution, plasma using a halide such as HF3 or F2 is used, or a temperature of 850°C and a pressure of 1 to 1
H under the conditions of 00 Torr and time of 5 to 10 m1n.
Dry cleaning is performed using a reduction reaction of 2 alone.

Next, using a multi-chamber growth apparatus equipped with a vacuum transfer system, the temperature was 260-360°C, the pressure was 0°01-1,
At 0 Torr, gas flow rate GeH4 = 5 cc/min and H
Under the condition of 2=500 cc/min, an a-00 layer 14 having a thickness of lQnm is selectively formed only on the nt type impurity region 12 within the contact window 17 (see FIG. 2(b)).

Next, the surface of the a-Ge layer 14 was heated at a temperature of 300° C. and a pressure of o, ooi to 0.1 ■Or, without exposing it to the atmosphere.
r, waste flow rate WF6/5iH4=IQ/7cc/mi
Depending on the condition of n, the a-Ge layer 14 within the contact window 17
An α-W contact layer 15 is selectively formed thereon. At this time, the thickness of the α-W contact layer 15 is controlled to such an extent that the contact window 17 is almost buried (see FIG. 2(C)).

Note that the source and
As the gas, W(Co)6 or CP2WH2 may be used instead of the above-mentioned WF6.

Furthermore, H2 (hydrogen) may be used as the atmospheric gas.

By the way, this α-W contact 1I 115 is grown using the a-00 layer 14 as an amorphous layer with an irregular lattice as a base, so it is not β-W but α-W contact 1I115 with a small orientation.
-W is formed. Therefore, this α-W contact layer 1
Since the growth rate of No. 5 is lower and more controllable than that of β-W, a desired film thickness can be easily obtained. Furthermore, since the film quality is higher than that of β-W, the specific resistance can be made several times smaller.

Furthermore, when an amorphous layer such as the a-00 layer 14 is exposed to the atmosphere, an oxide film with a lattice structure different from that of the underlying layer is formed on its surface, which affects the orientation of the metal layer to be formed on it. It may cause Therefore, as in this embodiment, a-
After forming the Ge layer 14, without exposing the P-type silicon substrate 11 to the atmosphere, α is deposited on the amorphous layer that is the a-G e layer 14.
- It is preferable to form a metal layer serving as the W contact layer 15.

The present inventor photographed an image of the α-W contact layer 15 using a selected area X-ray diffraction image, and confirmed that α=W indeed.

Further, at this time, a-G e is formed on the n-type impurity region 12.
Due to the presence of the layer 14, the WF6 does not react directly with Si in the n-type impurity region 12 as a metal halide, and therefore the surface of the nt-type impurity region 12 can be prevented from being eroded.

Next, after depositing an A1 layer over the entire surface, it is patterned into a predetermined shape to form an AI wiring layer 16 connected to the α-W contact layer 15 (see FIG. 2(d)).

At this time, since a high-density α-W contact layer 15 exists between the AI wiring layer 16 and the n-type impurity region 12, this α-W contact layer 15 acts as a barrier and This prevents local reactions between the layer 16+ and the n-type impurity region 12 from occurring.

In this way, according to the first embodiment, the nt type impurity region 1
By providing the a-Ge layer 14 as an amorphous layer having conductivity on the a-Ge layer 14, an α-W contact layer 15 as a contact layer with small orientation is formed on the a-Ge layer 14. be able to.

This α-W contact layer 15 is connected to the contact window 1.
By reducing the aspect ratio of 7, it is possible to prevent local thinning of the wiring layer at the stepped portion and prevent the occurrence of wire breakage due to electromigration.

In addition, since the α-W contact layer 15 is a high-density film with low orientation, it is possible to reduce the contact resistance and improve the barrier properties, so that the
A local reaction between I and St in the n-type impurity region 12 can be prevented, and leakage current due to junction breakdown in the n+-type impurity region 12 can be prevented from occurring.

Furthermore, even if a metal halide such as WF6 is used to form the α-W contact layer 15, since the a-Ge layer 14 exists on the n" type impurity region 12, the surface of the n+ type impurity region 12 is Erosion can be prevented, and therefore leakage current due to junction breakdown of the n+ type impurity region 12 due to this erosion can be prevented.

Next, the semiconductor device according to the second embodiment of the present invention was
This will be explained using the cross-sectional view shown in the figure.

For example, a silicon oxide film 22 as an insulating layer is formed on an AI layer 21 provided on a substrate (not shown), and a contact window is opened at a predetermined position. A Ge8 layer 23 having a thickness of 20 nm, for example, is formed as a conductive amorphous layer on the exposed AlN 21 in the contact window and on the top and side surfaces of the silicon oxide M22.

Further, on the Ge8 layer 23, a contact layer with a small orientation is formed, for example, γ-Ti2N or δ-T with a thickness of 30 nm.
A TiN contact layer 24 made of iN is formed. Furthermore, a W wiring layer 25 is formed on this TiN contact layer 24. These laminated W wiring layer 25, TiN contact layer 24, and Ge8 layer 23 are patterned into a predetermined wiring shape.

Next, a method for manufacturing the semiconductor device shown in FIG. 3 will be explained using the process diagram shown in FIG. 4.

After forming a silicon oxide film 22 as an insulating layer on an AI layer 21 provided on a substrate (not shown), the silicon oxide film 22 at a predetermined position is selectively etched to open a contact window 26. (See Figure 4(a)).

Next, using the same growth apparatus as in the first example, the temperature was increased to 3.
00~400°C1 Pressure 0°01~10■0"r H2
In the atmosphere, the waste flow rate GeH4/B2H6 = 10/10
Under the condition of cc/min, a Ge8 layer 23 with a thickness of 20 nm is formed on the entire surface as an amorphous layer having conductivity (see FIG. 4(b)).

Then, without exposing the substrate to the atmosphere, the temperature was increased to 400-500℃.
At 0°C, pressure 0, 1 to 10 Torr, waste flow rate T
Under the condition of iC14/NH3=5/30cc/min, a TiN contact layer 24 with a thickness of 30 nm is formed on the entire surface as a contact layer with low orientation (see FIG. 4(c)).

In addition, in forming the TiN contact layer 24, Cp2Ti(N3)2 may be used instead of the above-mentioned TiCl4, or P V D (Physical Vap
or Deposition) method may be used.

Next, after forming the W wiring layer 25 on the entire surface, the W wiring layer 2
5. Pattern the TiN contact layer 24 and the Ge8 layer 23 into a predetermined wiring shape (see FIG. 4(d)).

In this way, in the second embodiment, the Ge8 layer 23 is used as the amorphous layer having conductivity, and the TiN contact layer 24 is used as the contact layer with small orientation. In forming the contact layer 24, the W wiring layer 2 is grown after the entire surface is grown.
Although this embodiment differs from the selective growth of the first embodiment in that it is patterned into a predetermined wiring shape together with 5, it can basically achieve the same effects as the first embodiment.

In the second embodiment, the Si layer or the A1 layer is used as the base layer for the first X, but the present invention is also applicable to the case where a W layer, for example, is used as ρ1.

In addition, while the a-Ge layer 14 or the Ge8 layer 23 is used as the conductive amorphous film, it is not limited to the conductive amorphous film made of these group II or ■-■ group elements, for example, GeP
An electrically conductive amorphous film made of a TV-V group element such as a layer may also be used.

In addition, although the α-W contact layer 15 or the TiN contact layer 24 was used as a contact layer with small orientation, Ta (tantalum), Mo (molybdenum)
, AI, Cu (copper), Au (gold), or the like.

Note that when forming these as contact layers, the source gas is 1, for example 'T'aC15, Ta(C2
N5 ), Ta (N (CH3)2 >5; M
.

F6, MoF3, Mo(Co)5, Cp4M
oH; AlCl3, AI (CH3)2 H, AI
(CH3)3, AI (C2H5)3, A
I (C2H5)2H1AI (ic4H9)3
, AI (iC4H9)2H;Cu (HFA)
2, Cu (DPM)2; Au (HFA
)2, etc. may be used.

Further, when the contact layer and the wiring layer are made of the same material, for example, in the case of a combination of an α-W contact layer and a W wiring layer, there is no need to distinguish between them. Therefore, the group IV-IV, group IV-V-V,
Alternatively, a wiring layer with low orientation made of metal, which is the same material as the contact layer, may be directly formed on the conductive amorphous film made of a group Ⅰ element.

Effects of the Invention As described above, according to the present invention, by providing a conductive amorphous film and a contact layer with low orientation between the base layer and the wiring layer, the film quality of the contact layer can be improved to a high density. This makes it possible to reduce the resistance of the contact layer, improve the barrier properties that prevent reactions between the wiring layer and the underlying layer, and furthermore, reduce the aspect ratio of the contact window to reduce the resistance of the contact layer. Local thinning of the wiring layer can be prevented.

In addition, when forming a contact layer on an amorphous film, it is possible to grow a layer with small orientation easily and with good control. It is possible to prevent erosion of the strata.

As a result, contact resistance is low and wire breakage is less likely to occur.
Furthermore, it is possible to realize a wiring layer that prevents leakage from occurring.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a process diagram showing a method for manufacturing the semiconductor device of FIG. 1, and FIG. 3 is a second embodiment of the present invention. FIG. 4 is a process diagram showing a method for manufacturing the semiconductor device of FIG. 3, and FIGS. 5 and 6 are cross-sectional views showing a conventional semiconductor device. In the figure, 11.31...P-type silicon substrate, 12.3
2...n+ type impurity region, 13.22.33.
...Silicon oxide film, 14...a-Ge
Layer, 15...α-W contact layer, 16.34.3
6...AI wiring layer, 17.26...contact window, 21...A1 layer, 23...GeB layer, 24... TiN contact layer, 25...
・W wiring layer, 35...W contact layer. Applicant Fujitsu Ltd. Company Agent
First Embodiment of Patent Attorney Yoshi Kitano A cross-sectional view showing a semiconductor device layer. A cross-section showing the semiconductor device layer shown in Fig. 3;

Claims (1)

[Scope of Claims] 1. A base layer made of a semiconductor or a metal, and a III-IV group formed on the base layer through a contact window opened in an insulating layer provided on the base layer,
a conductive amorphous film made of a group IV-V element, or a group IV element, and a metal formed on the amorphous film, or a metal and a group III element;
1. A semiconductor device comprising: a contact layer with low orientation made of a metal alloy or metal compound with a group IV or V element; and a wiring layer made of metal formed on the contact layer. 2. A base layer made of a semiconductor or a metal, and a III-IV group formed on the base layer through a contact window opened in an insulating layer provided on the base layer,
1. A semiconductor device comprising: a conductive amorphous film made of a group IV-V or group IV element; and a wiring layer with low orientation made of a metal formed on the amorphous film. 3. After forming an insulating layer on a base layer made of semiconductor or metal, opening a contact window in the insulating layer at a predetermined position; IV
- forming an electrically conductive amorphous film made of a group V or group IV element, and forming a metal, or a metal alloy or metal compound of a metal and a group III, IV, or V element on the amorphous film; a step of forming a contact layer with low orientation consisting of a metal layer; and a step of depositing a metal layer over the entire surface and then patterning it into a predetermined shape to form a wiring layer connected to the contact layer. A method for manufacturing a semiconductor device according to claim 1. 4. The manufacturing method according to claim 3, wherein the amorphous film and the contact layer are sequentially and selectively formed on the base layer within the contact window. manufacturing method. 5. In the manufacturing method according to claim 3, after the irregularly shaped film, the contact layer, and the wiring layer are sequentially formed on the entire surface, the laminated wiring layer, the contact layer, and the irregularly shaped film are formed in a predetermined manner. 2. The method of manufacturing a semiconductor device according to claim 1, wherein patterning is performed in the shape of . 6. In the manufacturing method according to any one of claims 3 to 5, after forming the irregularly shaped film, the contact layer is continuously formed on the irregularly shaped film without exposing the irregularly shaped film to the atmosphere. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising: forming a semiconductor device. 7. After forming an insulating layer on a base layer made of semiconductor or metal, opening a contact window in the insulating layer at a predetermined position; IV
- A step of forming a conductive amorphous film made of a group V or IV element, and wiring that is connected to the amorphous film by patterning it into a predetermined shape after depositing a metal layer with low orientation on the entire surface. 3. The method of manufacturing a semiconductor device according to claim 2, further comprising the step of forming a layer. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the amorphous film is selectively formed on the base layer within the contact window. 9. The manufacturing method according to claim 7, wherein after the irregularly shaped film and the wiring layer are sequentially formed on the entire surface, the stacked wiring layer and the irregularly shaped film are patterned into a predetermined shape. 3. The method of manufacturing a semiconductor device according to claim 2. 10. The manufacturing method according to any one of claims 7 to 9, wherein after forming the irregularly shaped film, the wiring layer is continuously formed on the irregularly shaped film without exposing the irregularly shaped film to the atmosphere. 3. The method of manufacturing a semiconductor device according to claim 2, further comprising: forming a semiconductor device.