JPH04195572A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To match the characteristics of respective functional blocks with characteristics respectively required with a data bus by connecting a characteristic controlling capacitor corresponding to a selected functional block to the data bus through a switch circuit similarly corresponding to the block. CONSTITUTION:When any one of plural functional blocks 11 to 1n using the data bus 2 in common is selected, the characteristic control capacitor 5i corresponding to the selected functional block 1i is connected to the data bus 2 through the switch circuit 9i corresponding to the selected functional block 1i. Thus the characteristics of respective functional blocks 11 to 1n can be matched with respective characteristics required with the data bus 2.

Description

[Detailed Description of the Invention] [Summary] Regarding a semiconductor integrated circuit device having a plurality of functional blocks that share a data bus, each of the characteristics (AC standard) of the plurality of functional blocks is requested for the data bus. The purpose is to optimize and improve the characteristics by adjusting the characteristics of each functional block to the characteristics of the data bus for each functional block of the plurality of functional blocks. A capacitor for adjusting characteristics to match the characteristics required for the data bus, and a switch circuit for connecting the capacitor for adjusting the characteristics to the data bus are provided. When a functional block is selected, the capacity for characteristic adjustment provided corresponding to the selected functional block is
Similarly, the selected functional block is configured to be connected to the data bus via a switch circuit provided corresponding to the selected functional block.

[Industrial Field of Application] The present invention relates to a semiconductor integrated circuit device F (hereinafter referred to as LSI), which is provided with a plurality of functional blocks that share a data bus.

[Prior Art] Conventionally, an LSI of this type, the main part of which is shown in FIG. 4, has been proposed.

In the figure, 1. ~1fi is a functional block that each performs a certain function, 2 is a data bus, and 3 is a functional block 11~
AC standards that 1° has, that is, functional blocks 11~
The data bus The characteristic adjustment capacitor 4, ~4°, which is provided to match (adjust) the data delay time and data hold time required on the 2 side, is the functional block selection signal C81.
- C8o to the functional processors 211 to 1111, respectively. -1o are configured to be selected when the corresponding functional block selection signals C81 to C8, . However, selecting multiple functional blocks at the same time is prohibited.

[Problems to be Solved by the Invention] Here, the functional blocks 11 to 1fi do not necessarily have the same AC standard. Nevertheless,
In the conventional LSI shown in FIG.
The AC standards between all the functional blocks 11 to 1fi and the data bus 2 are matched. Therefore, even if it is possible to adapt the AC standards of some functional blocks to the data bus 2 side, the AC standards of all functional blocks 11 to 17 can be adapted to the data bus 2 side.
It is difficult to adjust to bus 2, and there are cases where there are functional blocks that are marginless.

FIG. 5 is a diagram for explaining such a problem. FIG. 5A shows a low active write enable signal, and the solid line in FIG. If not added, function block 1. The logical state of data bus 2 when is activated (data output),
That is, the AC standard of the functional block 11 is shown. Further, the solid line in FIG. 5C indicates the logical state of the data bus 2 when the functional block 12 operates (data output) when the capacitor 3 is not added to the data bus 2.
The AC standard of the functional block 12 is shown.

In this case, if the data bus 2 side requests a data delay time of T1 or less, and also requests a data hold time of 12 or more, the functional block 12 calculates the data delay time T1 or more. , is within time T1, and the data hold time T4 is longer than time 12, so this function block 1□
satisfies the AC standard required by the data bus 2 side.

On the other hand, in functional block 1, the data delay time T5 is within time T1, and in this respect it satisfies the request on the data bus 2 side, but the data hold time mT6 is within time 12. The request from the data bus 2 side is not satisfied. Therefore, in this case, the data of the functional block 11 cannot be handled effectively.

Therefore, conventionally, as shown in Figure 4, data
By adding a capacitor 3 to the bus 2 and extending the output data delay time, the data hold time is kept within the standard. In this case, the capacitance value of capacitor 3 was determined so as to match the standard value of the functional block, which is the worst for boat fishing, with the request on the data bus 2 side.

Here, the broken line in FIG. 5B shows the data when function block l operates when a capacitor 3 is added to data bus 2 to adapt the AC standard of function block 11 to the data bus 2 side.・The broken line in FIG. 5C shows the logic state of bus 2. Similarly, the broken line in FIG. The logic state of data bus 2 is shown when block 12 is activated. In this case, the AC standard of function block 1 can be adjusted to data bus 2, but
In No. 2, the data delay time is longer than the time T1, and the request on the data bus 2 side is not satisfied.

In this way, in the conventional LSI shown in FIG. 4, for some functional blocks, the AC standard is
Even if it can be adjusted to the bus 2 side, all functional blocks 11 to 1. Therefore, it is difficult to adapt the AC standard to the data bus 2, and there is a problem that some functional blocks may be marginless.

In view of this, the present invention provides an LSI that includes a plurality of functional blocks that share a data bus, and the characteristics of each functional block of the plurality of functional blocks are required for the data bus. LS that can be tailored to the characteristics and optimize and improve the characteristics.
The purpose is to provide I.

[Means for Solving the Problems] In the LSI according to the present invention, for an LSI having a plurality of functional blocks that share a data bus, the characteristics of each functional block are determined for each functional block of the plurality of functional blocks. A capacitor for adjusting the characteristics to match the characteristics required for the data bus, and a switch circuit for connecting the capacitor for adjusting the characteristics to the data bus are provided. When a functional block is selected, the characteristic adjustment capacitor provided corresponding to the selected functional block is connected to the capacitor provided corresponding to the selected functional block via the switch circuit provided corresponding to the selected functional block. It is configured to connect to a data bus.

[Operation] In the present invention, when any functional block is selected among a plurality of blocks that share a data bus, the capacity for characteristic adjustment provided corresponding to the selected functional block is are connected to the data bus via switch circuits provided corresponding to the selected functional blocks, so the characteristics of each functional block can be matched to the characteristics required for the data bus. I can do it.

[Embodiments] Various embodiments of the present invention will be described below with reference to FIGS. 1 to 3.

(1) Configuration FIG. 1 is a diagram showing the main parts of the first embodiment of the present invention,
In the figure, 51 to 5o are capacities, 6□ to 6fi are inverters,
7. ~7. ．． 81-8fi are transmission gates, and these inverters 61-6□ and transmission gates 71-7□, 81
Capacity 51-5. by ~8 fl. switch circuits 91-9. for connecting to data bus 2; , is configured. Other parts corresponding to those in FIG. 4 are given the same reference numerals.

Here, capacities 51 to 5 fl are functional blocks 1 and 5 fl, respectively.
~1°, and the capacitance value thereof is set to a value that optimizes matching of the AC standard with the data bus 2 for each of the functional blocks 11 to 1°.

In addition, since the switch circuits 91 to 9fi have the same configuration, the configuration and connection relationship with the capacitor 5I, the functional block selection signal transmission line 4, etc. will be explained below using the switch circuit 9□ as a representative. , First, the transmission gate 7 is connected to the data bus 2 at one end and connected to the capacitor 5 at the other end.
It is connected to one end of □ and one end of the transmission gate 81.

Further, the other ends of both the capacitor 51 and the transmission gate 8□ are grounded.

Further, the functional block selection signal transmission line 41 is connected to the gate of the pMOS 101 that constitutes the transmission gate 71 and the gate of nMO311+ that constitutes the transmission gate 81, and also constitutes the transmission gate 71 via the inverter 61. It is connected to the gate of the nMO812□ and the gate of the pMO3131 forming the transmission gate 81.

(2) Operation In the first embodiment, for example, when the functional block selection signals C81 to C81 are all at a high level "H", the transmission gates 71 to 7° are turned OFF, and the transmission gates 8 to 8fi are turned off. becomes ON. As a result, the capacity is 51
~5° is not connected to data bus 2.

On the other hand, for example, when the functional block selection signal C81 becomes low level "L" and the functional block 11 is selected, the transmission gate 71 is turned ON and the transmission gate 8□ is turned OFF.
Becomes FF. As a result, capacitor 5 is connected to data bus 2. Incidentally, when other functional blocks 12 to 1° are selected, the capacitors 52 to 511 are connected to the data node 2 in the same manner.

(3) Effect As described above, according to the first embodiment, when a certain functional block is selected by the functional block selection signals C3, to C3fi, the function block provided corresponding to the selected functional block is Since a capacitor having a capacitance value that optimizes the matching of the AC standard between this selected functional block and the data bus is connected to the data bus 2, all of the functional blocks 11-11 Therefore, it is possible to optimize the AC standard matching with the data bus 2 and improve the characteristics.

2 (2nd') (1) Configuration FIG. 2 is a diagram showing the main part of the second embodiment of the present invention,
In the figure, 14+ to 14. is the capacity, 15, ~15, is the inverter, 161~16. ．． 17□-17° are transmission gates, and these inverters 151-1511 and transmission gates 161-16. ．． 171-17. According to the capacity 14
1-14. Switch circuits 181 to 18° for connecting the data bus 2 to the data bus 2 are constructed. Other parts corresponding to those in FIG. 4 are given the same reference numerals.

Here, the capacity is 14□~14. , are functional blocks 1, to 1., respectively. The capacitance value is set to be a value that optimizes matching with the data bus 2 according to the hidden AC standard.

In addition, switch circuits 18□ to 18. have the same configuration, so the configuration, capacity 14□, functional block selection signal transmission line 4,
To explain the connection relationship with the transmission gate 16.
has one end connected to the data bus 2, and the other end connected to one end of the capacitor 141 and one end of the transmission gate 17□. Further, both the capacitor 14 and the transmission gate 171 have their other ends connected to the power supply line 20.

Further, the functional block selection signal transmission line 4. is connected to the gate of pMOS 21 + that constitutes the transmission gate 16□ and the gate of nMO322□ that constitutes the transmission gate 17t, and is connected via the inverter 151 to the gate of nMO8231 that constitutes the transmission gate 161 and the transmission gate. It is connected to the gate of pMO324□ which constitutes 17□.

(2) Operation In the second embodiment, for example, when all of the functional block selection signals C8l to C8 are at a high level "H", the transmission gates 161 to 16 are turned OFF, and the transmission gates 17□ to 17. .

becomes ON. As a result, capacitances 141-14° are not connected to data bus 2.

On the other hand, for example, when the functional block selection signal C5 becomes low level "L" and the functional block 11 is selected, the transmission gate 161 is turned on and the transmission gate 171 is turned on.
becomes OFF. As a result, capacitor 141 is connected to data bus 2 . In addition, other functional blocks 12 to II
The capacitance 14□ to 14. ,
is connected to the data bus 2.6 (3) Effects The second embodiment also provides the same effects as the first embodiment.

3.3. (1) Configuration FIG. 3 is a diagram showing the main parts of the third embodiment of the present invention,
In the figure, 25□~25Il, 26, ~26° are capacitances, 27
1~27 units are inverters, 281~28°, 291~2
9. ．． 301~30fi-31+~31. are transmission gates, and these inverters 271-27. and transmission gates 281-28fi, 291-29. -30+~30°, 311~311°, capacity 251~25. ．． 2
switch circuits 321 to 32 for connecting 6□ to 26□ to data bus 2; , is configured. Other parts corresponding to those in FIG. 4 are given the same reference numerals.

Here, the capacity is 251 to 25n, 26□ to 26. .

are provided corresponding to the functional blocks 11 to 1o, respectively, and their capacitance values are the same as those of the functional blocks 11 to 1o, respectively.
1. , is set to a value that optimizes matching of the AC standard with the data bus 2.

In addition, since the switch circuits 321 and 32° have the same configuration, the switch circuit 321 will be described below as a representative, and its configuration and connection relationship with the capacitances 25+ and 26□, the functional block selection signal transmission line 4, etc. To explain, first, one ends of the transmission gates 281 and 301 are connected to each other, and the midpoint of the connection is connected to the data bus 2. Further, the other end of the transmission gate 281 is connected to one end of the capacitor 251 and one end of the transmission gate 291, and the other ends of both the capacitor 251 and the transmission gate 21 are grounded. Further, the other end of the transmission gate 301 is connected to one end of the capacitor 26 and one end of the transmission gate 31, and the other ends of both the capacitor 261 and the transmission gate 311 are connected to the power supply line 20.

Further, the functional block selection signal transmission path 4□ is connected to the gate of the pM O8331 forming the transmission gate 281, the gate of the nMOS 34 I forming the transmission gate 281, the gate of the nMOS 34I forming the transmission gate 30. It is connected to the gate of the pMO 535□ forming the transmission gate 311 and the gate of the nMOS 361 forming the transmission gate 311, and via the inverter 271,
The gate of n M OS 371 which constitutes the transmission gate 28□, the p M OS 38 which constitutes the transmission gate 29°
1 gate, which constitutes the transmission gate 301
39 + gate, pM that constitutes the transmission gate 311
Connected to O540t(') gate.

(2) Operation In the third embodiment, for example, when all of the functional block selection signals C31 to C8 are at a high level "H", the transmission gates 28, to 28, and 301 to 30
fi is turned OFF, and transmission gates 291 to 29fi and 31 to 3111 are turned ON. As a result, the capacity is 251
~25°, 26, ~26. is not connected to data bus 2.

On the other hand, for example, when the functional block selection signal C8I is at a low level and the functional block 1□ is selected, the transmission gates 28+ and 30+ are turned ON and the transmission gates 29□ and 311 are turned OFF. As a result, the capacity is 25
1 and 26□ are connected to data bus 2. Note that other functional blocks 1□ to 1. If is selected, the capacity is 25□~25. ,．． 26□〜26. will be connected to data bus 2.

(3> Effects The third embodiment also provides the same effects as the first embodiment.

In addition, in the above-mentioned embodiment, the switch circuits 9□ to 9
Il, 18□~18ゎ, 321~32fi are controlled by function block selection signals C8l~csa,
Instead, the switch circuits 91 to 9°, 18, to 18 . l+3
It is also possible to control from 2+ to 3211.

[Effects of the Invention] According to the present invention, when any functional block is selected from a plurality of blocks that share a data bus,
A characteristic adjustment capacitor provided corresponding to the selected functional block is configured to be connected to the data bus via a switch circuit also provided corresponding to the selected functional block. By doing so, the characteristics of each functional block can be adjusted to the characteristics required for the data bus, so that the characteristics can be optimized and improved.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing the main part of the first embodiment of the present invention, Fig. 2 is a circuit diagram showing the main part of the second embodiment of the invention, and Fig. 3 is a circuit diagram showing the main part of the second embodiment of the invention. FIG. 4 is a circuit diagram showing the main parts of an example of a conventional LSI; FIG. 5 is a diagram for explaining the problems of the conventional LSI shown in FIG. 4. . (In Figures 1 to 3) 11-1. ...Functional block 2...Data bus 4, ~4U...Functional block selection signal transmission path C81~
C3fi...Functional block selection signal (in Fig. 1) 51-51...Capacity 91-9°...Switch circuit (in Fig. 2) 14□-14°...Capacity 181-18°. ... Switch circuit (in Fig. 3) 251-2511... Capacity 261-26. Capacity 321 to 3211...Switch circuit Main part of the first embodiment Fig. 1 Main part of the second embodiment Main part of the third embodiment Main part of conventional LSI Fig. 4 Problems will be explained. Diagram for Figure 5

Claims (1)

[Claims] A semiconductor integrated circuit device comprising a plurality of functional blocks sharing a common data bus, wherein characteristics of each functional block are required for the data bus for each functional block of the plurality of functional blocks. A capacitor for adjusting characteristics to match the characteristics and a switch circuit for connecting the capacitor for adjusting characteristics to the data bus are provided, and any one of the plurality of functional blocks is selected. In this case, a characteristic adjustment capacitor provided corresponding to the selected functional block is connected to the data bus via a switch circuit also provided corresponding to the selected functional block. A semiconductor integrated circuit device characterized in that it is configured as follows.