JPH04196341A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To separate and element excellently and finely by a method wherein a thick oxide film is formed on the upper end of a semiconductor substrate in contact with an element isolation region and then a region in the same conductivity as that of a semiconductor substrate but in the concentration about then times as high as that of the substrate is formed in a self-alignment manner. CONSTITUTION:After the formation of element isolating regions, the first channel stopper 104 is formed in a self-alignment manner on this element isolation end and then the second channel stopper 105 is additionally formed to enhance the element isolating characteristics. Accordingly, even if the electric field concentration occurs at the element isolation end due to the first channel stopper 104, the element isolating regions are hardly depleted thereby enabling a kink current to be avoided. Besides, the first channel stopper 104 formed after the selective oxidation is hardly affected by the thermal diffusion not to have an effect at all on a narrow channel MOS transistor. Furthermore, the extension of the depletion layer from the diffused layer can be restrained by the second channel stopper 105 thereby enabling an element to be finely isolated. Through these procedures, the element can be excellently isolated so that the fluctuation in the threshold voltage due to the difference in the channel width may be avoided.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for forming element isolation in a semiconductor device, and in particular to a method for manufacturing a semiconductor device that can suppress current caused by electric field concentration at the edge of an element isolation region. Regarding.

[Conventional technology]

Conventionally, LOGO3 (Loca
A selective oxidation method typified by 1 oxidation of 5 ilicon) is used. This will be explained in detail using FIG. 4.

First, in FIG. 4(a), for example, a silicon nitride film 302 is formed on a p-type semiconductor substrate 401 in a desired region that will become an active region, and then the exposed substrate region 403 is used as a mask.
An impurity to serve as a channel stopper is implanted by ion implantation or the like, and then (b) selective oxidation is performed to simultaneously form a field oxide film 404 and a channel stopper layer 405 in the element isolation region. After this, (c) a gate oxide film 406 and a gate electrode 407 were formed to form a MOS transistor.

In addition, in recent years, with the miniaturization of device dimensions, it has become a problem that the channel stopper layer described above also diffuses in the lateral direction due to thermal diffusion. Pages 532 to 535 (IEDM.

Technical Digest (1987) p p
532-535) [As described here, after performing selective oxidation for element isolation, a channel stopper layer was formed in the same manner.

This will be explained in detail using FIG. 5.

First, in FIG. 5(a), for example, a silicon nitride film 502 is formed on a p-type semiconductor substrate 501 in a desired region that will become an active region, and then (b) selective oxidation is performed using this as a mask to first form a field oxide film 503. After forming the channel stopper layer 504, (c) - the silicon nitride film is removed and impurities having the same conductivity type as the substrate are implanted into the entire surface by ion implantation or the like.
is formed. After this, (d) a gate oxide film 505 and a gate electrode 506 are formed to form a MOS transistor.
was forming.

[Problem to be solved by the invention]

The method for forming a channel stopper as shown in Figure 4 does not take into account that impurities implanted earlier during the formation of an oxide film in the element isolation region thermally diffuse, resulting in a narrowing of the effective channel width. Ta. As a result, the impurity concentration on the substrate surface becomes high at the edge of the element region, and as in Example 2 shown in FIG. 6, the threshold voltage of the channel becomes high when the field is narrow. Furthermore, as shown in FIG. 7, as the channel width becomes narrower, the threshold voltage rises more rapidly. Therefore, it has been difficult to achieve both a fine element region and an element isolation region.

Furthermore, in the method of forming a channel stopper as shown in FIG.
- It has excellent element isolation characteristics because it surrounds the source/drain diffusion layer of the transistor. However, the substrate concentration at the edge of the element region is lowered due to the accumulation of impurities during selective oxidation, and there is little change in the impurity concentration on the substrate surface side due to the formation of the channel stopper layer. Furthermore, as device dimensions become smaller, it is necessary to suppress the lateral extension (bird's beak) of the field oxide film during selective oxidation, which causes a local potential increase at the edge of the device region due to the influence of the electric field. . Therefore, in the gate voltage-drain current characteristics of the MOS transistor shown in FIG. 6, there arises a problem that an unnecessary current (king current) flows on the low voltage side of the gate voltage, as in Conventional Example 1, and the threshold voltage decreases. . Furthermore, as the channel width becomes narrower, the king current disappears, but the influence of the electric field is exerted from both sides of the device region, the potential on the substrate surface increases, and the threshold voltage further decreases, as shown in Figure 7. There was a problem.

Therefore, in both of the above, the threshold voltage changes with the channel width, which poses a problem in designing a circuit having a plurality of channel widths.

Furthermore, in a MOS memory such as a dynamic RAM or a static RAM, current consumption increases as the threshold voltage of a narrow channel element decreases. Furthermore, if the threshold voltage of the narrow channel element is increased to avoid this, the threshold voltage of the wide channel element also increases, resulting in an increase in circuit delay.

SUMMARY OF THE INVENTION An object of the present invention is to provide a manufacturing method capable of solving the above-mentioned problems and obtaining good and fine element isolation without changing the threshold voltage depending on the channel width.

[Means to solve the problem]

In order to solve the above problem, in the present invention, after forming the element isolation region, a first
form a channel stopper. In addition, a second channel stopper as shown in FIG. 3 is also added to improve element isolation characteristics.

[Effect]

In the present invention, even if electric field concentration occurs at the element isolation edge due to the first channel stopper, depletion is difficult to occur because the substrate concentration at the element region edge is high, and king current can be prevented. Furthermore, since the first channel stopper is formed after selective oxidation, it is less susceptible to thermal diffusion and does not affect the narrow channel MOS transistor.

Furthermore, the second channel stopper suppresses the extension of the depletion layer from the diffusion layer, resulting in fine element isolation.

These provide good element isolation that can prevent changes in threshold voltage due to differences in channel width.

〔Example〕

An embodiment of the present invention will be described with reference to FIG.

First, as shown in figure (a), for example, the impurity concentration is 1e1.
7/cs? After depositing a silicon nitride film 102, which is an oxidation-resistant insulating film, to a thickness of, for example, 200 nm on a p-type semiconductor substrate 101 of about 100 to 300 nm, a desired pattern is formed by lithography and etching to form an element isolation region. The p-type semiconductor substrate 101 is exposed.

Next, this p-type semiconductor substrate 101 is heated to a temperature of 1000 degrees Celsius, for example.
A thick oxide film 103 having a thickness of 400 nm, for example, is formed in the region not covered with the silicon nitride film 102 by performing thermal oxidation to a degree of zero, as shown in FIG. Next, BF2, which becomes an acceptor impurity, is implanted into this under, for example, condition 3.
0keV.

Ions are implanted obliquely at an angle of about 30 degrees using 2e13/a#, and the first
A channel stopper 104 is formed.

Next, as shown in the figure (c), after removing the silicon nitride film, B, which becomes the hair acceptor impurity of the p-type semiconductor substrate 101, is distributed so that the center of its distribution is directly under the thick oxide film 103 or shallower than it. For example, driving condition 150k
The second channel stopper 105 is formed by implanting over the entire surface at eV and 1e13/cn.

Thereafter, as shown in FIG. 3(d), a gate oxide film 107, a gate electrode 107, etc. are formed according to a conventional semiconductor manufacturing method.

According to this embodiment, the distribution of the channel stopper layer 104 can be controlled by changing the ion implantation angle and implantation energy.

Another embodiment of the present invention will be described with reference to FIG.

As in the first embodiment, first, as shown in FIG.
A silicon nitride film 202, which is an oxidation-resistant insulating film, is formed on 01.
After depositing a polycrystalline silicon film 203 to a thickness of 200 nm and 40 nm, respectively, by chemical vapor deposition, a desired pattern is formed by lithography and etching to expose a part of the p-type semiconductor substrate 201 in the element isolation region. Here, there is no problem even if the polycrystalline silicon film 203 on the silicon nitride film 202 is an oxide film.

Next, thermal oxidation is applied to this p-type semiconductor substrate 201,
A thick oxide film 205 having a thickness of 400 nm, for example, is formed in a region not covered with the silicon nitride film 202, as shown in FIG. At this time, since the polycrystalline silicon film 203 on the silicon nitride film 202 is also oxidized at the same time, an oxide film 204 is formed on the silicon nitride film 202.

Next, the silicon nitride film 202 is laterally recessed by about 50 nm on one side by isotropic dry etching using, for example, (CF4+02) as an etching gas. Note that in the thickness direction of the silicon nitride film, there is an oxide film 204 on top.
Because of this, etching can be prevented.

As a result, a part of the semiconductor substrate 201 is exposed around the thick oxide film 205, as shown in FIG. Next, after removing the oxide film 204 on the silicon nitride film 202 with a dilute aqueous solution of hydrofluoric acid, the thick oxide film 205 and the silicon nitride film 2 are removed.
Using 02 as a mask, ions of BF2 as an acceptor impurity are implanted under, for example, implantation conditions of 30 keV and 2e 13/a&, and the semiconductor substrate 201 at the edge of the thick oxide film 205 is
A first channel stopper 206 is formed in the exposed region.

According to this embodiment, unlike the first embodiment, oblique ion implantation is not required, so there is no restriction on the ion implantation apparatus.

In the above embodiment, the simplest selective oxidation method was used as the method for forming the element isolation region. However, other element isolation formation methods such as an improved selective oxidation method, trench type element isolation, etc. Adaptable.

Next, an example of groove type element isolation will be described using FIG.

First, as shown in (a), the substrate concentration is 1e17/a+
? A thermal oxide film 304 is formed to a thickness of about 20 nm on a P-type semiconductor substrate 301 of approximately 100 nm, and then a silicon nitride film 302 and an oxide film 303 are formed to a thickness of about 200 nm and 100 nm, respectively, by CVD.
rn is deposited and left in desired areas by known lamination and dry etching. Then, using these laminated films as a mask, a groove 305 with a depth of about 500 nm is formed in the semiconductor substrate as shown in FIG. Note that the grooves 305 may be formed all at once during the above laminated film processing. Next, a thermal oxide film 306 with a thickness of about 10 nm is formed on the side walls and bottom of the trench 305 by thermal oxidation. However, as shown in figure (c), after removing the oxide film at the bottom of the trench by anisotropic tri-etching, polycrystalline silicon, etc. is deposited inside the five trenches using known techniques such as selective growth and etchback. A conductive film 307 is embedded. At this time, the oxide film 303 is left on the silicon nitride film 302. After this, the silicon nitride film 302 is removed as shown in FIG.
Polycrystalline silicon 307 embedded in the trench using as a mask
is selectively oxidized to form a field oxide film 308 with a thickness of about 50 nm to 1100 nm. Furthermore, as shown in the figure (e), using the oxide film 303 as a mask, the silicon nitride film 302 is isotropically etched in the same manner as in the second embodiment, and is laterally recessed by about 50 nm on one side, and as shown in the figure (f). As shown, after removing the oxide film 303 with a hydrofluoric acid aqueous solution,
For example, apply BF2 at 50 keV to the entire surface.

Channel stopper layers 309 are formed at both ends of the element isolation region by performing ion implantation under conditions such as 1e13/d. At this time, since the element region is covered with a silicon nitride film, no channel stopper is formed.

Moreover, there is no problem even if the impurity for the channel stopper is implanted into the polycrystalline silicon film 307 in the element isolation region. Thereafter, the silicon nitride film 302 is removed using hot phosphoric acid or the like in the same manner as in the previous embodiment, and ions are implanted to form a channel stopper over the entire surface as shown in FIG. 3(g) to form a channel stopper layer 310. Further, in the MO5I-transistor, a gate oxide film 311 and a gate electrode 312 are formed by a known method.

According to the present invention, extremely fine element isolation can be realized, and the field oxide film in the element isolation region is 1100 nm thick.
Since the channel stopper 309 is relatively thin, electric field concentration at the edge of the device region can be alleviated, and the concentration of the channel stopper 309 can be lowered compared to other embodiments. Therefore, even if the channel width becomes narrow, the influence of the channel stopper 309 on the device characteristics can be reduced.

〔Effect of the invention〕

According to the present invention, it is possible to prevent kinging in the tail current of a MOS transistor, and it is also possible to suppress changes in threshold voltage due to element dimensions.
It becomes easy to design a circuit using MOS transistors with various element sizes. Furthermore, since a drop in threshold voltage in a microscopic element can be prevented, the off-state current of the MO5I-transistor can be reduced, and the current consumption of the integrated circuit can be reduced.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a cross-sectional view of the forming process showing the first embodiment of the present invention;
Figures 2 and 3 are cross-sectional views of the forming process showing other embodiments, Figures 4 and 5 are cross-sectional views of the conventional forming process, and Figures 6 and 7 are characteristic diagrams of the MOS transistor in the prior art. It is. 101.201...p-type semiconductor substrate, 102.2 (1
2...Silicon nitride film, 103,205...Field oxide film, 104,206...First channel stopper layer, 105,207...Second channel stopper 2m Revision 3 (XI 3011,, ,,,, Feel ■Attack 1 Eyes 3rd I
XJ3o3 312, Gate? Ii, polar shot 4H 407 gate? t1.4 6m Figure 7 Channel Convergence W

Claims (1)

[Claims] 1. In a device having a first conductivity type semiconductor substrate on which an element isolation region is formed, a thick oxide film for element isolation is formed at least on the upper end of the semiconductor substrate in contact with the element isolation region of the semiconductor substrate. 1. A method of manufacturing a semiconductor device, comprising forming a region having the same conductivity type as the semiconductor substrate and having a concentration about one order of magnitude higher than that of the substrate in a self-aligned manner after formation. 2. A method for manufacturing a semiconductor device according to claim 1, including the step of providing at least an oxidation-resistant film in a desired region that will become an active region on a semiconductor substrate of a first conductivity type, and the oxidation-resistant film. A step of forming a thick oxide film for device isolation in a self-aligned manner by selective oxidation in areas not covered by , forming a first conductivity type layer with an order of magnitude higher concentration on the upper part of the semiconductor substrate in contact with the element isolation region; and after removing the oxidation-resistant film, forming a first conductivity type layer in the element region and inside the semiconductor substrate in the element isolation region; A method of manufacturing a semiconductor device, comprising the step of implanting an impurity of one conductivity type. 3. A method for manufacturing a semiconductor device according to claim 1, including the step of providing at least an oxidation-resistant film in a desired region that will become an active region on a semiconductor substrate of a first conductivity type, and the oxidation-resistant film a step of forming a thick oxide film for device isolation in a self-aligned manner by selective oxidation in areas not covered by the oxidation-resistant film; a step of unilaterally scraping off the oxidation-resistant film to retreat laterally; and a step of implanting impurities of the first conductivity type using the thick oxide film as a mask to form a highly concentrated first conductivity type layer on the upper part of the semiconductor substrate in contact with the element isolation region;
A method for manufacturing a semiconductor device, comprising the step of, after removing the oxidation-resistant film, implanting an impurity of a first conductivity type into the semiconductor substrate in an element region and an element isolation region.