JPH04199331A - microcomputer - Google Patents

Abstract

PURPOSE:To support high function instruction without complicating hardware by providing a space for instruction emulation and switching an instruction area according to whether or not the fetched instruction is an emulation object instruction. CONSTITUTION:Spaces 40 and 50 for emulation instruction are provided separately from the other macroinstruction spaces 41 and 51, constructed so as to switch the instruction area according to whether or not the fetched instruction is the emulation object instruction. In short, an undefined instruction code in the existing instruction set is applied to allocate a code for emulation object instruction to this, an instruction line is arranged on emulation instruction spaces 40 and 50 so as to emulate the emulation object instruction with the instruction line included in the existing instruction set or the like. Therefore, the instruction executed by a normal mode and the emulation instruction executed by the emulation mode can be decoded by a common instruction decoder. Thus, the high function instruction can be supported with simple configuration.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a microcomputer that supports high-performance instructions similar to a Cl5C (complex instruction set computer) type microcomputer, and particularly to the architecture of its central processing unit. Regarding.

[Conventional technology]

In contrast to RISC (Reduced Instruction Set Computer) microcomputers, which have relatively simple instruction sets, Cl5C microcomputers have complex instruction sets and multiple addressing modes, making them highly functional. It is planned. Therefore, many instructions were executed in the form of microinstructions.

Nikkei Electronics (published on June 26, 1989)
No. 476) The microprocessor 1486 described on pages 117 to 130 can execute some instructions that can be executed in one clock at high speed by also using wired logic. ,
Most of the microinstructions corresponding to one clock instruction are generated, and the microinstructions can be directly generated without using the microcode ROM and sent to the control unit.

[Problem to be solved by the invention]

After studying the above-mentioned prior art, the present inventor found that: (1) the control path of [instruction decoder → control unit 1 - → execution unit] for clock instructions, and the control path of [micro code ROM → control unit] for other high-function instructions; Go to 1 → Execution unit”
control path is required.

As a result, it has become clear that the hardware configuration and control become complicated, and the chip size also increases.

An object of the present invention is to provide a microcomputer that can also support high-performance instructions with a relatively simple configuration.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, when configuring a microcomputer that emulates an instruction to be emulated as a predetermined instruction included in a macro instruction set with a sequence of emulation instructions as another macro instruction, the space for the emulation instruction is used as a space for other macro instructions. It is provided separately from the (non-emulation instruction) space, and is configured to switch and control the instruction space depending on whether or not the fetched instruction is an emulation target instruction.

The processing when switching the instruction space to transition from normal mode (operation mode in which data processing is performed in the space of non-emulation instructions) to emulation mode (operation mode in which data processing is performed in the space of emulation instructions) and returning to normal mode again. For simplicity, it is preferable to include a return instruction for restoring the instruction space in the emulation instruction sequence.

To avoid wasting unnecessary time saving the state of the program counter, etc. when switching the instruction space to ensure continuity of processing when switching from normal mode to emulation mode and then returning to normal mode. , a program counter, a condition code register, etc. may be provided separately for emulation instructions and other macro instructions, and these registers may be switched in synchronization with the switching of the instruction space.

Similarly, if it is necessary to guarantee the continuity of processing without taking the trouble of saving the state, and to increase the registers and work area required for high-performance processing by emulation, only the execution of emulation instructions can be performed. It is desirable to make available temporary registers available for additional use as resources for executing emulation instructions, and to separate data memory spaces for executing emulation instructions and for executing other macro instructions.

To make the operation code and immediate value of the corresponding emulation target instruction available for calculation processing to execute the emulation instruction,
It is preferable to provide an emulation instruction register that can receive and hold the fetched emulation target instructions and transfer all or part of the emulation target instructions held thereby to the arithmetic unit.

In order to easily obtain the start address of the emulation instruction string corresponding to the emulation target instruction, it is preferable to reflect all or part of the operation code in the emulation target instruction at the address.

When executing an instruction in multiple stages of pipeline processing such as instruction fetch, instruction decode, and instruction execution, when an instruction to be emulated is detected in an instruction decode cycle, the next instruction that has already been fetched is detected in a parallel instruction fetch cycle. In order to avoid the need to discard the next instruction, it is desirable to provide an instruction save register to save the next instruction.

[For production]

According to the above-mentioned means, an undefined instruction code in an existing instruction set such as a Cl5C type microcomputer is used, a code of an instruction to be emulated is assigned to it, and the instruction to be emulated is included in the existing instruction set. The instruction sequence is placed in the emulation instruction space so that it can be emulated with the instruction sequence.

Therefore, instructions executed in the normal mode and emulation instructions executed in the emulation mode can be decoded by a common instruction decoder, and a dedicated micro code F ROM is required for high-performance instructions such as the instructions to be emulated. No special provision is required.

〔Example〕

(Microcomputer Chip) FIG. 1 shows a microcomputer 1 according to an embodiment of the present invention.

This microcomputer 1 includes, but is not particularly limited to, a control unit 2 that performs control by fetching instructions, decoding instructions, generating signals, and various other controls, an arithmetic unit 3, a ROM 4 that stores operating programs, and a work area or temporary data storage area. It includes a RAM 5 serving as a storage area and a peripheral module 6, which are formed on one semiconductor substrate such as a silicone by known semiconductor integrated circuit manufacturing technology. This microcomputer 1 has a so-called Barbed architecture in which an instruction bus and an operand bus are separated. and ROM4, and is also connected to the operand address output bus DMA0UT and the operand data input bus DMDI.
N and an operand data output bus DMDOUT are connected to the arithmetic unit 3 and the RAM 5. Note that 7 is an external output circuit for memory access control signals, 8 is an external output circuit for address signals, 9 is an external input/output circuit for data, and 1o is an external input/output circuit connected to the peripheral module 6.

The microcomputer 1 of this embodiment realizes simple instructions using hard-wired logic, and complex high-function instructions by emulating a combination of these simple instructions. are native instructions, emulation target instructions, undefined instructions,
These instructions are classified into emulation instructions for emulating instructions to be emulated. For example, when comparing the existing instruction set of a Cl5C type microcomputer that has architecture common to the microcomputer 1 of this embodiment, the native instructions therein are mutually common, and undefined instruction codes in the instruction set are used. The code of the instruction to be emulated is then assigned to this, and the native instruction or the like is used as the emulation instruction.

The ROM4 is an empty space between the emulation ROM 4.0 and the user ROM4, and the emulation ROM 4.0 and the user ROM4 are empty spaces.
The M40 is a storage area for an operating program made up of emulation instructions, and the user ROM 41 is used as a storage area for an operating program made up of native instructions and emulation target instructions. Switching between the instruction spaces of the emulation ROM 4.0 and the user ROM 41 is controlled by a control signal φ■ output from the control unit 2, and when the control unit 2 decodes the fetched instruction, it detects that the instruction is an emulation target instruction. Then, at a predetermined timing, the instruction space is switched from the user ROM4.1 to the emulation R.0M40.

The RAM 5 is an emulation RAM 50 and a user R
Space divided into AM51, emulation RAM50
is a work area dedicated to executing emulation instructions, and the user RAM 51 is a work area used for executing native instructions and emulation target instructions.

Switching between the emulation RAM 50 and the user RAM 51 is controlled by a control signal φD output from the control unit 2, and when the control unit 2 detects that the fetched instruction is an emulation target instruction in the decoding operation of the fetched instruction, a predetermined The space is switched from the user RAM 51 to the emulation RAM 50 at the timing of .

(Central Processing Unit) FIG. 2 shows a detailed example of the control section 2 and calculation section 3.

In the figure, IRQ to IR5 are instruction registers, and when instructions are executed in a multistage pipeline, the instructions are sequentially shifted and transmitted to subsequent stages according to the operation cycle. D E CF.

DECA, DECD, and DECM are instruction decoders for generating control signals by decoding instructions supplied from the corresponding instruction registers, etc., and the instruction decoder DECF fully decodes all fields of the instruction and outputs the instructions. and generates control signals for basic operations according to the determined type.

The instruction decoder DECA generates operation control signals for arithmetic logical operations, arithmetic operations, etc., and control signals for data transfer. The instruction decoder DECD generates control signals for memory (RAM) access. Instruction decoder DEC
M generates control signals for multiplication. Control circuit C0N
T performs pipeline control, exception handling control, scoreboard control, register selection control, and the like. Tag registers TAG1 to TAG5 have instruction decoders DECF.
Predetermined information obtained by full decoding is retained,
It is supplied to instruction decoders DECA, DECD, and DECM. For example, it holds information regarding the type of instruction, such as whether it is an emulation target instruction, and information such as whether memory access is required and whether multiplication by 1 is to be performed.

The control signal φ■ for the space switching is outputted via the instruction decoder DECF and the latch LATI. When the instruction decoder DECF detects that the operation code of the instruction supplied to it is an instruction to be emulated, it inverts the level of the control signal φ■ and decodes the ROM.
4 instruction space is switched to emulation ROM 4.0. Further, the control signal φD is outputted via the instruction decoder DECD and the latch LATD. Instruction decoder DE
When the CD detects that the instruction is an emulation target instruction from the operation code of the instruction supplied to it or the information supplied from the tag register TAG2, it inverts the level of the control signal φD and transfers the space of the RAM 5 to the emulation RAM 50. Switch.

There are no particular restrictions on returning the ROM4 or RAM5 from the emulation space to the normal space, but the instruction decoder DECF detects an RTE (return) command included in the emulation command sequence, inverts the control signal φI, and returns R, This is realized by inverting the control signal φD by detecting the decoding result of the TE instruction by the decoder DECD via the tag register TAG2.

The start address of the emulation instruction string corresponding to the emulation target instruction is generated by an instruction decoder DECF or the like using all or part of the operation code in the emulation target instruction.

Immediate 1 to values of the instructions fetched into instruction register IRQ are supplied to immediacy 1 to register IMM through sign extension and decoding logic DEC8, and are subjected to calculations by arithmetic operation unit ATJ and the like.

The EIR is an emulation instruction register that receives and holds the emulation target instruction from the instruction register IRQ, and allows all or part of the emulation target instructions held by the EIR to be transferred to the arithmetic unit.

IRB is an instruction save register, and when executing an instruction in multiple stages of pipeline processing such as instruction fetch, instruction decode, and instruction execution, the instruction decoder DEC
When an instruction to be emulated is detected in the instruction lever-1 cycle by F, this function is used to save the next instruction that has already been fetched into the instance 1 lag register IRQ in the parallel instruction fetch cycle so that it does not have to be discarded. This is a backup instruction register. The instructions backed up in the instruction save register IRB are transferred to the instruction register IRQ again when execution of a predetermined emulation instruction sequence is completed.

Although the program counter holding the next instruction address to be fetched is not particularly limited, it has a four-stage configuration, and includes program counters PCEMO, PCEMI, and PCEMO, PCEMI, and PCEMI for emulation instructions held in the emulation ROM 40.
CEM2. PCEM3 and program counters PCO, PCI, PC2, and Pc3 for native instructions and emulation target instructions held in user ROM 41 are each individualized. Program counter is serial 4
The reason for the staged configuration is to hold the address of instructions fetched in the past in relation to pipeline processing and make it available when one exception handling occurs. The pcpc is used to hold branch destination addresses for conditional branches in advance so that one branch processing can be performed quickly. Further, EXAR is a register that holds an instruction address for exception processing.

The condition knee 1 to registers are also separated into a register CCRE M for emulation instructions and a register CCR for native instructions and emulation target instructions, and are switched between normal mode and emulation mode, similar to the program counter.

The general-purpose registers are RO to R7, and additionally, temporary emulation registers T1 to T3 are provided exclusively for emulation instructions.

In addition, LATCH is the latch circuit of the arithmetic operation unit AU, SP is the stack pointer register, FP is the frame pointer that holds the base address for acquiring automatic variables during a procedure call, and A is the arithmetic logic operation unit AL.
One input register of U, B is the other input register of arithmetic logic unit ALU, C1 and C2 are arithmetic logic unit A
The LU output value holding register, MAR, is an address register used for bus error processing.MDRIN is a data register that temporarily holds data supplied from the operand data input bus DMDIN.
OUT is a data register that temporarily holds data to be output to the operand data output bus DMDOUT;
ULT is a multiplier, MULI and MUL2 are multipliers MUL
This is the input register of T.

(Instruction Format) FIG. 3 shows the basic form of the instruction format. In the figure, X describes an operation code corresponding to the type of instruction. A code for specifying a source register is written in Rs, and a code for specifying a destination register is written in Rd. 1.
m m describes an immediate value, and CC in the branch format means a condition code that is a condition for branching.

Figure 4 shows instruction cells 1 to 2 of the [2 register format].
An example of instructions included in rMOV.

L”, rLOAD, LJ, rsTORE, LJ, rMO
,V,BJ,rBRA32J,rRTE'',rADDL
I ST, LJ are shown. Among the instructions shown here, the ADDLIST and L instructions are considered to be one of the emulation target instructions. The RTE command is a command for returning from emulation mode to normal mode.

In FIG. 5, r S HLA,LJ is shown as an example of the "Logistor and 4-pit horizontal format" command.

FIG. 6 shows rDc as an example of the "Luzister and 8-pit imizoid format" command.

NVJ is shown. This instruction rDcONVJ is one of the emulation target instructions.

The register specification fields Rs and Rd in the various instruction formats are each 4 bits, and the source register specification field Rs and data ' in the normal mode are 4 bits each.
The value of the staycation register specification field Rd,
The relationship with the registers specified thereby is shown below.

Specified field value Specified register 0000 →
RO 0001→ R1 0010→ R2 0011→ R3 0100→ R4 0101→ R5 01,10-) R6 0111→ R7 1000 to 1111 → Register specification field FRs in invalid normal mode,
If a value of 1000-11.11 is written in Rd, illegal instruction exception handling is performed.

When the microcomputer 1 is in emulation mode, the register designation field Rs.

The values of Rd from oooo to 0111 are the same as those in normal mode, but values from 1000 to 1111 have a new meaning of specifying registers in the following manner.

The following specification mode is substantially effective in emulation instructions.

Specified field value Specified register 1000 →
T1 1001 → T2 1010 → T3 1011 → EIR 1100-+ R5 1101 → Rd 1110 → Unused 1111 → Unused In the above register specification mode, the values 1000 to 1011 are specified as temporary register T1, temporary register T2, temporary register This is specified by T3 or emulation instruction register EIR. That is, such registers Tl, T2 . T3. The EIR is additionally made available as a dedicated resource when executing emulation instructions.

In addition, in the above register specification mode, 1100-+
If the value of the register specification field Rs of the emulation instruction is 1100, Rs is the register specification field R of the emulation target instruction corresponding to the instruction.
It has the meaning of specifying the register specified by s. Similarly, 1101→Rd has the meaning that if the value of the register specification field Rd of the emulation instruction is 1101, the register specified in the register specification field Rd of the emulation target instruction corresponding to the instruction is specified. By adopting such a register specification method, it becomes possible for the emulation instruction to access the register specified by the emulation target instruction.

(ADDL I ST, L instruction) As an example of an emulation target instruction, ADDL
The IST and L commands will be explained.

This ADDLIST, L instruction has a format as shown in FIG. 4, and as shown in FIG. Processing is performed to add the En1 edge pointed to by the field Rs.

This instruction is an emulation target instruction, and is realized by five emulation instructions EO to E4 shown below.

EO; LOAD, L @Rs, TIEl; 5
TORE, L Rd, @RsE2; MOV, L
Rs, RdE3; LOAD, L Tl,
RsE4; RTE FIG. 8 shows a specific example of the emulation command format constituting the emulation routine.

This emulation routine is ADDLIST,L
Load the data at the address held by the register specified by the register specification field Rs of the instruction into the temporary register T1 and save it (EO), ADDLIS
Store the value of the register specified by the register specification field Rd of the T, L instruction in the address held by the register specified by the register specification field R, s of the ADDLIST, L instruction.
The data at the address held by the register specified by the register specification field Rs of the IST, L instruction is transferred to the register specification field R of the ADDLIST, L instruction.
To transfer the value of temporary register T1 to the address held by the register specified by d (E2), ADD
The data is stored in the register designated by the register designation field Rs of the LIST and L instructions (E3), and finally the process returns to the normal mode [E4].

The emulation instruction EO-E4 constituting the emulation routine is stored in the emulation instruction space, that is, the emulation ROM 40, and is stored at the base address (emulation vector base address) EVBA of the vector table in the emulation instruction space.
The address obtained by adding the entry address output from the instruction decoder DECF corresponding to the operation code of the ADDLIST and L instructions, for example, EVBA+64 (decimal) address, is placed at the beginning.

FIG. 9 shows an example of the execution flow of the ADDLIST and L instructions and the corresponding emulation instructions. When the ADDLTST and L instructions are detected during the normal mode in which instructions are fetched from the instruction space of the user ROM 41 and processed, the emulation mode is switched to an emulation mode in which instructions are fetched from the instruction space of the emulation ROM 40 and processing is proceeded. By switching this mode,
The ADDLIST, L instruction decodes the operation code and the emulation vector base.
This is realized by the emulation instructions EO to E4 starting from the address determined by the address EVBA, and the mode is returned to the normal mode, and the instructions following the ADDLIST and L instructions are executed in the space of the user ROM 41.

FIG. 10 shows an example of a five-stage pipeline operation flow when the ADDLIST and L instructions are implemented by emulation.

First, the 5-stage pipeline starts with instruction fetch (IF
), instruction decode (ID), instruction execution (EX), data memory access (MEM), instruction execution result write (
It is assumed that each processing cycle of WB) is performed while being shifted by one cycle for each instruction. For example, as represented by the processing content of instruction N2, in an instruction fetch cycle in a native instruction, the user ROM 41 is accessed according to the value of the program counter PCO to fetch an instruction. In the instruction decode cycle, the fetched instruction is decoded by the decoder DECF to generate a control signal, and the value of the program counter PCO is incremented. In the instruction execution cycle, calculations are performed by operations such as an arithmetic logic unit ALU. In the data memory access cycle, the user RAM 51 is accessed. The spaces of RAM5 and ROM4 that are accessed when executing this native instruction are controlled by control signals φ■ and φD.
1) are selected. In the write cycle of the instruction execution result, the result is stored in a predetermined register or the like.

AD at instruction decode cycle T3 of native instruction N3
When the DLIST, L instruction is detected by the instruction decoder DECF, in the instruction decoding cycle T3, the control signal φ■ is inverted to control switching of the instruction space from the user ROM 4.1 to the emulation ROM 40.
Emulation vector base
Add address EVBA and emulation instruction E
Obtain the address of O and store it in the program counter PCEMO for emulation. Then, program counters PCO to PC3 are replaced by program counters PCEMO to PC3 for emulation.
, switch control to 3 to make it work. Furthermore, A
DDL I ST.

Control is performed to suppress or cancel the next instruction N4, which is fetched in parallel with the decode cycle T3 of the L instruction, from that decode cycle onwards.

In cycle T4 of the ADDLIST and L instructions, the condition code register is switched from CCR to CCREM exclusively for emulation. Furthermore, the instruction N4 held by the instruction register IRQ is saved in the instruction register IRB, and is made available immediately after emulation ends.

In cycle T5 of the ADDLIST, L instruction.

By inverting the control signal φD, the data memory space is
Switch from AM51 to emulation RAM50. This data space switching timing is performed in synchronization with the timing assigned to data memory access (MEM) in pipeline processing, so ADD
Access to the RAM 5 in instructions before the LIST and L instructions is always performed in normal space.

In cycles T4 to T7, emulation instructions EO-E3 are sequentially fetched from the emulation ROM 40 to the instruction register IRQ according to the value of the program counter PCEM0 and executed. Data memory access at this time is performed with respect to the emulation RAM 50 whose space has already been switched.

Emulation instruction E fetched in cycle T8
4 is decoded in cycle T9 and determined to be an RTE instruction, the instruction space is transferred to the emulation RO
Switch from M4.0 to user ROM 41, and switch the program counter from PCEM to PC. ,
Furthermore, the instruction N4 saved in the instruction register IRB is transferred to the instruction register IRQ.
Transfer to. Therefore, in the same cycle T9, RO
The instruction fetched from M4 is substantially invalidated, and the instruction N4 suppressed from cycle T4 to T7 is
It is made executable immediately after that.

After that, instruction fetches are performed in normal space.

In cycle Tll of the RTE instruction, the RAM 5 is switched from the emulation RAM 50 to the user RAM 51, and data memory access for subsequent instructions is performed in normal space.

(DCONV Instruction) Next, the DCONV instruction will be explained as another emulation target instruction.

FIG. 11 shows the detailed instruction format of the DCONV instruction. This instruction converts the contents of the register specified by the register specification field Rs in accordance with the contents of the conversion type specification fields TB and TA, and returns the result to the original register.

Conversion type specification field TB (1'ype
Before) indicates the data type before execution of the instruction, and the conversion type specification field TA (TypeAf
ter) indicates the data type after execution of the instruction.

The relationship between the value of the conversion type designation field and the data type is as follows.

oooo; Signed byte integer (lower 8 digits valid) 0001; Signed word integer (lower 16 digits valid) 0010; Signed longword integer (all 32 digits valid) 0011; Signed extent integer (next register join, 64 digits valid) 0100; Unsigned byte integer (lower 8 digits valid) 0101; Unsigned word integer (lower 16 digits valid) 0 ], 10; Unsigned longword integer (32 digits all bits valid) 0111; Signed extent Integer (next register combination, 64 digits valid) 1000; IEEE single precision floating point number (32 digits valid) 1001; IEEE double precision floating point number (64 digits valid)
1010; IEEE extended double-precision floating point number (
80 digits valid) 1011; undefined 1100; BCD integer (8 digits decimal) 1101; BC
D integer (16 decimal digits) 1110; undefined 1111; undefined Because the data format conversion supported by this DCONV instruction involves complex processing, conditional branching is used in the emulation to implement this instruction. There is.

In this conditional branch, the conversion type specification field TB of the DC○NV instruction.

Next, an outline of the process of extracting a TA and reflecting it in the offset of the branch destination address will be explained.

For example, the value of the conversion type specification field TB indicating the data type before instruction execution is rooo.

(signed pi 1 to integer)", and the value of the conversion type designation field TA indicating the data type after execution of the instruction is "rollo (unsigned longword integer)".

As shown in FIG. 12, when the DCONV instruction is fetched between the user ROMs 412G, the instruction space is switched to the emulation ROM 4.0, and the DC
The emulation ROM 40 is accessed by the address obtained by reflecting the instruction decoding result of the ONV instruction, and an emulation routine starting with the emulation instruction EO is started. The emulation routine according to this example uses the emulation instruction EO
After executing E3 from , a conditional branch is made to a routine starting with emulation instruction E8 according to the contents of the conversion, and finally an RTE instruction is executed with emulation instruction Ej to return to normal space again.

That is, (EO; MOV, L ERI, T2) DCONV held in emulation instruction register EIR via instruction register IRQ
The instruction is transferred to the temporary register T2, and (El; MOV, BT2.T2) all 8-bit values of the conversion type specification fields TB and TA of the DCONV instruction stored in the temporary register 1-2 are transferred to the same temporary register. Cut out by T2.

(E2; 5HLA, L T2. #3) The value cut out to temporary register T2 is shifted by 3 bits, and (E3; BRA32 T2) The value of temporary register゛2 is added to the value of program counter PCEM. Branches to address emulation instruction E8, (E8 to Ei) 1) Compares the value of the register specified by the register specification field Rs of the CON V instruction from a signed pi 1 to integer to an unsigned longword integer. Processing is performed, (Ej; RTE) Finally, RTE is executed and the instruction space is transferred to user ROM4.
Can be switched to 1 space.

According to the above embodiment, there are the following effects.

(1) AD that cannot be executed in one operation cycle
When realizing high-performance instructions such as DLIST, L instructions, and DCONV instructions by emulation, undefined instruction codes in the existing instruction set of the Cl5C microcomputer are used, and the codes of the instructions to be emulated are assigned to them. In order to be able to emulate an instruction to be emulated with an instruction string included in the existing instruction set, the instruction string is arranged in the emulation ROM 40 as an emulation instruction space. The emulation instruction space is arranged in a separate space from the user ROM 41, which is an instruction space that does not require emulation, and the instruction space is switched depending on whether the fetched instruction is an instruction to be emulated. Therefore, instructions executed in normal mode and emulation instructions executed in emulation mode can be decoded by a common instruction decoder such as a decoder DECF, and a dedicated microcode is used for high-function instructions such as instructions to be emulated. There is no need to provide a special ROM. As a result, a microcomputer that supports high-performance instructions can be obtained without complicating the hardware or increasing the chip size.

(2) By having a separate space for instruction emulation, emulation can be performed without changing the vector handler of the operating system in relation to an existing Cl5C type microcomputer that utilizes the instruction set.

It can support high-performance instructions while ensuring compatibility with conventional software.

(3) By executing the RTE command included in the emulation command sequence and realizing the process of transitioning from normal mode to emulation mode and then returning to normal mode, the process can be simplified.

(4) Program counters are provided separately for emulation instructions PCEMO to PCEM3 and other macro instructions PCO to PCEM3, and a condition code register is similarly provided for emulation instructions CC
By providing separate registers for RE M and CCR for other macro instructions, and controlling switching of these registers in synchronization with the switching of the instruction space, the instruction space can be switched from normal mode to emulation mode and back to normal mode. When ensuring continuity of processing when returning to the mode, there is no need to spend extra time saving the state of the program counter, etc., and most of the processing for saving the state can also be omitted.

, (5) Temporary registers T1 to T3 that can only be used to execute emulation instructions can be additionally used as resources for executing emulation instructions, and data memory space can also be used for executing emulation instructions (emulation RAM 50) and other macro instructions. By having separate memory for execution (user RAM 51), continuity of processing can be guaranteed without the hassle of saving the state, and the registers and work area necessary for high-performance processing through emulation can also be secured. can be made larger.

(6) Emulation instruction register E that receives and holds the fetched emulation target instructions and can transfer all or part of the emulation target instructions held thereby to the calculation unit 3
By providing the IR, it is possible to use the operation code and values of the corresponding emulation target instruction in the arithmetic processing for executing the emulation instruction.

(7) By reflecting all or part of the operation code in the emulation target instruction to the first address of the emulation instruction sequence, the address can be obtained in a short time by simple processing using the instruction decode cycle. become.

(8) When executing an instruction in multiple stages of pipeline processing such as instruction fetch, instruction decoding, and instruction execution, when an instruction to be emulated is detected in instruction lever-1 to cycle, instruction pheno-9 cycles parallel to the error are detected. An instruction save register IRB is provided to save the next instruction that has already been fetched into the instruction register IRQ.
By returning the value of the register IRB to the instruction register IRQ when the 'E instruction is executed, the efficiency of the instruction execution operation can be improved.

Although the invention made by the present inventor has been specifically explained based on examples, the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof.

For example, the emulation target instruction is the AD of the above embodiment.
The instruction is not limited to the DLIST, L instruction, or DCONV instruction, but can be set as any other instruction that requires a relatively large number of processing steps. Furthermore, the instruction format and instruction type are not limited to the above embodiments and can be changed as appropriate.

The number of serial stages of instruction registers and the number of serial stages of program counters can be changed depending on the functions of the microcomputer. Furthermore, the type of built-in arithmetic unit and the configuration of the internal bus are not limited to the above embodiments.

In the above explanation, the invention made by the present inventor will be mainly explained based on the field of application which is the background of the invention, such as RA, M, RO.
Although the case where the present invention is applied to a microcomputer with built-in peripheral modules on one chip has been described, the present invention is not limited thereto, and can also be applied to microcomputers in which RAM, ROM, and peripheral modules are not integrated on a chip. Widely applicable. The present invention can be applied at least to conditions where high-performance instructions are realized by emulation.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, when realizing high-performance instructions by emulation, a separate instruction emulation space is provided, and the instruction space is switched and controlled depending on whether the fetched instruction is an instruction to be emulated, and the normal mode and emulation mode are controlled. As a result, instructions executed in both operating modes can be decoded by a common instruction decoder, and there is no need to provide a special micro-code ROM for high-function instructions such as emulated instructions. This has the effect of making it possible to obtain a microcomputer that supports high-performance instructions without complicating the hardware or increasing the chip size.

Moreover, by having a separate space for instruction emulation, emulation can be performed without changing the vector handler of the operating system in relation to existing microcomputers that reuse the instruction set, and it is possible to perform emulation without changing the vector handler of the operating system. It is possible to support high-performance instructions while ensuring compatibility.

The process of returning to normal mode after transitioning from normal mode to emulation mode can be simplified by executing a return instruction included in the emulation instruction sequence.

By providing separate program counters, condition code registers, etc. for emulation instructions and other macro instructions, and controlling the switching of these registers in synchronization with switching the instruction space, you can switch the instruction space and emulate from normal mode. This has the advantage that there is no need to spend extra time saving the state of the program counter, etc. when ensuring continuity of processing when transitioning to normal mode and returning to normal mode.

By making temporary registers that can only be used to execute emulation instructions available as additional resources for executing emulation instructions, and by making data memory spaces separate for executing emulation instructions and for executing other macro instructions, Similarly, it is possible to guarantee the continuity of processing without taking the trouble of saving the state, and it is also possible to enlarge the registers and work area necessary for high-performance processing through emulation.

By providing an emulation instruction register that can receive and hold fetched emulation target instructions and transfer all or part of the held emulation target instructions to the arithmetic unit,
In arithmetic processing for executing an emulation instruction, the operation code and immediate value of the emulation target instruction corresponding to the emulation instruction can be easily used.

By reflecting all or part of the operation code in the emulation target instruction in the first address of the emulation instruction sequence, the address can be obtained in a short time by simple processing using the instruction decode cycle.

When executing an instruction in multiple stages of pipeline processing such as instruction fetch, instruction decode, and instruction execution, when an instruction to be emulated is detected in an instruction decode cycle, the next instruction that has already been fetched into the instruction register in a parallel instruction fetch cycle is By providing an instruction save register for storing instructions and returning the value of the register to the instruction register when a return instruction of an emulation instruction sequence is executed, instruction execution efficiency can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the microcomputer according to the present invention, FIG. 2 is a detailed block diagram of a central processing unit in the microcomputer of this embodiment, and FIG. 3 is a diagram illustrating the basic form of the instruction format. FIG. 4 is an explanatory diagram of an example of a 2-register format instruction, and FIG. 5 is an explanatory diagram of an example of a register and 4-pit equalize format instruction. FIG. 6 shows an example of an instruction to be emulated, and FIG. 7 shows an A.I. D
DLIST. FIG. 8 is an explanatory diagram of the processing contents for realizing the L instruction by emulation. L
FIG. 9 is a format diagram showing an example of an emulation instruction string corresponding to the instruction ADDLIST. FIG. 3 is an explanatory diagram of an example of an execution flow of an L instruction and an emulation routine corresponding thereto. Figure 10 shows ADDLIST. An explanatory diagram of an example of the 5-stage pipeline operation flow when realizing the L instruction by emulation, and FIG. 11 is another example of the instruction to be emulated.
CONV instruction format diagram, Figure 12 is DCONV
FIG. 2 is an explanatory diagram of an example of an execution flow of a command and a corresponding emulation routine. 1...Microcomputer, 2...Control unit, 3.
- Arithmetic unit, 4...ROM, 5...RAM, 40...
- Emulation ROM, 41... User ROM, 5
0... Emulation RAM, 51... User R
AM, IRO to IR5...Instruction register, IRB...Inst 1-action save register, E
IR...Emulation instruction register, TAG1 to TAG5...Tag register, DECF,
DECA, DECD, DECM...instruction decoder, φ
I, φD... Space switching control signal, pcO-PC
3...Program counter, PCEMO to PCEM3
...Program counter for emulation, T1
~T3...Temporary register for emulation, CCR...Condition code register, CCR
EM: Condition code register for emulation, C0NT: Control circuit. Figure 1 ■ / Figure 7 Figure 8 / Figure 4゜Figure 9 Figure 11 Figure 12 February 19, 1992 Director-General of the Patent Office 1, Indication of Case 1990 Patent Application No. 332846 2 , Name of the invention Microcomputer 3, Relationship with the person making the amendment Patent applicant name (5101 Hitachi Ltd. 4, Agent address 401 Suncourt Yushima, 3-21-5 Yushima, Bunkyo-ku, Tokyo)

Claims (1)

[Scope of Claims] 1. A microcomputer that emulates an emulation target instruction as a predetermined instruction included in a macro instruction set with an emulation instruction sequence as another macro instruction, wherein the space of the emulation instruction is used as an emulation instruction string as another macro instruction. A control means that is separate from the instruction space and has logic for determining whether a fetched instruction is an emulation target instruction and switching the instruction space to the emulation instruction space when an emulation target instruction is detected. A microcomputer characterized by: 2. The control means further includes logic for determining whether or not the fetched instruction is a return instruction as an emulation instruction, and for switching the emulation instruction space to another macro instruction space when a return instruction is detected. 2. The microcomputer according to claim 1, wherein the microcomputer is a microcomputer. 3. It has a program counter and a condition code register dedicated for emulation instructions and other macro instructions, and the control means includes logic for switching and selecting the registers in response to instruction space switching. The microcomputer according to claim 1 or 2, further comprising the following. 4. Temporary registers that can be used only for executing emulation instructions are provided, and the control means includes logic that makes these temporary registers available for additional use as resources for executing emulation instructions in response to detection of an instruction to be emulated. 4. The microcomputer according to claim 1, further comprising: a microcomputer according to claim 1; 5. An emulation instruction register is provided which receives and holds the emulation target instruction from the instruction register and can transfer all or part of the emulation target instruction held by the emulation instruction register to the arithmetic unit. A microcomputer according to any one of claims 1 to 4. 6. Claim characterized in that the control means further includes logic for calculating the address of the corresponding emulation instruction using all or part of the operation code in the emulation target instruction. 6. The microcomputer according to any one of items 1 to 5. 7. Separate dedicated data memory spaces are provided for instruction execution in the emulation instruction space and instruction execution in other macro instruction spaces; 7. The microcomputer according to claim 1, further comprising the following logic for switching and controlling the microcomputer. 8. When the control means detects an instruction to be emulated in an instruction decode cycle, an instruction save register is provided for storing the next instruction fetched in a parallel instruction fetch cycle; 3. The microcomputer according to claim 2, further comprising logic for returning the value of the instruction save register to the instruction register when an instruction is detected.