JPH04200224A - Inspection system for digital protective relay - Google Patents

Inspection system for digital protective relay

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Publication number
JPH04200224A
JPH04200224A JP2332898A JP33289890A JPH04200224A JP H04200224 A JPH04200224 A JP H04200224A JP 2332898 A JP2332898 A JP 2332898A JP 33289890 A JP33289890 A JP 33289890A JP H04200224 A JPH04200224 A JP H04200224A
Authority
JP
Japan
Prior art keywords
inspection
level
power flow
protective relay
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2332898A
Other languages
Japanese (ja)
Other versions
JP2723354B2 (en
Inventor
Kazuo Ueno
和生 上野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2332898A priority Critical patent/JP2723354B2/en
Publication of JPH04200224A publication Critical patent/JPH04200224A/en
Application granted granted Critical
Publication of JP2723354B2 publication Critical patent/JP2723354B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To obtain an inspection system for digital protective relay which can be applied even on a system having significantly short time variation of tidal current by making the value for judging defective inspection variable with the variation of tidal current. CONSTITUTION:A setting circuit 9 sets a tidal current variation alpha in a system. A CPU operating circuit 8 performs operation shown by formula 1 at step 8a and then performs operation shown by formula 4 while taking account the variation alpha of tidal current at step 8b. Operation shown by formula 5 is then performed at step 8c while taking account the variation alpha of tidal current. Results at steps 8b, 8c are then judged at step 8d. In case of acceptable inspection, the control proceeds to step 8e where 'I-level OK' is set and then an inspection counter is counted up at step 8f thus completing inspection. Otherwise, the control proceeds to step 8g where 'I-level NO' is set and the defective inspection is alarmed externally at step 8h thus completing the inspection.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は、系統側に変動負荷を有する場合におけるディ
ジタル保護継電装置の点検方式に関する。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an inspection method for a digital protective relay device when there is a fluctuating load on the grid side.

(従来の技術) 第3図により、ディジタル保護継電装置で一般的に行な
われているアナログ入力回路の点検方式について説明す
る。
(Prior Art) Referring to FIG. 3, a method of inspecting an analog input circuit that is generally performed in a digital protective relay device will be described.

アナログ入力回路は入力変換器1、フィルタ回路5、マ
ルチプレクサ回M6、アナログ・ディジタル変換回路7
等からなり、保護継電装置の保護演算用電流・電圧デー
タをCPu演算回路8へ導入する機能を有し、保護継電
装置における最も重要な回路である。電圧データについ
ては常時定格電気量が印加されているため常時監視で異
常を発見することが可能であるが、電流データについて
は系統運用状況によりそのレベルが一定しないため、点
検によりその回路に異常がないことを確認しておくこと
が是非とも必要である。この点検に際して、点検指令に
より点検入力印加回路3を閉路し、点検入力用発振回路
2の出力を点検入力重畳回路4に与える6点検入力重畳
回路4では入力変換部1からの系統電気量に入力印加回
路3からの点検入力量を重畳し、重畳電気量はフィルタ
回路5、マルチプレクサ回路6、アナログ・ディジタル
変換回路7を介してCPU演算回路8へ導入される。
The analog input circuit includes an input converter 1, a filter circuit 5, a multiplexer circuit M6, and an analog-to-digital conversion circuit 7.
It has the function of introducing current and voltage data for protection calculation of the protective relay device into the CPU calculation circuit 8, and is the most important circuit in the protective relay device. Regarding voltage data, since the rated amount of electricity is always applied, it is possible to detect abnormalities through constant monitoring, but because the level of current data varies depending on the system operation status, it is possible to detect abnormalities in the circuit by inspection. It is absolutely necessary to confirm that there is no such thing. During this inspection, the inspection input application circuit 3 is closed in response to an inspection command, and the output of the inspection input oscillation circuit 2 is supplied to the inspection input superimposition circuit 4.6 The inspection input superposition circuit 4 inputs the amount of grid electricity from the input converter 1 to the inspection input superimposition circuit 4. The inspection input amount from the application circuit 3 is superimposed, and the superimposed electrical amount is introduced into the CPU arithmetic circuit 8 via the filter circuit 5, the multiplexer circuit 6, and the analog-to-digital conversion circuit 7.

CPu演算回路8では以下に示すようにアナログ入力点
検としてのソフトウェア演算処理が行なわれる。
The CPU arithmetic circuit 8 performs software arithmetic processing as an analog input check as shown below.

8aステツプでは潮流キャンセル処理が実行される0点
検時にディジタルリレーに入力される電気量は前記した
通り、点検入力量(ITS)と系統電気量(■、)のベ
クトル合成されたものである。
In step 8a, the amount of electricity input to the digital relay at the time of zero inspection in which power flow cancellation processing is executed is, as described above, a vector combination of the amount of inspection input (ITS) and the amount of system electricity (■,).

系統電気量(I、)は系統運用状況によって変化しうる
ものであり、点検入力量(ITs)のレベルを知るため
にはこれを除外する必要がある。ディジタルリレー特有
のデータメモリ機能を有効に活用し、(1)式を演算す
ることで目的を達せられる。
The system electricity amount (I,) can change depending on the system operation status, and it is necessary to exclude it in order to know the level of the inspection input amount (ITs). The purpose can be achieved by effectively utilizing the data memory function unique to digital relays and calculating equation (1).

点検暗電流 点検前電流 ITS・・・点検入力成分 I  ′、I  ′、I  ′・・・各和事前潮流RL
      SL      TLIRL、ISt” 
TL・・・点検時各相潮流成分I  、  I  、 
 IT・・・求める各相潮流キャンセルS 後の成分 (1)式において、通常の系統では潮流の急変がないた
め、■ 〜I  ′ (S相、T相も同様)でRL  
 RL あり、潮流キャンセル後の各相成分(I、I。
Inspection dark current Pre-inspection current ITS...Inspection input component I', I', I'...Each sum pre-current RL
SL TLIRL, ISt”
TL...Each phase power flow component I, I, during inspection
IT...Determined power flow cancellation S for each phase In the following component (1) equation, since there is no sudden change in power flow in a normal system, RL is
RL Yes, each phase component after power flow cancellation (I, I.

S I )は全て点検入力成分(11S)として得られ■ る。S I) are all obtained as inspection input components (11S)■ Ru.

8bステツプでは相対値レベルチエツクか実行される。In step 8b, a relative value level check is performed.

点検入力が各相への同相入力であることに着目し、(1
)式で得られたデータを使用して(2)式を演算するこ
とで各相間の位相関係が正しいことを確認する。
Focusing on the fact that the inspection input is the in-phase input to each phase, (1
) It is confirmed that the phase relationship between each phase is correct by calculating the equation (2) using the data obtained from the equation.

(2)式において、ε0が点検不良判定レベルを示して
る。具体的な数値例としては、リレーハード誤差(1〜
2%)、ソフト演!誤差(1〜2%)、周波数変動等の
リレー外部条件誤差(3%)の合計(5〜7%)に対し
、マージンとして約2倍を考慮して点検入力の15%程
度で設定されている。
In equation (2), ε0 indicates the inspection defect determination level. As a specific numerical example, relay hard error (1 to
2%), soft performance! It is set at about 15% of the inspection input, taking into account about twice the margin as the total (5 to 7%) of errors (1 to 2%) and relay external condition errors such as frequency fluctuations (3%). There is.

8Cステツプでは絶対値チエツクが実行される。In step 8C, an absolute value check is performed.

相対値チエツクでは各相間の位相関係と相対レベルがチ
エツクされるが、絶対レベルがチエツクできない、(1
)式で得られたデータを使用して(3)式を演算するこ
とで絶対値レベルが正しいことを確認する。
In relative value checking, the phase relationship and relative level between each phase are checked, but the absolute level cannot be checked.
) Confirm that the absolute value level is correct by calculating equation (3) using the data obtained from equation.

K  < l I Hl <K2     f3)式(
3)式においてに1が下限判定レベル、K2が上限判定
レベルを示し、継電器入力誤差等を考慮して、通常、点
検入力レベル(I、S)に対して下限値が85%、上限
値が115%程度にて設定されている。K、に2のレベ
ル設定根拠は前述したε0のそれに準じている。なお、
各相の相対性は相対値チエツクで確認されるため、絶対
値チエツクは代表相(たとえばR相)で実施される。
K < l I Hl < K2 f3) Formula (
3) In the formula, 1 indicates the lower limit judgment level and K2 indicates the upper limit judgment level. Considering relay input errors, etc., the lower limit value is usually 85% and the upper limit value is 85% of the inspection input level (I, S). It is set at about 115%. The basis for setting the level of K and 2 is based on that of ε0 described above. In addition,
Since the relativity of each phase is confirmed by a relative value check, an absolute value check is performed on a representative phase (for example, R phase).

8dステツプでは、8bステツプと80ステツプの結果
を判定する。点検良好ならば8eステツプへ進み「I−
レベルOKJとし、8fステツプで点検カウンタをUR
L、点検を終了する。否ならば8gステップへ進み[I
−レベルNOJとし、8hステツプで点検不良外部警報
を行ない、点検を終了する。
In the 8d step, the results of the 8b step and 80 step are determined. If the inspection is good, proceed to step 8e and “I-
Set the level to OKJ and set the inspection counter to UR in 8f steps.
L. Finish inspection. If not, proceed to 8g step [I
- Set the level to NOJ, issue an external alarm for inspection failure in 8-hour steps, and complete the inspection.

以上がアナログ入力回路点検ソフトウェア処理の概要で
ある。
The above is an overview of the analog input circuit inspection software processing.

(発明が解決しようとする課題) 上記した従来の点検方式では、潮流キャンセルアルゴリ
ズムを演算のベースとして使用している。
(Problems to be Solved by the Invention) The conventional inspection method described above uses a power flow cancellation algorithm as the basis of calculation.

これは前述した通り点検暗電流から点検前電流を差し引
くことで実現しており、あくまで潮流が短時間に急変し
ないことを射程として考案されたアルゴリズムである。
As mentioned above, this is achieved by subtracting the pre-inspection current from the inspection dark current, and is an algorithm designed to ensure that the current does not suddenly change in a short period of time.

超高圧系統(275kV以上)では潮流の急変動はない
なめ従来の点検方式でも間Uはないが、低位系統(15
4kV以下)においてはこの潮流変動が無視できないこ
とが判明してきている。特に系統近傍に鉄鋼所等の工場
設備を有する場合においては、事前潮流(I ′)と点
検時R[ 潮流成分(IRl)の差が大きくなり、従来の点検方式
では装置が正常であるにも拘わらず点検不良に至ること
があり得る。
In ultra-high voltage systems (275 kV or higher), there are no sudden changes in power flow, so there is no time difference even with conventional inspection methods, but in low-voltage systems (15 kV or higher)
4kV or less), it has become clear that this power flow fluctuation cannot be ignored. Particularly in cases where there is factory equipment such as a steel mill near the system, the difference between the preliminary power flow (I') and the power flow component (IRl) at the time of inspection becomes large, and with conventional inspection methods, even if the equipment is normal, Inspection failure may occur regardless of the situation.

本発明は上記問題点を解決するためになされたものであ
り、潮流の短時間変動が顕著な系統においても適用でき
るディジタル保護継電装置の点検方式を提供することを
目的としている。
The present invention has been made to solve the above problems, and an object of the present invention is to provide an inspection method for a digital protective relay device that can be applied even to systems where short-term fluctuations in power flow are significant.

[発明の構成] (課題を解決するための手段) 上記目的を達成するために本発明では、点検不良判定値
を潮流変動の値をにらみ可変できるように構成した。
[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention is configured such that the inspection failure determination value can be varied in consideration of the value of the power flow fluctuation.

(作 用) したがって潮流変動のある系統においても点検不良判定
値を可変して設定できるため、系統毎にレベルが興なる
潮流変動に対し最適の点検不良判定レベルを設定して、
保護継電装置のアナログ入力回路点検を実施することが
可能となる。
(Function) Therefore, the inspection failure judgment value can be varied and set even in systems with power flow fluctuations, so the optimum inspection failure judgment level can be set for power flow fluctuations that vary in level for each system.
It becomes possible to inspect the analog input circuit of the protective relay device.

(実施例) 以下、第1図を参照して本発明の詳細な説明する。第1
図の基本構成は既に説明した第3図と同様であり、同一
内容については同一符号を付して説明を省略する。9は
整定回路であり、系統における潮流変動分(α)を整定
する。なお、整定回路はディジタル保護継電装置には必
ず備えられている回路であり、ここに整定要素を1個追
加するだけの構成としている。そしてCPu演算回路8
では上記で整定された潮流変動分(α)を導入し、以下
のソフトウェア演算にて処理する。
(Example) Hereinafter, the present invention will be described in detail with reference to FIG. 1st
The basic structure of the figure is the same as that of FIG. 3 already explained, and the same contents are given the same reference numerals and the explanation will be omitted. Reference numeral 9 denotes a settling circuit, which settles the power flow fluctuation (α) in the system. Note that the setting circuit is a circuit that is always provided in a digital protective relay device, and the configuration is such that only one setting element is added thereto. And CPU calculation circuit 8
Now, the power flow variation (α) determined above is introduced and processed by the following software calculation.

8aステツプでは前述した(1)式の演算を行なう。In step 8a, the above-mentioned equation (1) is calculated.

8bステツプでは上記整定による潮流変動分(α)を考
慮して(4)式を演算する。
In step 8b, equation (4) is calculated taking into consideration the power flow variation (α) due to the above-mentioned setting.

(4)式においてε。は前記した従来の点検不良判定レ
ベルに等しく、今回はこれに潮流変動分(α)を加算し
て相対値点検不良判定を実施するものである。
In equation (4), ε. is equal to the conventional inspection defect determination level described above, and this time, the power flow fluctuation amount (α) is added to this to perform a relative value inspection defect determination level.

8Cステツプでは同じく上記整定による潮流変動分(α
)を考慮して(5)式を演算する。
In the 8C step, the power flow fluctuation due to the above setting (α
) is taken into account to calculate equation (5).

K −αく]I 1くK +α  (5)式1式% (5)式においてK 1. K 2は前記した従来の点
検における下限判定レベル、上限判定レベルをそれぞれ
示しており、今回はこれに潮流変動分(α)を下限値に
は減算、上限値には加算して絶対値点検不良判定を行な
うものである。
K − α ] I 1 K + α (5) Equation 1 Equation % In Equation (5), K 1. K2 indicates the lower limit judgment level and upper limit judgment level in the conventional inspection described above, and this time, the power flow fluctuation (α) is subtracted from this to the lower limit value and added to the upper limit value to determine the absolute value inspection failure. It is for making judgments.

8dステツプ以下の処理は前述した従来の点検方式と同
様の処理が実施される。
Processing for steps below 8d is performed in the same manner as in the conventional inspection method described above.

第2図に本発明の他の実施例を示す、第1図との相違点
は整定回路9の内容でありこれを説明する。第1図の実
施例では潮流変動分(α)を個別整定項目として設けた
が、本実施例では電流変化分検出要素(以下ΔI要素と
称する。)の変化幅整定を共用するものである。
FIG. 2 shows another embodiment of the present invention. The difference from FIG. 1 is the content of the setting circuit 9, which will be explained. In the embodiment shown in FIG. 1, the power flow variation (α) is provided as an individual setting item, but in this embodiment, the variation width setting of the current variation detection element (hereinafter referred to as ΔI element) is shared.

ΔI要素は各相電流の変化分に対して応動するものであ
り、潮流変動に対し敏感に応動する0通常は定格電流の
10%程度で固定整定としているが潮流変動が顕著な場
合には、これを可変整定とする対応が行なわれる0本実
施例はこの可変整定値(α)に連動して点検不良判定レ
ベルを可変するものである。ΔI要素の整定は潮流変動
分をにげた値と□なるため、効果は第1図の実施例と同
様であり、個別整定項目を新たに設ける必要がない点だ
け有利である。本実施例は、Δ■要素を内蔵する保護継
電装置に限定されるが、潮流変動の顕著な低位系統にお
いては、このΔ■要素を内蔵する距離継電゛方式を用゛
いたディジタル保護継電装置が主流であるため、その効
果は大である。
The ΔI element responds to changes in each phase current, and responds sensitively to power flow fluctuations.Normally, it is fixed at about 10% of the rated current, but if the power flow fluctuations are significant, In this embodiment, the inspection failure determination level is changed in conjunction with this variable setting value (α). Since the setting of the ΔI element is □, which excludes the power flow fluctuation, the effect is similar to that of the embodiment shown in FIG. 1, and the advantage is that there is no need to newly provide individual setting items. Although this embodiment is limited to a protective relay device with a built-in Δ■ element, in a low-level system where power flow fluctuations are significant, a digital protective relay using a distance relay method with a built-in Δ■ element can be used. Since electrical devices are the mainstream, the effect is significant.

[発明の効果] 以上説明したように、本発明によれば潮流変動分(α)
を整定によってディジタルリレーに入力し、点検不良判
定レベルを可変するように構成したので、潮流変動のな
い系統は言うまでもなく、潮流変動が顕著な系統におい
てもディジタル保護継電装置の点検機能を最大限有効に
生かしつつ装置を運用できる点検方式を提供できる。
[Effect of the invention] As explained above, according to the present invention, the power flow fluctuation (α)
is input to the digital relay by setting, and the inspection failure judgment level is variable, so the inspection function of the digital protective relay device can be maximized not only in systems with no power flow fluctuations, but also in systems with significant power flow fluctuations. It is possible to provide an inspection method that allows the equipment to be operated effectively.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の1実施例を示すブロック図、第2図は
本発明の他の実施を示すブロック図、第3図は従来装置
のブロック図である。
FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing another embodiment of the present invention, and FIG. 3 is a block diagram of a conventional device.

Claims (1)

【特許請求の範囲】[Claims] 電力系統の各相に対応するアナログ電気量を一定周期で
サンプリングしてディジタル量に変換し、これを予め定
められた演算アルゴリズムに基づいてディジタル演算を
行なって動作判定し、前記電力系統を保護するようにし
たディジタル保護継電装置において、アナログ入力回路
に点検入力を印加して前記演算アルゴリズムに基づいて
振幅値を算出し、この振幅値と点検入力の差が点検不良
判定値以内であることで点検良好と判定するに際し、点
検不良判定値を可変するように構成したことを特徴とす
るディジタル保護継電装置の点検方式。
Analog electrical quantities corresponding to each phase of the power system are sampled at regular intervals, converted to digital quantities, and digitally calculated based on a predetermined calculation algorithm to determine operation and protect the power system. In such a digital protective relay device, a check input is applied to the analog input circuit, an amplitude value is calculated based on the calculation algorithm, and the difference between this amplitude value and the check input is within the check failure judgment value. 1. An inspection method for a digital protective relay device, characterized in that when determining that the inspection is good, the inspection failure judgment value is varied.
JP2332898A 1990-11-29 1990-11-29 Inspection method for digital protective relay Expired - Lifetime JP2723354B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2332898A JP2723354B2 (en) 1990-11-29 1990-11-29 Inspection method for digital protective relay

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2332898A JP2723354B2 (en) 1990-11-29 1990-11-29 Inspection method for digital protective relay

Publications (2)

Publication Number Publication Date
JPH04200224A true JPH04200224A (en) 1992-07-21
JP2723354B2 JP2723354B2 (en) 1998-03-09

Family

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Country Status (1)

Country Link
JP (1) JP2723354B2 (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55150735A (en) * 1979-05-09 1980-11-22 Mitsubishi Electric Corp Power system data detecting system
JPS5635621A (en) * 1979-08-28 1981-04-08 Tokyo Shibaura Electric Co Digital protective realy check system
JPS6049417A (en) * 1983-08-29 1985-03-18 Nec Corp Overcurrent detecting circuit
JPS60183916A (en) * 1984-02-29 1985-09-19 株式会社東芝 Digital protective relaying device
JPH0279137U (en) * 1988-12-08 1990-06-18
JPH02188121A (en) * 1989-01-11 1990-07-24 Toshiba Corp Inspection system for current differential protective relay system, central processing unit and terminal equipment

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55150735A (en) * 1979-05-09 1980-11-22 Mitsubishi Electric Corp Power system data detecting system
JPS5635621A (en) * 1979-08-28 1981-04-08 Tokyo Shibaura Electric Co Digital protective realy check system
JPS6049417A (en) * 1983-08-29 1985-03-18 Nec Corp Overcurrent detecting circuit
JPS60183916A (en) * 1984-02-29 1985-09-19 株式会社東芝 Digital protective relaying device
JPH0279137U (en) * 1988-12-08 1990-06-18
JPH02188121A (en) * 1989-01-11 1990-07-24 Toshiba Corp Inspection system for current differential protective relay system, central processing unit and terminal equipment

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