JPH042008B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a CMOS selector circuit that is high speed and consumes little power.

(Prior art) In a 1/m selector circuit that selects one of m (m≧2 ^M , M2) inputs, a 1/2 selector circuit that selects one of two inputs is used. It is common to use multiple units. Figure 3 shows an example in which the selector is configured with a 1/2 selector circuit. The 1/8 selector circuit uses 3-bit control signals a ₀ , a ₁ , a ₂ and their inverted signals ₀ , ₀ , ₂ to select inputs I ₀ to I _{7 .}
One of the data is transferred to Q _j .
That is, first, depending on the value of a ₀ , I ₀ , I ₂ , I ₄ , I ₆ or I ₁ ,
One of the pairs I ₃ , I ₅ , and I ₇ is selected. If the selected set is I ₀ , I ₂ , I ₄ , I ₆ , then either the set I ₀ , I ₄ or I ₂ , I ₆ is selected depending on a ₁ . Subsequently, one of the two is selected depending on the value of _a2 , and finally only one data is selected.

Next, FIG. 4 shows a circuit diagram of the 1/2 selector circuit shown in FIG. 3. (A) and (B) are cases where a transfer gate is used as the 1/2 selector circuit.
If the delay or distortion of the input signal is large when multiple transfer gates are connected, a buffer is usually inserted to shape the waveform.

As this buffer, CMOS inverter, E/
A DMOS inverter can be considered, but a CMOS inverter type is preferable from the perspective of low power consumption.
If you use the selector in (B), it will look like (C).

FIG. 5 shows a conventional circuit diagram in which the 1/8 selector circuit is constructed from the 1/2 selector circuit shown in FIG. 4B and a CMOS buffer. In Figure 5, R ₀ to R ₂ are 8
This is a circuit that holds control signals a ₀ , a ₁ , and a ₂ that determine which one of the book inputs is selected, D ₀ is the control signal input, and CLK ₀ enters R ₀ to _{R 2.} Is the clock signal _S1 in a connected state where the 1/8 selector circuit selects any one of the 8 inputs, or in a released state where it does not select any of the 8 inputs? This is a signal that indicates. In Figure 5, the values of a ₂ , a ₁ , and a ₀ are CLK ₀ as D ₀ .
After serial input by , normal rotation of each a ₀ , a ₁ , a ₂ ,
It is assumed that both inverted and reversed signals are output, but
Of course, the control signals may be input in parallel.

(Problem to be solved by the invention) When a high-speed digital signal of several tens of MHz is input to this selector circuit, the problem is that the CMOS
Because of the configuration, the increase in power consumption is not noticeable when low-speed digital signals are being handled. This is because in the conventional example shown in FIG. 5, parasitic capacitances and buffers that do not need to be driven are driven, and dynamic power is consumed in the input signal drive buffer and intermediate buffers. That is, in the case of the 1/8 selector shown in FIG. 5, there are two buffers in the intermediate stage. Now control signal a ₀ ,
When a ₁ and a ₂ are 1, 0, 0, I ₁ is selected and output to O ₀ . The route through which the input signal passes at this time is shown by a thick line. As you can see from the figure, the only signal that is originally required is I ₁ , but other signals enter the selector and the buffer A ₁ does not need to be driven.
This means that the parasitic capacitances C ₁ , C ₂ , C ₃ , C ₅ , and C ₇ are driven by high-speed signals unnecessarily, and unnecessary operating power is consumed accordingly.

An example of applying this selector circuit is a digital space switch LSI. Figure 6 shows an example of a digital space switch LSI with eight incoming lines and eight outgoing lines using eight 1/8 selector circuits.
I ₀ to I ₇ are incoming lines, BU is a buffer, SE ₀ to _{SE 7} are 1/8 selector circuits, and O ₀ to O ₇ are outgoing lines. When the selector circuit shown in Figure 4c is used in a digital space switch LSI, when the number of input and output lines increases, the number of buffers that operate in vain and the parasitic capacitance in the LSI also increase, and the number of input lines 16 and output lines 16 increases. In case, 176 circuits, 32 input lines
In the case of 32 outgoing lines, 912 circuits waste power. This wasted power is incoming line 32 outgoing line 32
When a high-speed digital signal of about 30MHz is input to a CMOS LSI, it reaches a value of 200 to 300mW.
There was a problem that the low power consumption of the device was impaired.

In order to eliminate these drawbacks, the present invention aims to reduce power consumption by reducing the number of unnecessarily driven buffers and parasitic capacitance as much as possible while suppressing an increase in circuit scale in a selector circuit. shall be.

(Means for Solving the Problems) In order to achieve the above object, the present invention turns off all unselected gates to cut off input signals, and also sets unselected CMOS buffer inputs to "1" or "0". A switching means Q is provided to set the value to a fixed value.

(Function) Power consumption within the CMOS is reduced by setting unselected CMOS buffer inputs to a fixed value of “1” or “0”, resulting in lower power consumption overall.
A CMOS selector circuit is obtained.

(Embodiment) FIG. 1 is an embodiment of the present invention, and similarly to FIG. 5, it shows a 1/8 selector, and R ₀ to _{R 2} ,
D ₀ , S ₀ , and CLK ₀ are the same as in FIG. In Figure 1, the signal controlling the transfer gate at the front stage increases, and the inputs of the buffers A ₀ to _{A 1} are set to “1”.
The main difference from FIG. 5 is that switching means Q (Pch transistor) for fixing the switch is added. FIG. 2 shows the logic of the control circuit shown in FIG. The 1/2 selector circuit in the front row of the 1/8 selector circuit in FIG. 1 is controlled by a connection/release signal S ₀ and 3-bit control signals LSBa ₀ and MSBa ₂ , which are control signals for selection. That is, when S ₀ = 0, the 1/8 selector circuit is in the open state, all the transfer gates at the front stage are turned off, and I ₀ (0) to I ₇ (0)
data is not accepted. At this time, the inputs of _A0 to _A1 are fixed to "1" by _f1 and _f2 . This means that A ₀ to _{A 1} are CMOS inverters, and if this gate input becomes a high impedance state,
This is to prevent the possibility of static current flowing in the inverter and consuming power due to the intermediate potential between V _DD and GND. By doing this,
All inputs in A ₀ to _{A 1} are fixed values of "1" or "0", and the power consumed in A ₀ to _{A 1} is only due to leakage, resulting in a remarkable reduction in power consumption. On the other hand, when S ₀ =1, the 1/8 selector circuit of FIG. 1 is in a connected state and always selects one of the eight inputs. At this time, it has already been stated that all the buffers of A ₀ and A ₁ and all the parasitic capacitances in the selector do not need to be driven.
MSBa ₂ allows about half to be inactive. That is, when a ₂ =0, the upper half in charge of I ₀ to I ₃ is in an operating state, and the lower half in charge of I ₄ to _{I 7} is in an inactive state and is not driven. Further, when a ₂ =1, the lower half in charge of I ₄ to I ₇ is in an operating state, and the upper half in charge of I ₀ to _{I 3} is in an inactive state and is not driven. In the open state where S ₀ =0, the entire selector is inactive and no extra parasitic capacitance is driven.

The power during CMOS operation is P∝fCV ² (P: power consumption, f: frequency, C: load capacity, V: power supply voltage)
The effect of FIG. 1 is significant because the power consumption can be reduced in proportion to the load capacity.

In Figure 1, the number of control circuits and control lines increases, which leads to an increase in pattern area.The operating frequency of the control circuit is generally lower than the frequency of data passing through the selector circuit, so power consumption by the control circuit increases. can be ignored.

Furthermore, since the scale of the control circuit excluding the control signal holding circuit remains constant even as the scale of the selector increases, the effect of the present invention is more pronounced for large-scale selector circuits with 32 or 46 inputs. becomes. In particular, the space switch LSI shown in Figure 6, which uses a selector circuit.
The effect is great. In Figure 1, as a transistor Q for fixing the buffer input voltage, P-ch
Using a transistor, the output O ₀ in the open state was made to have the same polarity as O ₀ in Figure 5 (“0” in this case).
Of course, the same reduction in power consumption can be achieved by using an N-ch transistor and the inverted signals f ₁ and f ₂ shown in FIG. 5 as control signals, and by adding one more stage of inverter to the final stage.

Furthermore, although the example using FIG. 4B as the 1/2 selector circuit has been described, it goes without saying that the same effect can be achieved when the circuit of FIG. 4A is used.

(Effects of the Invention) As explained above, by applying the circuit described in this explanation to the COMS selector circuit, it is possible to reduce the buffer load capacity that does not need to be driven, and it is possible to reduce power consumption. When implementing digital space switch LSIs using this circuit, there are significant advantages in terms of operating speed and power consumption.

[Brief explanation of drawings]

Figure 1 shows an embodiment of the selector circuit of the present invention (1/8
FIG. 2 is a diagram showing the control logic of the selector circuit of the present invention, and FIG. 3 is a diagram showing the control logic of the selector circuit of the present invention. FIG. Figure 4 shows an example of an 8-selector circuit. Figure 4 shows a 1/2 selector circuit and CMOS buffer, Figure 5 shows a conventional selector circuit, and Figure 6 shows an example of a 1/8 selector circuit using eight input lines and eight output lines. Space switch with 8 lines
FIG. 2 is a diagram showing an example of an LSI configuration. I ₀ ~ I ₇ ... Input, Oj ... Output, S _0j ~ S _6j ... 1/2
Selector, a ₀ , a ₁ , a ₂ ... Control signal for selecting one of the eight transistors, Q ₁ , Q ₂ , Q ₄ ... N-channel transistor (enhancement type), Q ₃ ,
Q ₅ , Q ₆ ... P channel transistor (enhancement type), D ₀ ... 1/2 selector circuit output,
BU...Buffer that sends incoming data to each selector, _A0 to _A1 ...Buffer used in the middle stage of the 1/2 selector circuit ( _A2 in Figure 5 is an AND circuit), _S0 ...1 /m Selector control signal that determines connection or release, R ₀ to R ₂ ...Circuit that holds the selector control signal that selects one of the 8 input lines,
D ₀ ... _R0 input signal, CLK ₀ ... _R0 to _R3 clock signal, SE ₀ to _{SE 7} ...1/8 selector circuit, BU...
... Buffer that sends incoming data to each selector, O ₀ - O ₇ ... Output, b ₁ - f ₁ , b ₂ - h ₂ ... Signal that controls the 1/2 selector in the front row.

Claims (1)

[Claims] In a 1/m selector circuit that selects any one of 1 m (natural number of m4) inputs or deselects all inputs, the number of inputs is m. =2 ^M (M2 is a natural number), using (2 ^M -1) 1/2 selector circuits, and the above 1/2 selector circuit is composed of two transfer gates,
In a CMOS selector circuit configured to insert a CMOS buffer between arbitrary 1/2 selector circuits, the 2 ^M transfer gates of the 2 ^M-1 1/2 selector circuits in the front row are connected to the 1/m selector circuit. The 1-bit first control signal (S ₀ ) determines connection or release, and the 2 ^M- 1 first control signal (S 0 ) in the front row among the M-bit control signals for selecting one of m inputs. A 1-bit second control signal (contents of R ₀ ) that controls the 1/2 selector circuit, and a 1-bit third control signal (contents of R ₂ ) that controls one 1/2 selector circuit in the last column. If the first control signal indicates that the 1/m selector circuit is to be opened, all ^2M transfer gates are turned off and the first row of
2 The output of ^M-1 1/2 selector circuits is set to a fixed value of “1” or “0”, and the first control signal is set to 1/m
If it indicates that the selector circuit is to be connected, ^{2M -1} transfer gates that do not belong to the path selected by the third control signal among the 2M transfer gates in the front row are connected. All agates are turned off, and the first row of agates that do not belong to the path selected by the third control signal are
2 A switching means Q is provided for setting the outputs of ^{the M-2} 1/2 selector circuits to a fixed value of "1" or "0", and the switching means Q of the front row belonging to the path selected by the third control signal is provided. The 2 ^M-1 transformer gate is controlled by the second control signal to select one of the two inputs that enter one 1/2 selector circuit, and the (2 ^M- 1 ^1-1 ) 1/2 selector circuits are controlled by (M-1) bit control signals excluding the second control signal.
CMOS selector circuit.