JPH0420129U - - Google Patents
Info
- Publication number
- JPH0420129U JPH0420129U JP6206090U JP6206090U JPH0420129U JP H0420129 U JPH0420129 U JP H0420129U JP 6206090 U JP6206090 U JP 6206090U JP 6206090 U JP6206090 U JP 6206090U JP H0420129 U JPH0420129 U JP H0420129U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- digital
- input circuit
- digital input
- switching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Description
第１図は本考案に係るデジタルステータス入力
回路の一実施例を示す回路構成図、第２図は第１
図の回路の動作を示す回路構成図、第３図は従来
のデジタルステータス入力回路の一例を示す回路
構成図である。
１……切換え回路、２……バツフア回路、３…
…コントロール信号発生回路、４……データバス
、Ｔｒ１〜Ｔｒｎ……トランジスタ、ＶＥ……電
源部、Ｄ１〜Ｄｎ……デジタル入力回路、Ｂ１〜
Ｂｎ……バツフア。
FIG. 1 is a circuit configuration diagram showing one embodiment of the digital status input circuit according to the present invention, and FIG.
FIG. 3 is a circuit diagram showing an example of a conventional digital status input circuit. 1...Switching circuit, 2...Buffer circuit, 3...
...Control signal generation circuit, 4...Data bus, Tr1 to Trn ...Transistor, VE...Power supply section, D1 to Dn ...Digital input circuit, B1 to
B n ...Batsuhua.
Claims (1)
クタ側に接続されたデジタル入力回路と、各トラ
ンジスタのエミツタ側を等電位点に接続するとと
もに前記各デジタル入力回路に電源を供給する電
源部と、からなるデジタルステータス入力回路に
おいて、 前記電源部をオン／オフする切換え回路と、 アクテイブになつたときに前記各デジタル入力
回路の入力値を取り込むバツフア回路と、 読み込み信号と回路選択信号の両方がアクテイ
ブになつたときのみに、前記切換え回路をオンに
して前記デジタル入力回路に電源を供給するとと
もに、前記バツフア回路をアクテイブにするコン
トロール信号を発生するコントロール信号発生回
路と、 を具備したことを特徴とするデジタルステータス
入力回路。[Claims for Utility Model Registration] A plurality of transistors, a digital input circuit connected to the collector side of each transistor, and an emitter side of each transistor connected to an equipotential point, and supplying power to each digital input circuit. A digital status input circuit consisting of a power supply section, a switching circuit that turns on/off the power supply section, a buffer circuit that takes in the input value of each of the digital input circuits when activated, and a read signal and a circuit selection signal. a control signal generating circuit that turns on the switching circuit to supply power to the digital input circuit and generates a control signal that activates the buffer circuit only when both of the switching circuits become active. A digital status input circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6206090U JPH0420129U (en) | 1990-06-12 | 1990-06-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6206090U JPH0420129U (en) | 1990-06-12 | 1990-06-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0420129U true JPH0420129U (en) | 1992-02-20 |
Family
ID=31590868
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6206090U Pending JPH0420129U (en) | 1990-06-12 | 1990-06-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0420129U (en) |
-
1990
- 1990-06-12 JP JP6206090U patent/JPH0420129U/ja active Pending
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