JPH0420311B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an imaging device using imaging means such as a solid-state imaging device.

(Prior art) Conventionally, this type of device has an X-Y address type
MOS image sensor, interline type CCD, frame transfer type CCD, or
BBD party's solid-state image sensor is often used.
Among them, frame transfer type CCDs are structurally much simpler than MOS image sensors and interline type CCDs because they do not require a vertical transfer register in the imaging section. Therefore, it is possible to provide a larger number of horizontal pixels corresponding to the horizontal direction of a TV screen.

Figure 1 shows such a conventional frame transfer type.
As shown in the figure, the CCD 100 includes an imaging section 1 that performs photoelectric conversion, and an imaging section 1 that performs photoelectric conversion.
a horizontal shift register 3 that takes in the accumulated charge in the memory section 2 according to VT horizontal synchronization and transfers it horizontally; and an output amplifier 4 for converting the voltage into a voltage and outputting the voltage. On the imaging section 1 of such a CCD 100, a color separation filter necessary for obtaining color signals is provided by adhesive or on-chip.

FIG. 2 shows an example of such a color separation filter.

Here, we will discuss a conventional example using a complementary color stripe color filter consisting of three types of filter parts: Ye (yellow), G (green), and Cy (cyan), which are said to have extremely high light utilization efficiency. .

When using such a filter, as shown in Figure 1
A horizontal transfer clock pulse having a frequency corresponding to the pixel pitch in the horizontal direction is applied to the horizontal shift register 3 of the CCD 100 as shown by φs in FIG. 3, and the output amplifier 4 outputs an output as shown by S in FIG. I get a signal.

This output signal S is originally required Ye, G, Cy
In addition to the point sequential signal component A, it includes a clock noise component B due to the transfer pulse φs.

Figure 4 shows CCD100 obtained in this way.
This figure shows a conventional example of a signal processing circuit for separating and obtaining a luminance signal and a color signal from the output signal of the . The output signal S is first amplified by an inverting amplifier 5, then a clock noise component is removed by a sample and hold circuit 6, and then a luminance signal (hereinafter referred to as Y signal) is extracted through an LPF 7. In this case, the Y signal is the original calculation ratio (Y = 0.59G +
0.33R+0.11B), but this is sufficient as a simple one, and it is also possible to add corrections later. On the other hand, regarding the color signal, sample holds 61, 62, and 63 output Ye, G, and
Each signal of Cy is separated and then this separated
The Ye, G, and Cy signals are LPF71, 72, and 7, respectively.
3 to the arithmetic units 81 and 82, respectively, as shown in the figure.
(red) and B (blue) signals are obtained.

In this way, conventionally, a sample and hold circuit 6 is required to remove clock noise, and three sample and hold circuits (6) are required for color separation.
1, 62, 63), the size of the signal processing circuit increases, and the price increases.

(Objective) The present invention solves the above-mentioned drawbacks of the conventional art, and eliminates or significantly reduces the need for sample-and-hold circuits for removing clock noise components and for color separation, thereby reducing the size and cost of signal processing circuits. The object of the present invention is to provide a novel imaging device that enables the following.

(Example) The present invention will be explained below based on Examples.

First, an embodiment of the present invention will be explained with reference to FIGS. 5 and 6. In order to eliminate the above-mentioned drawbacks, this embodiment uses one horizontal shift register as a readout transfer path as in the prior art. CCD with
Instead, for example, as shown in Figure 5a, three horizontal shift registers are used as readout transfer paths.
It uses CCD.

That is, the CCD 101 shown in FIG. 5a has three horizontal shift registers 3 as readout transfer paths.
1, 32, and 33 (each of which is isolated from the others by means such as a control gate), and the charges generated in the imaging section 1 and stored in the memory section 2 are read out from the memory. Column 1 in the arrangement along the columns and rows of photosensitive cells through the distribution section 2a provided at the last stage of section 2;
4, 7,...3n-2, rows 2, 5, 8,..., 3n-1,
and columns 3, 6, 9, ...3n, and the first group (columns 1, 4, 7, ...3n
-2), for example, the horizontal shift register 31
, the second group (columns 2, 5, 8, ...3n-1)
For example, the charges of the third group (columns 3, 6, 9, ... 3n) are taken into the horizontal shift register 32, and the charges of the third group (columns 3, 6, 9, ... 3n) are taken into the horizontal shift register 33, respectively, and then each shift register is separated from each other by the control gate. and these registers 31 to 3
By driving the registers 31 and 3 in the same phase, each register 31,
The configuration is such that the signals of each group can be obtained in phase from charge-voltage conversion output amplifiers 41, 42, and 43 provided at the output stages 32 and 33.

Three horizontal shift registers 31 as described above
5b in the imaging unit 1 of the CCD 101 having 33
As shown in FIG _. 5, if a stripe color filter with _the same color scheme as that shown in _FIG. By providing respective horizontal transfer clock pulses, the output amplifier 4
1, 42, and 43, outputs shown as S ₁ , S ₂ , and S ₃ in FIG. 5c, that is, outputs corresponding to Ye, G, and Cy, respectively, are obtained in phase.

FIG. 6 shows an example of a signal processing circuit for obtaining a Y signal and a color signal from the Ye, G, and Cy signals obtained from the CCD 101 in this manner.

First, for the Y signal, the output S ₁ (Ye) and the output
A signal S ₂ ' that is delayed by passing S ₂ (G) through the delay circuit 10 and a signal that is further delayed by passing the output S ₃ (Cy) similarly through the delay circuit 11.
S ₃ ' in an adder circuit 12, passes it through an inverting amplifier 13, and then removes high frequency components in an LPE 7. Delay circuit 1
0, 11 are the horizontal transfer clock pulses φs ₃₁ , φs ₃₂ , φs ₃₃ as _shown in FIG _.
The delay times are set to be 1/3 and 2/3 of one period, respectively. Therefore, as shown in FIG. 5c, the signal SY taken out as the output of the adder circuit 12 has a clock noise component whose period is 1/3 of the repetition period of the horizontal transfer clock pulse, so the clock noise component is removed by the LPF 7. Can be easily removed. On the other hand, the signal component also
Since high frequency components are removed by the LPF 7, a simple Y signal can be obtained as in the conventional example.

Next, the color signal can be obtained as follows. That is, the subtracter 83 performs the calculation (S ₂ -S ₁ ) to obtain the signal SB. This means that the calculation -G-(-Ye)=R is performed as a signal component, resulting in an R point-sequential signal.
On the other hand, the clock noise component can be almost completely removed because the clock noise contained in the outputs S ₁ and S ₂ are equal. The thus obtained R point sequential signal S _R is passed through the LPF 74 to remove high frequency components and becomes an R color signal. Similarly, subtractor 8
In No. 4, a B point-sequential signal without a clock noise component is obtained by the calculation (S ₂ -S ₃ ), and is passed through the LPF 75 to become a B color signal.

In this way, in this embodiment, the Y signal and R,
Each B color signal can be obtained with a simple circuit configuration without using a sample and hold circuit.

Note that in the above embodiment, the duty of the horizontal transfer clock pulses φ ₃₁ to φ ₃₃ for the horizontal registers 31 to 33 is not particularly defined, but it is set to 1/
3 or 2/3, it is possible to almost completely remove clock noise components from the output SY of the adder 12. FIG. 7 shows the case where the duty of the horizontal transfer clock pulses φ ₃₁ to _{φ 33} is set to 1/3. In this case, the output S1 of the output amplifier 41 and each output S ₂ ' of the delay circuits 10 and 11,
Each clock noise component in S ₃ ' has a phase shifted from each other by 1/3 period of the period of the horizontal transfer clock pulse, and the width is also 1/3 period, so adder 1
When the signal SY is synthesized by 2, the clock noise components cancel each other out, and only the signal component is obtained.

Furthermore, in the above embodiment, horizontal transfer clock pulses φ _S31 , φ _S32 , and φ _S33 were of the same phase.
Instead of this, one having a phase different from each other by 1/3 period may be used. In this case, each output amplifier 4
Since the outputs S ₁ , S ₂ , and S ₃ of the outputs S 1 , 42 , and 43 inevitably have signals whose phases differ by 1/3 period, the delay circuits 10 and 11 are used to delay the outputs S ₂ and S ₃ . is no longer necessary for the adder 12 for obtaining the luminance signal, and instead for the subtracter 83 for obtaining the color signal.
84.

Next, another embodiment of the present invention will be described with reference to FIGS. 8 and 9. In this embodiment, as shown in FIG. 8a, a CCD having two horizontal shift registers is used as a readout transfer path.

That is, the CCD 102 shown in FIG. 8a has two horizontal shift registers 3 as readout transfer paths.
4 and 35 (each of which is isolated from the other by means such as a control gate), and the charges generated in the imaging section 1 and stored in the memory section 2 are stored in the memory section 2 when read out. Columns 1, 3, 5...2n-1 and columns 2, 4, 6...2n in the arrangement along the vertical columns and horizontal rows of photosensitive cells through the distribution section 2a provided at the last stage of section 2. divided into two groups,
The charges in the first group (columns 1, 3, 5...2n-1) are taken into the horizontal shift register 34, and the charges in the second group (columns 2, 4, 6...2n) are taken into the horizontal shift register 35, respectively. Then,
By driving these registers 34 and 35 in the same phase, the signals of each group can be obtained in the same phase from the charge voltage conversion output amplifiers 44 and 45 provided at the output stage of each register 34 and 35. When a stripe color filter having the same color scheme as that shown in FIG. 2 is provided in the imaging section 1 of the CCD 102 as shown in FIG. By providing _S34 and φ _S35 , the output amplifiers 44 and 45 of the output stage of each horizontal shift register 34 and 35 produce outputs as shown by S ₁₁ and S ₁₂ in FIG. 8c, respectively, that is, the Ye signal. An output S ₁₁ containing alternately the and Cy signals and an output S ₁₂ containing only the G signal are obtained.

FIG. 9 shows an example of a signal processing circuit for obtaining a Y signal and a color signal from such outputs S ₁₁ and S ₁₂ .

First, regarding the Y signal, the output S ₁₁ and the output S ₁₂ are delayed by passing through the delay circuit 14.
S ₁₂ ' in an adder circuit 15, and the output thereof is passed through an inverting amplifier 13 and then further passed through an LPF 7. In this case delay circuit 1
4 has an output S ₁₁ as shown _in Fig. 8c.
The amount of delay is set so that the phase is exactly inverted with respect to the clock noise component. Therefore, the adder circuit 15
As shown in the output SY in FIG. 8c, the clock noise component is almost completely removed.

On the other hand, for the color signal, the subtracter 85 calculates (S ₁₁ −
S ₁₂ ), a dot-sequential signal in which R and B are arranged alternately as shown by SC in FIG. By sampling and holding, independent point sequential signals of R and B are obtained, and R and B color signals are obtained by LPFs 74 and 75. In this example, complementary color type color filters were used, but the color arrangement of the filter is not limited to the example. Furthermore, it is of course possible to use a pure color filter as a color filter by performing the necessary operations in an addition/subtraction circuit.

(Effects) As explained above, according to the present invention, the sample-and-hold circuit conventionally used for removing clock noise can be made unnecessary, and the sample-and-hold circuit for color separation can also be omitted or greatly reduced. This provides many advantages, such as being able to reduce clock noise and, at the same time, almost completely eliminate clock noise.

[Brief explanation of drawings]

Figure 1 is a configuration diagram of a conventional frame transfer type CCD.
Figure 2 is a diagram showing an example of a striped color filter with a color scheme of Ye, G, and Cy, and Figure 3 is the same as in Figure 1.
A waveform diagram showing horizontal transfer clock pulses and their output signals for the CCD, FIG. 4 is a block diagram showing an example of a conventional signal processing circuit applied to the CCD shown in FIG. 1, and FIG. 5a shows the first embodiment of the present invention. A configuration diagram of a frame transfer type CCD as an imaging means applied to the example, FIG. 5b is a diagram illustrating the distribution of one horizontal line of signals of the memory section of the CCD shown in FIG. 5a according to color to three horizontal registers. FIG. 5c is a waveform diagram showing the horizontal transfer clock pulse and its output signal for the CCD shown in FIG.
A block diagram showing the signal processing circuit of the embodiment, FIG. 7 is a waveform diagram showing the output signal when the duty ratio of the horizontal transfer clock pulse to the CCD is changed in the first embodiment, and FIG. 8a is a waveform diagram of the second embodiment. A configuration diagram of a frame transfer type CCD as an applied imaging means,
Figure 8b is 1 of the memory section of the CCD shown in Figure 8a.
A diagram illustrating the color-corresponding distribution of horizontal line signals to two horizontal registers, Figure 8c is the same as Figure 8a.
A waveform diagram showing horizontal transfer clock pulses and their output signals for the illustrated CCD, and FIG. 9 is a block diagram showing the signal processing circuit of the second embodiment. 101; 102...imaging means (frame transfer type
CCD), 1...imaging section, 2...memory section, 2a
... Signal distribution section, 31 to 33; 34, 35 ... Plural readout transfer paths (horizontal shift register), 4
1 to 43; 44, 45...Output amplifier, 10 to 1
2, 83, 84; 14, 15, 85... Components of noise removal means.

Claims (1)

[Scope of Claims] 1. A color filter with a predetermined color arrangement, a plurality of photoelectric conversion elements for photoelectrically converting imaging light incident from a subject through this color filter, and for outputting a signal from each photoelectric conversion element. a two-channel horizontal transfer section, and a distribution section that distributes the output from each photoelectric conversion element to each of the horizontal transfer sections and supplies the output corresponding to a single color to at least one horizontal transfer section. an imaging means having the above, a driving means for forming a drive pulse for driving each of the horizontal transfer sections in the same phase to output the output from each of the photoelectric conversion elements in the same phase; a luminance signal forming means for adding the output signals by shifting the phases of the superimposed output signals by a predetermined amount; a removing means for removing the driving pulse from the luminance signal outputted by the luminance signal forming means; and an output from each of the horizontal transfer sections. 1. An imaging apparatus comprising: color signal forming means for subtracting the respective output signals from each other to remove the drive pulse, and for generating color signals and distributing these color signals to a plurality of channels.