JPH04206597A - Printed wiring board - Google Patents
Printed wiring boardInfo
- Publication number
- JPH04206597A JPH04206597A JP2328863A JP32886390A JPH04206597A JP H04206597 A JPH04206597 A JP H04206597A JP 2328863 A JP2328863 A JP 2328863A JP 32886390 A JP32886390 A JP 32886390A JP H04206597 A JPH04206597 A JP H04206597A
- Authority
- JP
- Japan
- Prior art keywords
- component
- board
- soldering
- solder
- land
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はチップ部品のはんだ接続信頼性を向上したプリ
ント配線基板に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a printed wiring board with improved solder connection reliability of chip components.
従来、基板上にチップ部品をはんだ接続する技術には、
特開昭６１−１５２０９１号公報あるいは、特開昭６１
−１５２０９２号公報に記載のように、基板の同一面の
はんだ付はランド上に、はんだペーストを塗布後、チッ
プ部品を搭載し、リフローはんだ付けを行なっていた。Conventionally, the technology for soldering chip components on a board includes:
JP-A-61-152091 or JP-A-61
As described in Japanese Patent Application No. 152092, soldering on the same side of the board was performed by applying solder paste on the lands, mounting chip components, and performing reflow soldering.
上記従来技術では、チップ部品の電極が両端部だけでな
く、部品底面にも電極を具備する場合はんだ接続信頼性
のため、はんだ量を確保すると。In the above-mentioned conventional technology, when the chip component has electrodes not only on both ends but also on the bottom surface of the component, a sufficient amount of solder must be ensured to ensure solder connection reliability.
はんだ溶融後の部品中央面あるいは底面のはんだ盛り上
がりにより、部品傾きや部品倒れが発生し、逆に部品倒
れを防止するため、はんだ量を減らすことにより、はん
だ接続の信頼性を低下させるという問題があった。After the solder melts, the solder builds up on the center or bottom of the component, causing the component to tilt or fall.In order to prevent the component from falling, reducing the amount of solder reduces the reliability of the solder connection. there were.
本発明の目的は、かかる問題を解消し、両端以外に底面
にも電極を具備するチップ部品の、はんだ接続信頼性を
向上したプリント配線基板を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to solve this problem and provide a printed wiring board with improved solder connection reliability of a chip component having electrodes on the bottom surface in addition to both ends.
上記目的を達成するために、リフロー工程にて基板に部
品接続する際、チップ部品量端電極の基板はんだ付はラ
ンドは搭載面外装パターンに設け、チップ部品底面電極
の基板はんだ付ランドは基板内層に、かつそのランドは
チップ部品幅より長くしたものである。To achieve the above objective, when connecting components to a board in the reflow process, the land for soldering the end electrode of the chip component is placed on the exterior pattern of the mounting surface, and the land for soldering the bottom electrode of the chip component is placed on the inner layer of the board. , and the land is longer than the width of the chip component.
はんだペーストを塗布、部品実装しりフローはんだ付け
する際、チップ部品両端電極の基板はんだ付はランドは
基板外層面に形成していることに対し、チップ部品底面
電極の基板はんだ付ランドは基板内層にあるため、部品
を搭載することにより、部品底面電極はんだ付はランド
は部品搭載面より低位となる為、部品底面電極と基板内
層電極間に空間が発生する。塗布したはんだペーストを
溶融すると、そのはんだはチップ部品と内層電極間の空
間に留まり、チップ部品中央部をはんだで持ち上げ１部
品倒れを発生させることなく、かつはんだ付は信頼性が
確保できるはんだ量を確保したはんだ付けが可能となる
。また、チップ部品幅より基板内層はんだ付はランドを
長くすることにより、目視によるはんだ付はチエツク、
及びはんだ付は補修が可能となる。When applying solder paste and mounting components during flow soldering, the land for soldering the electrodes at both ends of the chip component is formed on the outer layer of the board, whereas the land for soldering the bottom electrode of the chip component is formed on the inner layer of the board. Therefore, when a component is mounted, the land for soldering the bottom electrode of the component is lower than the component mounting surface, and a space is created between the bottom electrode of the component and the inner layer electrode of the board. When the applied solder paste is melted, the solder stays in the space between the chip component and the inner layer electrode, and the center of the chip component is lifted up with solder to prevent the component from falling over, and to ensure reliability in soldering. This makes it possible to perform soldering with a high degree of accuracy. In addition, by making the land longer when soldering the inner layer of the board than the width of the chip component, visual soldering can be checked.
And soldering can be repaired.
以下、本発明の一実施例を第１図〜第５図により説明す
る。An embodiment of the present invention will be described below with reference to FIGS. 1 to 5.
第１図は、部品両端部以外に、部品底面に電極を具備す
るチップ部品をはんだ付けした本実施例の状態を示し、
第２図はそのチップ部品を示す。FIG. 1 shows the state of this embodiment in which a chip component having electrodes on the bottom surface of the component is soldered in addition to both ends of the component.
FIG. 2 shows the chip components.
両端電極４の池底面電極５を具備するチップ部品３を第
３図に示すプリント配線基板のチップ部品はんだ付はラ
ンド１及び内層はんだ付はラント２にリフローはんだ付
けする時、第４図に示す様にまず適当量のクリームはん
だ７をはんだ付はランド１及び内層はんだ付はランド２
上に塗布し、この上にチップ部品３を搭載する。チップ
部品両端電極４の基板はんだ付はラント１は基板外層面
にあるが、チップ部品３の底面電極５の基板はんだ付は
ランド２は基板内層にあるため、空間６が発′生ずる。The chip component 3 having the bottom electrode 5 of the electrodes 4 at both ends is shown in FIG. 3. The soldering of the chip component on the printed wiring board is as shown in FIG. First, apply an appropriate amount of cream solder 7 to land 1 for soldering and land 2 for inner layer soldering.
The chip component 3 is mounted on top of the coating. When soldering the electrodes 4 at both ends of the chip component to the substrate, the runt 1 is on the outer layer of the substrate, but when soldering the bottom electrode 5 of the chip component 3 to the substrate, the land 2 is on the inner layer of the substrate, so that a space 6 is generated.
塗布したはんだペースト７及び８を溶融すると、第１図
に示す様に、はんだ付ランド１上のはんだ７′はチップ
部品３の両端電極４と接続し、溶融したはんだ８′はチ
ップ部品３と内層はんだ付ランド２間の空間６に留まり
はんだ付けされる。これによりチップ部品３の中央部を
、はんだで持ち上げ部品倒れを発生させることなくかつ
。When the applied solder pastes 7 and 8 are melted, the solder 7' on the soldering land 1 is connected to the electrodes 4 at both ends of the chip component 3, and the melted solder 8' is connected to the chip component 3, as shown in FIG. It remains in the space 6 between the inner layer soldering lands 2 and is soldered. As a result, the center part of the chip component 3 can be lifted with solder without causing the component to fall.
はんだ付は信頼性が維持できるはんだ量を確保できる。Soldering can ensure the amount of solder that maintains reliability.
また、第５図の上面図に示す様に、チップ部品３の幅よ
り基板内層はんだ付ランド２を長くすることにより目視
によるはんだ付はチエツク及びはんだ付は補修が可能と
なる。Further, as shown in the top view of FIG. 5, by making the board inner layer soldering land 2 longer than the width of the chip component 3, it becomes possible to visually check and repair the soldering.
本発明は、以上説明したように構成されているので以下
に記載されるような効果を奏する。Since the present invention is configured as described above, it produces the effects described below.
チップ部品底面電極のはんだ付はランドを基板内層に形
成するため、部品とはんだ付はランド間に空間層が発生
する。これにより、はんだ付は信頼性が維持できるはん
だ量が確保できる。When soldering the bottom electrode of a chip component, a land is formed on the inner layer of the board, so when soldering the component, a space layer is generated between the lands. This makes it possible to secure an amount of solder that can maintain reliability during soldering.
また、はんだによるチップ部品中央部の盛り上がりがな
いため、部品の傾きや、部品倒れの発生の可能性が少な
い。Furthermore, since there is no bulge in the center of the chip component due to solder, there is less possibility of the component tilting or falling down.
さらに、基板内層のはんだ付ランドは、部品幅より長く
形成するため、目視にてはんだ付は状態のチエツクが可
能であり、また、はんだ補修も容易に実施できる。Furthermore, since the soldering lands on the inner layer of the board are formed to be longer than the width of the component, it is possible to check the soldering condition visually, and the soldering can be easily repaired.
第１図は本発明の一実施例の部品搭載しはんだ付けした
状態の断面図、第２図は部品両端部の他。
部品底面に電極を具備するチップ部品の斜視図、第３図
は本発明の基板断面図、第４図は第３図にクリームはん
だ、チップ部品を搭載した状態の断面図、第５図は本発
明のチップ部品を搭載した状態の上面図である。
１・・基板表面はんだ付ランド、
２・・・基板内層はんだ付ランド、
３・・・チップ部品、 ４・・・チップ部品両端電極
、５・・・チップ部品底面電極、
６・・・空間層、 ７・・・はんだペースト、
８・・・はんだペースト、７′・・・はんだ。
８′・・・はんだ。
阜 Ｉ 図
阜 ２ 図
＄３図FIG. 1 is a sectional view of an embodiment of the present invention in which parts are mounted and soldered, and FIG. 2 shows both ends of the parts and other parts. A perspective view of a chip component equipped with an electrode on the bottom of the component, FIG. 3 is a cross-sectional view of the substrate of the present invention, FIG. 4 is a cross-sectional view of the chip component mounted with cream solder in FIG. 3, and FIG. FIG. 3 is a top view of a state in which the chip component of the invention is mounted. 1... Board surface soldering land, 2... Board inner layer soldering land, 3... Chip component, 4... Chip component both end electrodes, 5... Chip component bottom electrode, 6... Space layer , 7...Solder paste,
8...Solder paste, 7'...Solder. 8'...Solder. Fu I Figure Fu 2 Figure $3
Claims (1)
部品をはんだ付けする多層基板において、部品両端部の
基板はんだ付ランドは基板外層に、部品底面の基板はん
だ付ランドは基板内層に設け、かつ部品幅よりも長くし
たことを特徴とするプリント配線基板。1. In a multilayer board to which a chip component is soldered, which has electrodes on both ends of the component and on the bottom of the component, the board soldering lands at both ends of the component are provided on the outer layer of the board, the board soldering lands on the bottom of the component are provided on the inner layer of the board, and the width of the component is A printed wiring board characterized by being longer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2328863A JPH04206597A (en) | 1990-11-30 | 1990-11-30 | Printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2328863A JPH04206597A (en) | 1990-11-30 | 1990-11-30 | Printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04206597A true JPH04206597A (en) | 1992-07-28 |
Family
ID=18214939
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2328863A Pending JPH04206597A (en) | 1990-11-30 | 1990-11-30 | Printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04206597A (en) |
-
1990
- 1990-11-30 JP JP2328863A patent/JPH04206597A/en active Pending
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