JPH0420699U - - Google Patents
Info
- Publication number
- JPH0420699U JPH0420699U JP5973390U JP5973390U JPH0420699U JP H0420699 U JPH0420699 U JP H0420699U JP 5973390 U JP5973390 U JP 5973390U JP 5973390 U JP5973390 U JP 5973390U JP H0420699 U JPH0420699 U JP H0420699U
- Authority
- JP
- Japan
- Prior art keywords
- address
- section
- shift section
- shift
- address data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Semiconductor Memories (AREA)
Description
第１図は本考案によるアドレス回路の一実施例
を示すブロツク図、第２図ａ〜ｃは各々同実施例
の効果を説明するための平面図、第３図はメモリ
容量とパツケージとの関係を示す表図、第４図ａ
〜ｃは各々各メモリ容量に対するパツケージの一
例を示す平面図である。
２……内部クロツク発生部（クロツク発生回路
）、４ａ〜４ｎ……シフト部（ラツチ回路）、６
……アドレス指定部（Ｘデコーダ）、８……アド
レス指定部（Ｙデコーダ）、１１……アドレス入
力端子、１３……チエツク端子。
FIG. 1 is a block diagram showing an embodiment of the address circuit according to the present invention, FIGS. 2 a to c are plan views for explaining the effects of the embodiment, and FIG. 3 shows the relationship between memory capacity and package. Table showing, Figure 4a
-c are plan views each showing an example of a package for each memory capacity. 2... Internal clock generation section (clock generation circuit), 4a to 4n... Shift section (latch circuit), 6
. . . address designation section (X decoder), 8 . . . address designation section (Y decoder), 11 . . . address input terminal, 13 . . . check terminal.
Claims (1)
次、シフトしてパラレルなアドレスデータを生成
するシフト部と、このシフト部によつて得られた
パラレルなアドレスデータに基づいてアドレス指
定を行なうアドレス指定部とを備えたことを特徴
とするアドレス回路。 (2) 前記シフト部はラツチ回路を備え、該ラツ
チ回路によるアドレスデータのラツチが終了した
後、クロツク信号に基づいて次のアドレスに進め
ることを特徴とする請求項(1)記載のアドレス回
路。 (3) 前記シフト部はリセツトパルスによりリセ
ツトされることができることを特徴とする請求項
(1)又は(2)記載のアドレス回路。 (4) 前記シフト部はシフト動作によつて得られ
た最終データを外部に出力する請求項(1)記載の
アドレス回路。 (5) 前記シフト部は内部クロツク発生部を有し
、この内部クロツク発生部によつて得られたクロ
ツク信号に基づいて外部からシリアルなアドレス
データを取り込む請求項(1)記載のアドレス回路
。[Claims for Utility Model Registration] (1) A shift section that sequentially shifts input serial address data to generate parallel address data, and a shift section that generates parallel address data based on the parallel address data obtained by the shift section. 1. An address circuit comprising: an address designation section that performs address designation. (2) The address circuit according to claim 1, wherein the shift section includes a latch circuit, and after the latch circuit finishes latching the address data, the shift section advances to the next address based on a clock signal. (3) Claim characterized in that the shift section can be reset by a reset pulse.
Address circuit described in (1) or (2). (4) The address circuit according to claim (1), wherein the shift section outputs final data obtained by the shift operation to the outside. (5) The address circuit according to claim 1, wherein the shift section has an internal clock generating section, and takes in serial address data from the outside based on a clock signal obtained by the internal clock generating section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5973390U JPH0420699U (en) | 1990-06-06 | 1990-06-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5973390U JPH0420699U (en) | 1990-06-06 | 1990-06-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0420699U true JPH0420699U (en) | 1992-02-20 |
Family
ID=31586491
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5973390U Pending JPH0420699U (en) | 1990-06-06 | 1990-06-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0420699U (en) |
-
1990
- 1990-06-06 JP JP5973390U patent/JPH0420699U/ja active Pending
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