JPH04211543A - Digital data secret device - Google Patents

Abstract

PURPOSE:To keep digital data secret against any person other than a legal receiver without fail. CONSTITUTION:In a transmission part 1, the initial value for an M sequence signal generation part 14 is changed at a constant cycle based on a secret code 17a inputted from an external device. M sequence bit sequence data 14a at this time and transmission data 11a are added and transmitted in an adder 15. A receiving part 3 changes the secret code from the external device at a constant applicable cycle and generates initial data 33a of an M sequence signal generation part 34. M sequence bit sequence data 34a at this time and receiving data 37a are added and decoded in an adder 35.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital data concealment device, and more particularly to a digital data concealment device for concealing digital data to be transmitted from other than the authorized transmission partner on a transmission path.

0002

2. Description of the Related Art As a so-called encryption method for concealing transmitted digital data, for example, DES (Data Enervation Stand) is widely adopted in the United States.
ard) There is an algorithm. The DES algorithm is an extension of the old encryption algorithm, and is constructed based on transliteration and substitution.

[0003] This DES algorithm has the disadvantage that the algorithm is complicated because it uses transliteration and substitution methods, and the circuit scale becomes large for data randomization.

0004

[Object of the Invention] Therefore, the present invention has been made to eliminate the drawbacks of the conventional ones, and its purpose is to provide a digital data concealment system that can conceal digital data with a simple circuit configuration. The goal is to provide equipment.

[0005]

According to the present invention, there is provided a digital data concealing device for concealing digital data to be transmitted on a transmission path from persons other than the authorized transmission party, the device comprising a transmitter and a receiver, The machine uses an M-sequence signal generation means and a secret code input from the outside as initial values.
initial data generating means for generating initial data for the M-sequence signal generating means while sequentially varying it at a predetermined period;
Adding means for adding the M-sequence bit sequence data from the M-sequence signal generating means and the digital data to be transmitted by addition modulo 2 to obtain concealed data;
transmitting means for superimposing periodic data indicating the predetermined period on the confidential data, and the receiver
a second M-sequence signal generating means having the same configuration as the sequence signal generating means; and generating the second M-sequence signal while sequentially varying it at the period using a secret code inputted from the outside and the same as the secret code as an initial value; initial data generating means for generating initial data of the means, M-sequence bit sequence data from the second M-sequence signal generating means and the received concealed data, which are added together by addition modulo 2, and then decoded; A digital data concealment device is obtained, which is characterized in that it includes an adding means for converting the digital data into digits.

[0006]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. Transmission digital data and a secret code are input to the transmitter 1, and the transmitted digital data is made secret according to the secret code and sent to the transmission path 2. The receiving unit 3 receives the confidential data transmitted via the transmission path 2, and
According to the cipher code input to the cipher code, the digital data is decrypted by performing the reverse process of ciphering.

[0008] When the secret codes input to the transmitter 1 and the receiver 3 are the same, the transmitted digital data is correctly decoded as received digital data. On the other hand, when the secret codes do not match, the data is decoded as incorrect digital data. Therefore, if the secret code is known only to the communication partners, a third party will not be able to decode the correct digital data, and therefore it is possible to secretly transmit the digital data.

Next, the transmitter 1 will be explained. The secret code input to the input terminal 18 is input to the initial value generation circuit 13 and stored. The initial value generation circuit 13 receives the frame pulse 16d from the pattern generation circuit 16 and the load signal 16a that sets the initial value of the M-sequence signal generation circuit 14. The code is output as the initial value 13a. Also,
The initial value 13a is changed by adding a certain value to the secret code every time the load signal 16a is generated. However, the load signal 16a is the frame pulse 16
It is a signal with a short period compared to d.

The M-series signal generation circuit 14 generates an initial value 13a every time it receives a load signal 16a from the pattern generation circuit 16.
The M-sequence signal 14a is taken in, the values of the registers constituting the M-sequence signal generator are initialized, and the M-series signal 14a is supplied to the adder 15.

The transmitted digital data is added to the M-sequence signal 14a by the modulo-2 adder 15 via the input terminal 11, and is multiplexed with the frame synchronization signal 16b in the multiplexing circuit 17 as secret data 15a, and then sent to the output terminal. 1
2 to the transmission line 2.

The pattern generation circuit 16 is a circuit that generates a frame for synchronizing transmitted digital data and an M-sequence signal in a transmitting section and a receiving section, and multiplexes a frame synchronization signal 16b for synchronizing in the receiving section. 17, and also outputs a control signal 16c indicating a multiplexing position in order to multiplex frame synchronization signals. It also outputs a frame pulse 16d and a load signal 16a for initial value setting for each synchronization frame.

Next, the receiving section 3 will be explained. Receiving section 3
Then, confidential data is received via the input terminal 32 and supplied to the frame synchronization circuit 36 and the separation circuit 37. The frame synchronization circuit 36 establishes frame synchronization by detecting the frame synchronization signal 16b multiplexed by the transmitter 1. When frame synchronization is detected, a frame pulse 36d is sent to the initial value generation circuit 13 in response to the transmitter pattern generation circuit 16 using the frame synchronization as a reference, and an initial value load signal 3 is sent to the initial value generation circuit 13.
6a to the initial value generation circuit 33 and the M-sequence signal generation circuit 34, respectively, and also supplies the control signal 36b for separating the frame synchronization signal to the separation circuit 37.

The initial value generating circuit 33 inputs the secret code via the input terminal 38 and transmits the secret code to the initial value generating circuit 13 of the transmitter 1.
The initial value 33a is set to the M-sequence signal generation circuit 3 by the same operation as
Supply to 4. The M-sequence signal generation circuit 34 is the M-sequence signal generator of the transmitter 1
The M sequence signal 34a is generated by the same operation as the sequence signal generator 14.
is supplied to the adder 35.

Confidential data 32 input to separation circuit 37
a is separated from the frame synchronization signal, and an M-sequence signal 34 is added to the modulo-2 adder 35 as secret data 37a.
a and output terminal 3 as received digital data.
1.

As the M-sequence signal generation circuits 14 and 34, the well-known L
FSR (Linear Feedback Shift Register: Line
ar Feedback Shift Register
r) type of circuit configuration can be adopted.

Here, in the M-series signal generation circuit, all 0 codes are prohibited, so 1 bit is always set to the initial value "1".
Therefore, for example, when considering an 8-bit binary code as the secret code, it is necessary to have an LFSR configuration with nine or more stages.

For example, as shown in FIG. 2, a 9-bit shift register 21 is provided, and the fourth bit r4 and the ninth bit from the right are
The bit r9 is added by the adder 22 modulo 2, and the addition output is fed back to the input of the 9th bit r9, and the 1st bit r1 is added to the M-sequence signal k.
i (14a/34a).

The initial value 13a/33a of the 9-bit shift register 21 is generated from the initial value generating circuit 13/33 in accordance with the secret code 17a/38a.

In the 9-bit LFSR configuration shown in FIG. 2, 511 different patterns are repeatedly generated from the initial value loaded with the maximum period, so the first bit r1 is used as the M-sequence signal. This means that it can be derived.

It should be noted that the concealed data ci from the transmitter 1 is expressed as ci = mi + ki (1), where mi is the transmitted digital data and ki is the M-sequence signal. Note that + indicates addition modulo 2.

Furthermore, since the received data at the receiving section 3 is ci in equation (1), the addition output 35a at the adder 35 is ci +ki = (mi +ki)+
ki = mi (2), which is the same as the digital data mi to be transmitted, making it possible to decrypt the encrypted data.

As mentioned above, if the secret code is 8 bits, 256 initial settings are possible, and if the secret codes do not match in both the transmitting and receiving sections, the change phases of the M-sequence signals will not match. , the digital data will not be restored correctly and the secrecy function will be activated. Of course, the longer the secret code is, the better the concealment effect will be.

FIG. 3 is a block diagram of another embodiment of the present invention, in which parts equivalent to those in FIG. 1 are designated by the same reference numerals. First, the transmitting device 1 will be explained. The secret code input to the input terminal 18 is input to the initial data generation circuit 13 and stored in the register 131.

Pattern generation circuit 192 of multiplexing circuit 19
generates timing signals for configuring multiplexed data. The pattern generation circuit 192 outputs a frame pulse 192b, a subframe pulse 192a, a frame synchronization signal 192c, and a switching signal 192 from the switching device 193.
generate d.

The frame pulse 192b is supplied to the counter 134, register 133, M-sequence signal generator 14, and parallel/serial converter 191 of the initial data generation circuit 13, respectively.

The subframe pulse 192a is supplied to a parallel/serial converter 191, and the frame period signal 192c and switching signal 192d are supplied to a switch 193.

The counter 134 receives the frame pulse 192b.
The count value 134a is supplied to the register 133 and the parallel/serial converter 191, and is taken in by the frame pulse 192b for each secret frame. The count value taken into the register 133 is input to the adder 132 as a secret code conversion value 133a, and is added to the secret code of the register 131 by the adder 132 and converted.

The converted secret code 132a is supplied to the M-sequence signal generation circuit 14. M-series signal generation circuit 14
takes in the secret code 132a converted by the frame pulse 192b into a shift register for generating an M-sequence signal, and generates an M-sequence signal based on the clock until the next frame as initial data of the M-sequence signal. M that occurred
The sequence signal 14a is supplied to an adder 15.

Transmission digital data is input from input terminal 11 and supplied to adder 15 . The adder 15 performs a modulo-2 addition of the M-sequence signal 14a to conceal the signal and connects it to the switch 193 of the multiplexing circuit 19.

The count value taken into the parallel/serial converter 191 is input to the switch 193 as serial data by the subframe pulse 192a. The switch 193 switches the secret digital data 15a by the switch signal 192d.
, the count value 134a and the frame synchronization signal 192c are switched and multiplexed, and sent to the transmission line 2 via the output terminal 12 as multiplexed data 193a.

Next, the receiving device will be explained. The receiving device 3 receives the multiplexed data via the input terminal 32,
It is connected to a hoom synchronization circuit 393, a serial/parallel converter 391, and a register 392.

The frame synchronization circuit 393 detects a frame synchronization signal from the received multiplexed data, establishes frame synchronization, and generates timing signals for separating signals. From the frame synchronization circuit 393, the frame pulse 3
The subframe pulse 393a is supplied to the M-series signal generation circuit 34, the subframe pulse 393b is supplied to the serial/parallel conversion circuit 391, and the data enable signal 393c is supplied to the register 392.

The serial/parallel converter 391 takes in a 32-bit count value using a subframe pulse 393b synchronized with the multiplexed data, and supplies it to the adder 332 as a 32-bit parallel signal.

Similarly, the register 392 separates only the digital data concealed by the data enable signal 393c synchronized with the multiplexed data and supplies it to the modulo-2 adder 35.

The secret code is input from the input terminal 38 and stored in the register 331 of the initial data generation circuit 33. This secret code is usually entered at the beginning of communication. The stored secret code is sent to the adder 332
and is added to the count value separated for each concealed frame, and is added to the M-sequence signal generation circuit 34 having the same configuration as the transmitter.
supplied to

The M-series signal generation circuit 34 takes in the secret code 332a converted by the frame pulse 393a into the system register for M-series signal generation, and uses it as initial data of the M-series signal based on the clock until the next frame. Generates a series signal.

The generated M-sequence signal 34a is supplied to an adder 35, which performs modulo-2 addition with the concealed data, and outputs the resultant signal to the output terminal 31 as received digital data.

FIG. 4 is a time chart showing the operation of the embodiment shown in FIG. In the example shown in FIG. 4, 64 control bits (Ci) are arranged at equal intervals in the frame.
The frame structure is such that frame synchronization signals F1 to F32 are multiplexed to odd numbered bits and count values W1 to W32 are multiplexed to even numbered bits, respectively.
2 constitutes a frame synchronization pattern, which is repeated every frame.

The frame synchronization circuit 393 of the receiver 3 detects this frame synchronization pattern and generates a timing signal necessary for the receiver 3 in synchronization with the received multiplexed data.

The count value 134a is multiplexed into W1 to W32, but the count value 134a transmitted in the i-th frame is delayed by one frame by the register 133, and the count value 134a is transmitted in the i-th frame.
Used to generate M-sequence signals for frames. Therefore, in the receiving device 3, the count value used for the i+1th frame is received during the i-th frame, and is used for generating the M sequence signal in the receiving device 3 in the i+1th frame, and the transmission and reception are synchronized.

In the embodiment, a 32-bit secret code was used so that 232 codes could be used, but in this case,
M-sequence signal generator 14 consisting of a 32-stage shift register
, 34, and the pattern length is very long (232-1) bits, and may not repeat once in the secret frame. In addition, if a transformed value is not used, an M-sequence signal with the same phase in each frame will be generated, but if a transformed value is used, the phase changes in each frame and the anonymized data is further randomized. That will happen.

[0043] The number of bits of the secret code is 32 in this embodiment.
Although it is assumed to be bits, it can be realized with any number of bits.

[0044]

[Effects of the Invention] As explained above, according to the present invention, M
Since the transmitted digital data is scrambled using a sequence signal and the phase of this M-sequence signal is changed using a cipher code, it is impossible to receive the transmitted digital data unless the cipher code is known. By changing the phase, the concealment ability is further increased. Therefore, there is an effect that digital data can be concealed with a simple circuit configuration.

[Brief explanation of the drawing]

FIG. 1 is a system block diagram of one embodiment of the present invention.

FIG. 2 is a diagram showing a specific example of an M-sequence signal generation circuit.

FIG. 3 is a system block diagram of another embodiment of the present invention.

FIG. 4 is an operation time chart of the embodiment of FIG. 3;

[Explanation of symbols]

1 Transmission section 2 Transmission line 3 Receiving section 13, 33 Initial value generation circuit 14, 34 M-series signal generation circuit 15, 35 Adder circuit 16, 36 Pattern generation circuit

Claims (5)

[Claims] 1. A digital data concealment device for concealing digital data to be transmitted on a transmission path from persons other than the authorized transmission party, the transmitter comprising a transmitter and a receiver, the transmitter transmitting an M-sequence signal. a generating means; an initial data generating means for generating initial data for the M-sequence signal generating means while sequentially varying it at a predetermined cycle using a secret code inputted from the outside as an initial value; and the M-sequence signal generating means. adding means for adding the M-sequence bit sequence data from the source and the digital data to be transmitted by addition modulo 2 to obtain concealed data; The receiver includes a second M-sequence signal generating means having the same configuration as the M-sequence signal generating means, and a secrecy code inputted from the outside that is the same as the secrecy code as an initial value. initial data generation means for generating initial data for the second M-sequence signal generation means while sequentially varying the cycle; and the received M-sequence bit sequence data from the second M-sequence signal generation means; 1. A digital data concealment device, comprising: an addition means for adding and decoding the encoded data by modulo-2 addition. 2. M-sequence signal generation means, and initial data generation means for generating initial data for the M-sequence signal generation means while sequentially varying it at a predetermined cycle using a secret code inputted from the outside as an initial value. and adding means for adding the M-sequence bit sequence data from the M-sequence signal generating means and the digital data to be transmitted by addition modulo 2 to obtain concealed data, and periodic data indicating the predetermined period. and transmitting means for superimposing the information on the anonymized data and transmitting the anonymized data. 3. An initial stage for generating initial data for the M-sequence signal generation means, using a secret code inputted from the outside as an initial value, while sequentially varying it at a period superimposed on received data. data generating means;
A digital data receiver comprising: an adding means for adding the M-sequence bit sequence data from the sequence signal generating means and the received secret data by modulo-2 addition to obtain digital data. 4. A digital data concealment device for concealing digital data to be transmitted on a transmission path from persons other than the authorized transmission partner, the transmitter comprising a transmitter and a receiver, the transmitter transmitting an M-sequence signal. Generating means generates initial data for the M-sequence signal generating means by adding a conversion value that changes according to a predetermined rule for each predetermined concealed frame to a secret code inputted from the outside. an initial data generating means; an adding means for adding the M-sequence signal bit sequence data from the M-sequence signal generating means and the digital data to be transmitted by modulo-2 addition to obtain concealed data; the receiver includes a second M-sequence signal generator having the same configuration as the M-sequence signal generator; means for detecting the concealed frame synchronization signal from the received signal and separating the concealed data from the converted value; initial data generation means for generating initial data for the second M-sequence signal generation means by adding the converted values separated for each concealed frame; and an M-sequence bit sequence from the second M-sequence signal generation means. A digital data concealing device comprising: an adding means for adding and decoding data and the separated concealed data by modulo-2 addition. 5. An M-sequence signal generating means, which adds a conversion value that changes according to a predetermined rule for each predetermined concealed frame to a concealment code input from the outside to generate the M-sequence signal. Initial data generation means for generating initial data of the generation means, M-sequence signal bit sequence data from the M-sequence signal generation means, and digital data to be transmitted are added together by addition modulo 2 to generate concealed data. 1. A digital data transmitter comprising: an adding means for transmitting the concealed data; and a transmitting means for multiplexing and transmitting the concealed data, the concealed frame synchronization signal, and the converted value.