JPH04212466A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To manufacture a field effect transistor high in reliability even if it is miniaturized by a method wherein the field concentration between a source and drain is restrained without enhancing the short channel effect. CONSTITUTION:A protrusion 1a is formed on a P type semiconductor substrate 1 and then a gate insulating film 4 and a gate electrode 5 are formed on the protrusion 1a while n type impurities are implanted in inner sides of the protrusion 1a to form LDD n<-> layers 2a, 2b. Later, a gate leading-out electrode 8c, a source leading-out electrode 8a and a drain leading-out electrode 8b are formed.

Description

[Detailed description of the invention]

[Object of the invention]

0002

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to the structure of a field effect transistor.

0003

2. Description of the Related Art Recently, semiconductor integrated circuits have become increasingly highly integrated, and semiconductor elements have become significantly smaller.

Among these, miniaturization of field effect transistors (FETs) such as MOS type FETs is a typical example, and trial production of elements on the submicron order is actively being carried out.

However, as FETs, particularly MOSFETs, become smaller, local electric field concentration occurs between the source and drain, leading to the generation of hot carriers. As a result, the device malfunctions, resulting in a complete loss of reliability as a semiconductor device.

[0006] LDD (
F of Lightly Doped Drain) structure
There is ET. Figure 79 shows the n-channel M of the conventional LDD structure.
FIG. 2 is a cross-sectional view showing the structure of an OS type FET. As shown in this figure, an n-type source 143a and a drain 1 are provided on the surface of a p-type semiconductor substrate 141 via a channel portion 141a.
43b is formed. In addition, an n- type conductive layer (LDDn- layer) 14 having a lower impurity concentration than the source 143a and drain 143b on the side of the channel part 141a.
2a and 142b are formed, respectively. Furthermore, a gate insulating film 144 is formed on the surface of the substrate 141, and a gate electrode 145 is formed on the channel portion 141a via this gate insulating film 144. Here, the LDDn-
Parts of layers 142a and 142b are connected to this gate electrode 1.
It overlaps with part of 45.

Furthermore, the gate electrode 145 and the source 143
a and the drain 143b are insulated by an interlayer insulating film 147 formed thereon and connected to respective electrodes 148. Further, 149 is a nitride film formed on the side wall of the gate electrode 145, and 146 is a field insulating film for element isolation. If the FET has such an LDD structure, the LDD
Since the n- layers 142a and 142b are interposed between the source 143a and drain 143b and the channel 141a, electric field concentration between them can be alleviated.
However, the above LDD structure FET has the following problems. In other words, with the miniaturization of semiconductor elements,
It becomes impossible to secure an overlapping area between the LDDn- layer and the gate electrode, and electric field concentration between the source and drain tends to occur. For this reason, there was a problem in that reliability as a semiconductor device was impaired. Conversely, in order to increase the overlap area, LDDn
- If an attempt is made to form a wide layer below the gate electrode, there is a problem in that the channel length becomes short and the short channel effect increases.

[0008]

As described above, conventional field effect transistors have had the problem that local electric field concentration tends to occur between the source and drain. Moreover, when attempting to solve this problem, there is a problem of increasing the short channel effect.

The present invention has been made in view of the above-mentioned circumstances, and provides a field effect transistor that suppresses electric field concentration between the source and drain without increasing the short channel effect and is highly reliable even when miniaturized. The purpose is to

[Configuration of the invention]

[0011]

[Means for Solving the Problems] Therefore, the semiconductor device of the present invention includes a semiconductor substrate having a step portion formed on its surface, and a pair of semiconductor substrates having a conductivity type opposite to that of the semiconductor substrate formed on the side wall of the step portion. and a first conductive layer of the same conductivity type as the first conductive layer, which is formed on a surface portion of the semiconductor substrate excluding the stepped portion so as to be connected to the pair of first conductive layers, respectively. a pair of second conductive layers having higher conductivity than this conductive layer, an insulating film formed on the surface of the stepped portion, and facing the first conductive layer via the insulating film, and a control electrode formed to cover the stepped portion.

The present invention also provides a step of forming a step portion on a semiconductor substrate of one conductivity type, and forming a pair of first conductive layers of a conductivity type opposite to that of the substrate so as to face sidewalls of the step portion. forming a pair of second conductive layers connected to each of the first conductive layers and having higher conductivity than the first conductive layers on the substrate surface on both sides of the stepped portion; a step of forming an insulating film on the surface of the substrate on which the stepped portion and the second conductive layer are formed; forming a control electrode covering the stepped portion via the insulating film formed on the stepped portion; A method of manufacturing a field effect transistor is provided.

[0013]

According to the semiconductor device of the present invention, a pair of first conductive layers having conductivity types opposite to that of the semiconductor substrate are formed on the sidewalls of the stepped portion formed on the surface of the semiconductor substrate. Since the control electrode is provided so as to cover the first conductive layer, it is possible to increase the overlapping area between the control electrode and the first conductive layer. Therefore, electric field concentration does not occur between the pair of second conductive layers, and generation of hot carriers is prevented. Therefore, malfunctions of the elements do not occur, and the reliability of the semiconductor device is improved. Furthermore, in the field effect transistor having this structure, since the channel is formed on the surface of the stepped portion between the pair of first conductive layers, the channel will not become short and no short channel effect will occur.

Further, according to the method of the present invention, a highly reliable field effect transistor can be manufactured without causing the short channel effect or electric field concentration as described above.

[0015]

[Embodiment] Hereinafter, an n-channel MOS type F according to an embodiment of the present invention will be described.
ET will be explained in detail with reference to the drawings.

Embodiment 1 FIG. 1 is a cross-sectional view showing the structure of an n-channel MOS FET as a first embodiment of a field effect transistor according to the present invention.

In this figure, reference numeral 1 denotes a p-type semiconductor substrate, and a convex protrusion 1a is formed on this semiconductor substrate 1. As shown in FIG. A pair of n- type conductive layers (LDDn- layers) 2a and 2b are formed as a pair of first conductive layers so as to face each other on both sides of the side wall portion of the projection 1a. moreover,
On the surface of the semiconductor substrate 1 on both sides of the protrusion 1a, n-type source and drain diffusions having a higher impurity concentration (that is, higher conductivity) than the LDD n- layers 2a and 2b are formed as a pair of second conductive layers. Layers 3a and 3b are formed, which connect to LDDn- layers 2a and 2b, respectively.

On the other hand, an insulating film 4 is formed on the protrusion 1a and the surface of the semiconductor substrate 1, and a gate electrode 5 is formed on the protrusion 1a so as to cover the protrusion 1a. Also,
An interlayer insulating film 7 is provided on the element having the above structure, and electrodes 8a, 8b, and 8c for drawing out the source 3a, drain 3b, and gate electrode 5, respectively, are formed penetrating the interlayer insulating film 7.

According to the FET having the above structure, since the gate electrode 5 widely covers the LDDn- layers 2a and 2b,
Compared to conventional FETs with an LDD structure, local electric field concentration between the source and drain is suppressed, thereby preventing the generation of hot carriers. Furthermore, at this time, channel section 1
The short channel effect can be suppressed without shortening the length of b.

Next, a method of manufacturing the field effect transistor according to the first embodiment of the present invention described above will be explained.

FIGS. 2 to 9 are process cross-sectional views showing the manufacturing process of the field effect transistor according to the embodiment of the present invention described above.

First, as shown in FIG. 2, a silicon oxide film 21 is deposited by the CVD method on a p-type silicon substrate 1 whose surface has been oxidized, and a resist pattern 22 is further formed on it to form a gate formation area. cover.

Next, as shown in FIG. 3, using the resist pattern 22 as a mask, the silicon oxide film 21 except under the resist pattern 22 is selectively removed using anisotropic etching.

Next, as shown in FIG. 4, the resist pattern 22 is removed and anisotropic etching is performed using the silicon oxide film 21 as a mask to form a convex projection 1a on the substrate 1. I do. Note that this height is assumed to be very low (for example, about several percent of the gate length).

Furthermore, as shown in FIG. 5, silicon oxide films 23a and 23b are formed on the exposed surface of the silicon substrate 1, and an impurity layer 24 of a conductivity type opposite to that of the silicon substrate 1, that is, an n-type is formed on the substrate 1. On the other hand, ions are implanted obliquely by the rotational ion implantation method. As a result, as shown in this figure, a lightly doped source portion (LDDn- layer) 2a and a lightly doped drain portion (LDD- layer) 2b are formed on the side wall portion of the projection 1a. Here, the silicon oxide films 23a and 23b are used to prevent damage to the surface of the substrate 1.

Next, as shown in FIG. 6, impurities 25 of the opposite conductivity type, that is, n-type, are ion-implanted perpendicularly to the substrate 1 so as to have a higher concentration than the LDDn- layer. As a result, as shown in this figure, n-type source and drain regions 3a and 3b are formed.

Next, as shown in FIG. 7, the silicon oxide film 21 and the silicon oxide films 23a, 23 are etched.
Remove b.

Furthermore, as shown in FIG. 8, a silicon oxide film 4 that will become a gate insulating film is formed on the surface of the substrate 1, and a conductive layer such as a polycrystalline silicon layer 5 that will become a gate electrode is formed thereon.
Deposit.

Next, as shown in FIG.
Patterning the polycrystalline silicon layer 5 so as to cover a,
Gate electrode 5 is formed.

Finally, after depositing an interlayer insulating film 7 on the entire surface, contact holes are opened in this insulating film 7 to connect to the source 3a, drain 3b, and gate electrode 5, respectively, and the electrode 8
Form a, 8b, and 8c.

In this way, the field effect transistor shown in FIG. 1 is completed.

Embodiment 2 FIGS. 10 to 13 are process cross-sectional views showing another embodiment of the method for manufacturing a field effect transistor of the present invention. below,
In FIGS. 10 to 13, the same parts are denoted by the same reference numerals, and detailed explanations will be omitted.

First, a low concentration source portion (LDDn- layer) 2a,
After a low concentration drain portion (LDD- layer) 2b is formed on the side wall portion of the protruding portion 1a, the entire surface is covered with an insulating film such as a silicon oxide film 31 by, for example, the CVD method, as shown in FIG.

Next, as shown in FIG. 11, by performing anisotropic etching on this silicon oxide film 31, this silicon oxide film 31 is formed on the side wall of the protrusion 1a of the substrate 1.
remain.

Furthermore, as shown in FIG. 12, ions of an n-type impurity 32 are implanted perpendicularly to the substrate 1 using the silicon oxide film 31 on the sidewall described above and the silicon oxide film 21 formed by the CVD method as a mask. LDDn- layer 2a, 2
n-type source and drain with higher impurity concentration than b (
After forming the second conductive layers 33a and 33b, respectively, the silicon oxide film 21 and the silicon oxide films 23a and 23 are
b. The silicon oxide film 31 is removed.

Then, through the same steps as in FIGS. 8 and 9 of the first embodiment, a gate insulating film 4 and a gate electrode 5 are formed, and an electrode 8a is connected to the sources 33a, 33b and the gate electrode 5, respectively. , 8b, 8c, FIG.
The embodiment of the field effect transistor according to the present invention shown in No. 3 is completed.

According to this method, although the process is more complicated than that of the first embodiment, the LDDn- layers 2a, 2
This is effective when you want to make b long. The field effect transistor formed by this method also has substantially the same effect as the field effect transistor shown in the first embodiment.

Embodiment 3 Next, FIGS. 14 to 21 are process cross-sectional views showing still another embodiment of the method for manufacturing a field effect transistor of the present invention.

As shown in FIG. 14, first the silicon substrate 1 is
A silicon oxide film 41 is formed thereon, and a resist pattern 42 is further provided thereon. Furthermore, using this resist pattern 42 as a mask, n-type impurity 43 is ion-implanted perpendicularly to the substrate 1 at high acceleration to form LDD n- layers (first conductive layers) 44a and 44b deep into the substrate 1.
form.

Next, as shown in FIG. 15, the resist pattern 42 and oxide film 41 are removed. Furthermore, Figure 1
6, a silicon oxide film 4 is formed on the entire surface by CVD method.
5, and a resist pattern 46 for forming protrusions thereon is formed so as to straddle the LDDn- layers 44a and 44b.

Next, as shown in FIG. 17, using the resist pattern 46 as a mask, the CVD silicon oxide film 45 is selectively etched and patterned.

Further, as shown in FIG. 18, using the patterned CVD silicon oxide film 45 as a mask, the substrate 1 is anisotropically etched to form convex protrusions 1a. At this time, portions of the LDDn- layers 44a and 44b are left on the side wall of the convex projection 1a and the surface of the substrate 1 on both sides of the side wall.

Next, as shown in FIG. 19, after covering the exposed surface of the substrate 1 with silicon oxide films 47a and 47b, an n-type impurity 48 is applied to the substrate 1 using the CVD silicon oxide film 45 as a mask. ion implantation vertically. As a result, the remaining LDDn-
The LDDn- layers 44a, 44b are overlapped so as not to be offset with the layers 44a, 44b.
N-type source and drain regions (second conductive layers) 49a and 49b each having a higher impurity concentration are formed.
Next, as shown in FIG. 20, a CVD silicon oxide film 45
Then, the silicon oxide films 47a and 47b are removed.

Thereafter, steps similar to those shown in FIGS. 8 and 9 described in the first embodiment are performed to complete the field effect transistor embodiment shown in FIG. 21.

The field effect transistor formed by this method also has substantially the same effects as the first embodiment. However, LD
Compared to the case where the Dn- layer is implanted by oblique ion implantation, there is an advantage that the overlap region with the gate electrode 5 can be widened to the top of the convex portion.

[0046] In this way, the step of forming the step portion on the semiconductor substrate may be performed after forming the first conductive layer and the like on the semiconductor substrate.

Embodiment 4 FIG. 22 is a sectional view showing the structure of a field effect transistor according to a fourth embodiment of the present invention.

This field effect transistor differs from the field effect transistor of the first embodiment shown in FIG. 1 in that the gate electrode is divided into three regions 5a, 5b, and 5c.

That is, as shown in this figure, the gate electrode 5a is connected to the LDD n- layer 2a and the n- layer through the insulating film 4a.
The type source region 3a and the gate electrode 5b are connected to the LDDn- layer 2b and the n-type drain region 3b via the insulating film 4b.
The gate electrodes 5c are formed to face the upper surfaces of the protrusions 1a of the substrate 1 with the insulating film 4c interposed therebetween. Further, the gate electrodes 5a, 5b, 5c are kept at the same potential by an electrode 8c spanning these three regions, and are configured to control carriers flowing through the channel portion 1b and the LDDn- layers 2a, 2b.

This field effect transistor also has the same effects as the field effect transistor of the first embodiment described above.

[0051] Here, the gate electrodes 5a, 5b,
It is also possible to provide independent electrodes on 5c and control the potentials of these three electrodes independently. In this case, it is also possible to expect the effect of moving the location of electric field concentration from the vicinity of the junction between the drain and the channel portion to another location.

Next, the manufacturing process of this field effect transistor will be explained.

FIGS. 23 to 30 are cross-sectional views of this process.

First, as shown in FIG. 23, an oxide film such as silicon oxide 61 which will become the gate insulating film 4c is formed on the p-type silicon substrate 1, and a conductive layer such as a polycrystalline silicon layer 62 which will become the gate electrode 5c is formed thereon. , CVD silicon oxide film 63 are sequentially deposited. Furthermore, a resist pattern 64 is formed on this upper layer, thereby covering the gate formation region. Next, as shown in FIG. 24, this resist pattern 6
4 as a mask, the CVD silicon oxide film 63 is anisotropically etched, and then the resist pattern 64 is removed.

Further, as shown in FIG. 25, using the CVD silicon oxide film 63 as a mask, etching is performed so as to penetrate into the substrate 1, so that a convex projection 1a is formed. As a result, the polycrystalline silicon layer 62
is processed into the gate electrode 5c, and the silicon oxide film 61 is processed into the gate insulating film 4c.

Next, as shown in FIG. 26, the exposed substrate 1
Oxide films, such as silicon oxide films 64a and 64b, are formed on the surface of the gate electrode 5c and the side surfaces of the gate electrode 5c. Furthermore, by rotationally implanting n-type impurities 65 into the substrate 1, the LD
Dn- layers 2a and 2b are formed.

Next, as shown in FIG. 27, impurity 66 is ion-implanted perpendicularly to the substrate 1 to form n-type source and drain regions 3a and 3b.

Next, as shown in FIG. 28, the CVD silicon oxide film 63 and the silicon oxide films 64a and 64b are removed by etching.

Thereafter, as shown in FIG. 29, an insulating film 67 such as a silicon oxide film, which will become the gate insulating films 4a and 4b, is formed on the exposed surface of the substrate 1 and the surface of the gate electrode 5c, and then the gate electrode is formed on the entire surface. A conductive layer 5a, 5b, for example a polycrystalline silicon layer 68, is deposited.

Next, as shown in FIG. 30, polycrystalline silicon layer 68 is left on the sides of gate electrode 5c and protrusion 1a by anisotropic etching, and gate electrodes 5a, 5b are
form.

Finally, in the same manner as in the first embodiment described above, the interlayer insulating film 7 and the contact layers 8a, 8b,
8c is provided.

In this way, a field effect transistor as shown in FIG. 22 is completed.

Note that here, the electrode 8c is the gate electrode 5.
contact holes are formed separately for the gate electrodes 5a, 5b, and 5c, and electrodes are formed independently for each of these gate electrodes 5a, 5b, and 5c. It may be provided.

Embodiment 5 Next, a modification of the structure in which the gate electrode is divided into three parts as in the field effect transistor of the fourth embodiment of the present invention shown in FIG. 22 will be described.

FIGS. 31 to 33 are cross-sectional views of the process.

First, steps similar to those shown in FIGS. 23 to 25 described above are performed to form the projections 1a, and then the CVD silicon oxide film 63 and the silicon oxide films 64a and 64b are selectively removed by etching (FIG. 31).

Next, an insulating film such as a silicon oxide film 71 and a conductive layer such as a polycrystalline silicon layer 72 are sequentially formed over the entire surface (FIG. 32).

Thereafter, as shown in FIG. 33, anisotropic etching is performed to leave the polysilicon layer 72 on the sides of the protrusion 1a of the substrate 1, forming the gate electrode 5c and the gate electrodes 5a and 5b. .

Furthermore, as shown in FIG. 34, n-type impurity 73 is ion-implanted perpendicularly to the substrate 1 using the gate electrodes 5a, 5b, and 5c as masks, and the n-type source and drain regions (second conductive layers) 74a and 74b are formed.

Thereafter, the interlayer insulating film 7 and electrodes 8a, 8b, 8c are provided by performing steps similar to those shown in FIG.

In this way, a field effect transistor is completed as shown in FIG.

This field effect transistor differs from the field effect transistor in the fourth embodiment (FIG. 22) in that the LDDn- layers 2a and 2b are longer than in the field effect transistor in the fourth embodiment described above. This allows for a large overlap area with the control gate 5a or 5b. This field effect transistor also has substantially the same effect as the first embodiment.

Embodiment 6 FIGS. 36 to 41 are process cross-sectional views for explaining a method of manufacturing a field effect transistor according to a sixth embodiment of the present invention.

First, after patterning the CVD silicon oxide film 21 through the same steps as in FIGS. 2 and 3 described above,
After removing the resist pattern 22, isotropic etching is performed using the CVD silicon oxide film 21 as a mask. At this time, the edge portion 21a of the lower surface of the CVD silicon oxide film 21 is exposed, and a tapered projection 1a' is formed on the surface of the substrate 1 (FIG. 36).

Next, as shown in FIG. 37, the exposed surface of the substrate 1 is covered with silicon oxide films 81a and 81b, and n-type impurities 82 are ion-implanted perpendicularly to the substrate 1. As a result, a source 8 is formed on the surface of the substrate 1 as a second conductive layer.
3a and a drain 83b are formed.

At this time, ion implantation is not performed because the CVD film 21 serves as a mask for the taper of the projection 1a'.

Next, as shown in FIG. 38, isotropic etching is performed on the CVD silicon oxide film 21 and the silicon oxide films 81a, 81b to remove the silicon oxide films 81a, 81b.
1b is removed, and the edge portion 21a of the lower surface of the CVD silicon oxide film 21 is removed so that the tapered protrusion 1
Etching is performed until it coincides with the edge of the upper surface of a' (so that the CVD silicon oxide film 21 does not serve as a mask for the taper). Next, as shown in FIG. 39, the exposed surface of the substrate 1 is covered with silicon oxide films 84a and 84b again.
After covering the substrate 1 with n-type impurity 85, rotational ion implantation is performed obliquely to the substrate 1 to form a tapered protrusion 1a.
'LDDn- layer 86a as a first conductive layer on the sidewall part of
, 86b.

Next, as shown in FIG. 40, the CVD silicon oxide film 21 and the silicon oxide film 84a are removed by etching.
, 84b are removed, electrodes are formed by steps similar to those shown in FIGS. 8 and 9, and a field effect transistor is completed as shown in FIG. 41. Note that here, 4' is a gate insulating film, and 5' is a gate electrode.

This field effect transistor is similar to the field effect transistor of the first embodiment, except that the shape of the protrusion is tapered. Further, the method and apparatus in this embodiment have almost the same effects as the method and apparatus in the first embodiment, but the protrusion has a tapered shape compared to the first and second embodiments. This is superior in that electric field concentration is less likely to occur.

Embodiment 7 FIG. 42 is a sectional view showing the structure of a field effect transistor according to a seventh embodiment of the present invention.

This field effect transistor differs from the field effect transistor of the first embodiment shown in FIG. 1 in that the step formed on the surface of the substrate 1 is not a convex projection but a concave opening. The point is that

That is, an opening 91 is provided on the surface of the p-type silicon substrate 1, and the bottom surface of this opening is provided with the p-type silicon substrate 1.
A p-type diffusion layer (third conductive layer) 92 having a higher impurity concentration than the type silicon substrate 1 is provided. This diffusion layer 9
2 corresponds to a part of the channel, and by adjusting its impurity concentration, the threshold voltage of the field effect transistor is set.

Further, on the side wall of the opening 91, an n-type low concentration impurity diffusion layer (LDDn-
layers) 93a and 93b are formed, and n-type sources 94a and drains 94b are formed as second conductive layers on the surface of the substrate 1 around them. Further, an insulating film (gate insulating film) 95 is formed on the surface of the substrate 1 including the surface of the opening 91, and a gate electrode 96 is formed so as to fill the opening 91 through the insulating film 95.

This field effect transistor has an LDDn- layer 9 in which a gate electrode 96 is formed on the side wall of the opening 91.
Since it is widely covered by 3a and 93b, it has almost the same effect as the field effect transistor of the first embodiment described above. Moreover, unlike the first to sixth embodiments, the source 9
4a and drain 94b can be secured,
It is possible to obtain the effect that the problem of punch-through can also be prevented.

Next, a method of manufacturing the above-described embodiment of the field effect transistor will be explained. 43 to 54 are cross-sectional views of the process.

First, as shown in FIG. 43, an oxide film such as a silicon oxide film 101 and a nitride film such as a silicon nitride film 102 are formed on the surface of a p-type silicon substrate on which a field insulating film (not shown) for element isolation is formed. , and resist pattern 103 are sequentially formed.

Next, the silicon nitride film 102 and the silicon oxide film 101 are etched by anisotropic etching according to the pattern 103, and the surface of the substrate 1 is etched with the resist pattern 103 and the patterned silicon nitride film 102 and the silicon nitride film 102 thereunder. Using the silicon oxide film 101 as a mask, etching is performed anisotropically by reactive ion etching or the like to form an opening 91 (FIG. 44).

Next, as shown in FIG. 45, after removing the resist pattern 103, the exposed surface of the substrate 1 in the opening 91 (in this case, the surface of the opening 91) is oxidized to form a silicon oxide film 101a. Form.

Furthermore, as shown in FIG. 46, the opening 91
A resist layer 104 is formed on the silicon oxide film so as to bury it.

Next, the entire surface of this resist layer 104 is exposed to light so that the resist layer 104 remains only at the bottom of the opening 91 (FIG. 47).

Next, the exposed oxide film 101a within the opening 91 is removed by ammonium fluoride solution etching or the like. At this time, the bottom oxide film is protected by the resist 104 and is not etched.

Further, as shown in FIG. 48, the remaining resist layer 104 is removed, and an insulating film 105 such as an AsSG film is formed over the entire surface so as to fill the opening 91.
After forming the LDDn-
Layers 93a and 93b are formed. Next, as shown in FIG. 49, AsSG film 105 and silicon oxide film 103
is removed by etching. Here, the silicon nitride film 102 serves to protect a field insulating film (not shown) for element isolation from being etched.

Furthermore, the surface of the opening 91 is covered with the oxide film 1 again.
After coating with 0.06, p-type impurity 107 is ion-implanted perpendicularly to the substrate 1 to form a p-type diffusion layer 92 on the bottom surface (channel region) of the opening 91 (FIG. 50).

Next, as shown in FIG. 51, the silicon nitride film 102, silicon oxide film 101, and oxide film 106 are selectively etched away.

Thereafter, as shown in FIG. 52, an insulating film (gate insulating film) 95 and a conductive layer, such as a polycrystalline silicon layer 96, which will become the gate electrode are formed in this order over the entire surface.

Next, as shown in FIG. 53, the polycrystalline silicon layer 96 is patterned to form a gate electrode 96, and a new resist mask R for forming a source and drain is formed. After this, this resist mask R and gate electrode 9
6 as a mask, n-type impurity 108 is ion-implanted perpendicularly to the substrate 1 to form an n-type source 94a and drain 94b as shown in FIG.

Finally, a field effect transistor as shown in FIG. 42 is completed through steps similar to those of the first embodiment.

The field effect transistor thus formed has the same effects as the first embodiment, as described above.

Example 8 Next, another method of manufacturing the field effect transistor of Example 7 described above will be described.

FIGS. 55 and 56 are process cross-sectional views showing an embodiment of this manufacturing method.

First, in the process of Example 7, FIGS.
After forming a concave portion by performing a process similar to that shown in FIG.
(Figure 55).

Next, as shown in FIG. 56, anisotropic etching is performed to leave the silicon oxide film 111 only at the bottom of the opening 91. Furthermore, by performing the same steps as the steps after FIG. 48, it is possible to complete the field effect transistor of Example 7 of the present invention as shown in FIG.

According to this method, the process is simpler than the method of Example 7, and the thickness of the silicon oxide film left on the bottom can be made thicker.
This is a better method because As does not diffuse into the channel region 92 during the subsequent solid phase diffusion from the AsSG film 105.

Embodiment 9 Next, still another manufacturing method for manufacturing the field effect transistor of the seventh embodiment of the present invention will be described.

FIGS. 57 to 61 are process cross-sectional views showing the manufacturing method.

First, as shown in FIG. 57, an insulating film 95a and a patterned silicon nitride film 121 are sequentially formed on a p-type silicon substrate 1 on which a field insulating film (not shown) for element isolation is formed. As shown in FIG. 58, anisotropic etching is performed using the nitride film 121 as a mask until an opening 91 is formed in the substrate 1. Then, as shown in FIG.

Next, as shown in FIG. 59, after forming a silicon oxide film 122 on the surface of the opening 91, an n-type impurity 123 is rotationally implanted obliquely into the substrate 1 to form a silicon oxide film 122 on the surface of the opening 91. LDDn- layers 93a and 93b are formed on the sidewalls.

Furthermore, as shown in FIG. 60, p-type impurity 1
By ion-implanting 24 perpendicularly to the substrate 1, a p-type diffusion layer 92 is formed on the bottom surface of the opening 91.

Further, as shown in FIG. 61, after removing the silicon oxide film 122, the uppermost nitride film is removed, and a gate insulating film 95b is again formed on the surface of the opening 91.

Next, a conductive layer, such as a polycrystalline silicon layer 96, which will become a gate electrode is formed on the entire surface by a process similar to that shown in FIG. The field effect transistor according to the seventh embodiment of the present invention shown in 42 is completed.

The field effect transistor thus formed has the same effects as the first embodiment.

Embodiment 10 FIGS. 62 to 68 are process cross-sectional views for explaining a tenth embodiment of a field effect transistor according to the present invention and its manufacturing method.

First, as shown in FIG. 62, a thermally oxidized silicon oxide film 131 and a CVD silicon oxide film 132 are formed on a p-type silicon substrate 1 on which a field insulating film (not shown) for element isolation is formed. After forming these in sequence, they are patterned.

Next, as shown in FIG. 63, isotropic etching is performed so that the substrate 1 under the ends of the patterned silicon oxide film 131 and the CVD silicon oxide film 132 is etched. A shaped opening 133 is formed.

Furthermore, as shown in FIG.
After forming a silicon oxide film 134 on the surface of the substrate 1, p-type impurity 135 is ion-implanted perpendicularly to the substrate 1. As a result, a p-type diffusion layer 92 is formed at the bottom of the opening 133.

Next, as shown in FIG. 65, after selectively removing the CVD silicon oxide film 132, silicon oxide films 131 and 134, a silicon oxide film 136 is again formed on the entire surface as shown in FIG. Low concentration impurities in the mold 137
The ions are implanted while rotating diagonally to the substrate. As a result,
LDDn- layers (first conductive layers) 138a and 138b are formed on the sidewalls of the opening 133.

Next, as shown in FIG. 67, the oxide film 136 is removed.

Thereafter, the same steps as those shown in FIGS. 52 to 54 are performed to complete the field effect transistor according to the present invention shown in FIG. Here, 95' is a gate insulating film,
96' is a gate electrode.

The field effect transistor formed by this method can also obtain the same effects as the first embodiment.

Example 11 The field effect transistor formed in the recess shown in FIG. 42 is formed by the steps shown in FIGS. 43 to 54, but the mask for forming the LDDn- layer on the side wall of the recess is placed on the bottom surface of the recess of the substrate. When forming the LDDn- layer, anisotropic etching of the resist or anisotropic etching of the silicon oxide film is used, but since the thickness of this film cannot be controlled sufficiently, the controllability of the LDDn- layer is poor. , there was a problem that the characteristics became unstable.

[0121] Here, a method for forming this LDDn- layer with good controllability will be explained.

FIGS. 69 to 74 are cross-sectional views of the process.

First, as in the method of Example 7, as shown in FIG.
An oxide film, such as a silicon oxide film 101, and a nitride film, such as a silicon nitride film 10, are formed on the surface of the p-type silicon substrate.
2 and a resist pattern 103 are sequentially formed.

Next, the silicon nitride film 102 and the silicon oxide film 101 are etched by anisotropic etching according to the pattern 103, and the surface of the substrate 1 is etched with the resist pattern 103 and the patterned silicon nitride film 102 and the silicon oxide film 102 thereunder. Using the silicon oxide film 101 as a mask, etching is performed anisotropically by reactive ion etching or the like to form an opening 91 (FIG. 70).

Next, as shown in FIG. 71, after removing the resist pattern 103, a silicon nitride film 150 is formed over the entire surface.

Then, as shown in FIG. 72, this silicon nitride film 150 is etched by anisotropic etching and left on the side wall of the recess.

Thereafter, as shown in FIG. 73, heat treatment is performed in an oxygen atmosphere to form a silicon oxide film 151 only on the bottom surface of the opening 91.

Then, as shown in FIG. 74, the silicon nitride film 150 on the sidewall of the recess is removed using isotropic etching, and the substrate surface is oxidized to fill the opening 91 (as shown in FIG. 48). Similarly), after forming an insulating film, for example, a glass film 152 such as an AsSG film on the entire surface so as to fill the opening 91, LDDn-
Layers 93a and 93b are formed.

After this, as shown in FIGS. 49 to 54, p-type impurity ions are implanted perpendicularly to the substrate 1 to diffuse p-type into the bottom surface (channel region) of the opening 91. A layer 92 is formed, a gate insulating film and a gate electrode are formed, and an n-type impurity is added to the substrate 1 using the gate electrode as a mask.
Ions are implanted perpendicularly to the n-type source 94a and drain 94b.

Finally, a field effect transistor as shown in FIG. 42 is completed through steps similar to those of the first embodiment.

[0131] In addition to the effects of Example 1, the field effect transistor formed in this manner has
- Since the layer formation is performed with good controllability, the threshold voltage and driving ability are stable.

Example 12 Here again, a method for forming this LDDn- layer with good controllability will be described.

[0133] This method is a modification of Example 11. In Example 11, a silicon nitride film was formed on the side wall of the recess,
Selective oxidation is performed using this as a mask, but in this example, the entire opening 91 is covered with a silicon oxide film 154 before forming the silicon nitride film on the side wall. It is.

FIGS. 75 to 77 are cross-sectional views of the process.

First, as in the method of Example 11, an opening 91 is formed on the surface of a p-type silicon substrate on which a field insulating film (not shown) for element isolation is formed, and the resist pattern 103 is removed. After that, as shown in FIG. 75, a silicon oxide film 154 is formed on the inner wall of the opening 91 by thermal oxidation, and a silicon nitride film 153 is further formed on the entire surface.

Then, as shown in FIG. 76, this silicon nitride film 153 is selectively etched by anisotropic etching and left on the side walls of the recess.

Thereafter, as shown in FIG. 77, heat treatment is performed in an oxygen atmosphere to selectively form a silicon oxide film 155 only on the bottom surface of the opening 91.

Then, the silicon nitride film 153 on the side wall of the recess is removed using isotropic etching, and the opening 91 is further removed.
The silicon oxide film on the sidewalls of the substrate is removed by wet etching using an ammonium fluoride solution.

At this time, the silicon oxide film 15 on the bottom is sufficiently thicker than the silicon oxide film 154 on the side walls, so it is not removed by this etching.

After oxidizing the substrate surface, Example 11
In the same manner as (FIG. 74), after forming an insulating film, for example, a glass film 152 such as an AsSG film on the entire surface so as to fill the opening 91, LDDn- layers 93a and 93b are formed on the side walls of the opening by thermal diffusion. . Further, through similar steps, a field effect transistor as shown in FIG. 42 is completed.

According to this method, the entire opening 91 is covered with the silicon oxide film 154 before forming the silicon nitride film on the sidewall, and therefore, in addition to the effect of Example 11, the substrate It is possible to alleviate the stress that would otherwise occur if a silicon nitride film is directly formed, thereby further increasing reliability.

Example 13 The field effect transistor having the structure as described above occupies a small area and has good characteristics, so it is also effective as a transistor for configuring a memory cell of a DRAM.

Next, a DRAM formed using this field effect transistor will be explained. This DRAM
As shown in FIG. 78, the field effect transistor formed in Example 12 was used, and a trench-structured capacitor was arranged so that the storage node electrode 201 was connected to the drain region 94b to configure a memory cell. It is something.

This capacitor has a storage node electrode 201 made of a polycrystalline silicon film, a storage node electrode 201 made of a silicon nitride film and a silicon oxide film, and a silicon oxide film as an insulating film 200 in a trench T formed on the surface of the substrate. It is composed of a capacitor insulating film 202 made of a layered film and a plate electrode 203 made of a polycrystalline silicon film.

204 is an interlayer insulating film, 205 is a passing word line, 206 is an interlayer insulating film, and 207 is a bit line made of a polycide film or the like formed so as to be in contact with the source region 94a of the field effect transistor. 208 is a field oxide film.

[0146] According to a DRAM having such a structure, it is possible to significantly miniaturize cells while maintaining reliability.

Note that it is possible to apply not only the field effect transistor of this structure but also any field effect transistor of the present invention, such as the field effect transistors of the first to eleventh embodiments, to a DRAM.

Note that the present invention is not limited to the above embodiments. For example, the shape of the stepped portion can be appropriately selected from protrusions, openings, etc. having various shapes formed by processing the surface of the substrate. For example, the materials of the reverse tapered protrusion, the CVD film, the conductive layer, the n-type and p-type impurities, the substrate, etc. can be changed as appropriate. Furthermore, the oxide film provided on the surface of the substrate can also be replaced with other materials to prevent damage due to ion implantation or rotational ion implantation.

Furthermore, the present invention is not limited to the above-mentioned n-channel MOS type FET, but also applies to p-channel MOS type FET.
It is also applicable to other field effect transistors such as MESFETs.

[0150] In addition, various modifications can be made without departing from the gist of the present invention.

[0151]

According to the present invention, the overlapping area between the gate electrode and the first conductive layer, specifically the LDDn- layer, can be increased without increasing the short channel effect. Therefore, even if the semiconductor element is miniaturized, the threshold voltage can be kept stable. Furthermore, local electric field concentration between the source and drain can be suppressed,
Generation of hot carriers can be prevented and reliability can be improved.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a field effect transistor according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of a field effect transistor according to a first embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of a field effect transistor according to a first embodiment of the present invention.

FIG. 4 is a manufacturing process diagram of a field effect transistor according to a first embodiment of the present invention.

FIG. 5 is a manufacturing process diagram of a field effect transistor according to a first embodiment of the present invention.

FIG. 6 is a manufacturing process diagram of a field effect transistor according to a first embodiment of the present invention.

FIG. 7 is a manufacturing process diagram of a field effect transistor according to a first embodiment of the present invention.

FIG. 8 is a manufacturing process diagram of a field effect transistor according to a first embodiment of the present invention.

FIG. 9 is a manufacturing process diagram of a field effect transistor according to a first embodiment of the present invention.

FIG. 10 is a manufacturing process diagram of a field effect transistor according to a second embodiment of the present invention.

FIG. 11 is a manufacturing process diagram of a field effect transistor according to a second embodiment of the present invention.

FIG. 12 is a manufacturing process diagram of a field effect transistor according to a second embodiment of the present invention.

FIG. 13 is a manufacturing process diagram of a field effect transistor according to a second embodiment of the present invention.

FIG. 14 is a manufacturing process diagram of a field effect transistor according to a third embodiment of the present invention.

FIG. 15 is a manufacturing process diagram of a field effect transistor according to a third embodiment of the present invention.

FIG. 16 is a manufacturing process diagram of a field effect transistor according to a third embodiment of the present invention.

FIG. 17 is a manufacturing process diagram of a field effect transistor according to a third embodiment of the present invention.

FIG. 18 is a cross-sectional view showing a field effect transistor according to a third embodiment of the present invention.

FIG. 19 is a manufacturing process diagram of a field effect transistor according to a third embodiment of the present invention.

FIG. 20 is a manufacturing process diagram of a field effect transistor according to a third embodiment of the present invention.

FIG. 21 is a manufacturing process diagram of a field effect transistor according to a third embodiment of the present invention.

FIG. 22 is a manufacturing process diagram of a field effect transistor according to a fourth embodiment of the present invention.

FIG. 23 is a manufacturing process diagram of a field effect transistor according to a fourth embodiment of the present invention.

FIG. 24 is a manufacturing process diagram of a field effect transistor according to a fourth embodiment of the present invention.

FIG. 25 is a manufacturing process diagram of a field effect transistor according to a fourth embodiment of the present invention.

FIG. 26 is a manufacturing process diagram of a field effect transistor according to a fourth embodiment of the present invention.

FIG. 27 is a manufacturing process diagram of a field effect transistor according to a fourth embodiment of the present invention.

FIG. 28 is a manufacturing process diagram of a field effect transistor according to a fourth embodiment of the present invention.

FIG. 29 is a manufacturing process diagram of a field effect transistor according to a fourth embodiment of the present invention.

FIG. 30 is a manufacturing process diagram of a field effect transistor according to a fourth embodiment of the present invention.

FIG. 31 is a manufacturing process diagram of a field effect transistor according to a fifth embodiment of the present invention.

FIG. 32 is a manufacturing process diagram of a field effect transistor according to a fifth embodiment of the present invention.

FIG. 33 is a manufacturing process diagram of a field effect transistor according to a fifth embodiment of the present invention.

FIG. 34 is a manufacturing process diagram of a field effect transistor according to a fifth embodiment of the present invention.

FIG. 35 is a manufacturing process diagram of a field effect transistor according to a fifth embodiment of the present invention.

FIG. 36 is a manufacturing process diagram of a field effect transistor according to a sixth embodiment of the present invention.

FIG. 37 is a manufacturing process diagram of a field effect transistor according to a sixth embodiment of the present invention.

FIG. 38 is a manufacturing process diagram of a field effect transistor according to a sixth embodiment of the present invention.

FIG. 39 is a manufacturing process diagram of a field effect transistor according to a sixth embodiment of the present invention.

FIG. 40 is a manufacturing process diagram of a field effect transistor according to a sixth embodiment of the present invention.

FIG. 41 is a manufacturing process diagram of a field effect transistor according to a sixth embodiment of the present invention.

FIG. 42 is a diagram showing a field effect transistor according to a seventh embodiment of the present invention.

FIG. 43 is a manufacturing process diagram of a field effect transistor according to a seventh embodiment of the present invention.

FIG. 44 is a manufacturing process diagram of a field effect transistor according to a seventh embodiment of the present invention.

FIG. 45 is a manufacturing process diagram of a field effect transistor according to a seventh embodiment of the present invention.

FIG. 46 is a manufacturing process diagram of a field effect transistor according to a seventh embodiment of the present invention.

FIG. 47 is a manufacturing process diagram of a field effect transistor according to a seventh embodiment of the present invention.

FIG. 48 is a manufacturing process diagram of a field effect transistor according to a seventh embodiment of the present invention.

FIG. 49 is a manufacturing process diagram of a field effect transistor according to a seventh embodiment of the present invention.

FIG. 50 is a manufacturing process diagram of a field effect transistor according to a seventh embodiment of the present invention.

FIG. 51 is a manufacturing process diagram of a field effect transistor according to a seventh embodiment of the present invention.

FIG. 52 is a manufacturing process diagram of a field effect transistor according to a seventh embodiment of the present invention.

FIG. 53 is a manufacturing process diagram of a field effect transistor according to a seventh embodiment of the present invention.

FIG. 54 is a manufacturing process diagram of a field effect transistor according to a seventh embodiment of the present invention.

FIG. 55 is a manufacturing process diagram of a field effect transistor according to an eighth embodiment of the present invention.

FIG. 56 is a manufacturing process diagram of a field effect transistor according to an eighth embodiment of the present invention.

FIG. 57 is a manufacturing process diagram of a field effect transistor according to a ninth embodiment of the present invention.

FIG. 58 is a manufacturing process diagram of a field effect transistor according to a ninth embodiment of the present invention.

FIG. 59 is a manufacturing process diagram of a field effect transistor according to a ninth embodiment of the present invention.

FIG. 60 is a manufacturing process diagram of a field effect transistor according to a ninth embodiment of the present invention.

FIG. 61 is a manufacturing process diagram of a field effect transistor according to a ninth embodiment of the present invention.

FIG. 62 is a manufacturing process diagram of a field effect transistor according to a tenth embodiment of the present invention.

FIG. 63 is a manufacturing process diagram of a field effect transistor according to a tenth embodiment of the present invention.

FIG. 64 is a manufacturing process diagram of a field effect transistor according to a tenth embodiment of the present invention.

FIG. 65 is a manufacturing process diagram of a field effect transistor according to a tenth embodiment of the present invention.

FIG. 66 is a manufacturing process diagram of a field effect transistor according to a tenth embodiment of the present invention.

FIG. 67 is a manufacturing process diagram of a field effect transistor according to a tenth embodiment of the present invention.

FIG. 68 is a manufacturing process diagram of a field effect transistor according to a tenth embodiment of the present invention.

FIG. 69 is a manufacturing process diagram of a field effect transistor according to an eleventh embodiment of the present invention.

FIG. 70 is a manufacturing process diagram of a field effect transistor according to an eleventh embodiment of the present invention.

FIG. 71 is a manufacturing process diagram of a field effect transistor according to an eleventh embodiment of the present invention.

FIG. 72 is a manufacturing process diagram of a field effect transistor according to an eleventh embodiment of the present invention.

FIG. 73 is a manufacturing process diagram of a field effect transistor according to an eleventh embodiment of the present invention.

FIG. 74 is a manufacturing process diagram of a field effect transistor according to an eleventh embodiment of the present invention.

FIG. 75 is a manufacturing process diagram of a field effect transistor according to a twelfth embodiment of the present invention.

FIG. 76 is a manufacturing process diagram of a field effect transistor according to a twelfth embodiment of the present invention.

FIG. 77 is a manufacturing process diagram of a field effect transistor according to a twelfth embodiment of the present invention.

FIG. 78 is a cross-sectional view showing the configuration of a DRAM according to an embodiment of the present invention.

FIG. 79: Conventional n-channel MOS type F with LDD structure
FIG. 3 is a cross-sectional view showing the configuration of ET.

[Explanation of symbols]

1,141 P-type semiconductor substrate 1a, 1a' Projection part 1b, 141a Channel part 2a, 2b, 44a, 44b, 86a, 86b, 93a
, 93b, 138a, 138b, 142a, 142b
LDDn-layer 3a, 33a, 49a, 74a, 83a, 94a, 14
3a Source 3b, 33b, 49b, 74b, 83b
, 94b, 143b Drain 4, 4a, 4b, 4c, 4', 95, 95', 144
Gate insulating film 5, 5a, 5b, 5c, 5', 96, 96', 145
Gate electrode 7, 147 Interlayer insulating film 8a, 8b, 8c, 148 Electrode 21, 45, 63, 132 CVD film 22, 42, 4
6, 103, 121 Resist pattern 23a, 23
b, 41, 47a, 47b, 61, 64a, 64b, 8
1a, 81b, 84a, 84b, 101, 106, 12
2,131,134,136 Oxide film 24,25,3
2, 43, 48, 65, 66, 73, 82, 85, 10
8,123,137 n-type impurity 107,124,
135 p-type impurity 31, 67, 71, 95, 10
5 Insulating films 62, 68, 72 Conductive layer (polycrystalline silicon layer) 91 Opening 92 P-type conductive layer 101, 111 Silicon oxide film 102 Silicon nitride film 104 Resist layer 133 Tapered opening T Trench 200 Insulating film 201 Storage node electrode 202 Capacitor insulating film 203 Plate electrode 204 Interlayer insulating film 205 Passing word line 206 Interlayer insulating film 207 Bit line 208 Field insulating film

Claims (11)

[Claims] 1. A semiconductor substrate having a step portion formed on its surface, a pair of first conductive layers of a conductivity type opposite to that of the semiconductor substrate formed on the sidewalls of the step portion, and excluding the step portion. A pair of conductive layers having the same conductivity type as the first conductive layer and higher conductivity than the first conductive layer, which are formed on the surface portion of the semiconductor substrate so as to be connected to the pair of first conductive layers, respectively. a second conductive layer, an insulating film formed on the surface of the stepped portion, and a control formed to face the first conductive layer via the insulating film and to cover the stepped portion. 1. A semiconductor device comprising a field effect transistor having an electrode. 2. The semiconductor device according to claim 1, wherein the stepped portion has a convex shape. 3. The semiconductor device according to claim 2, wherein the control electrode is divided into three regions, and each control electrode is held at the same potential. 4. The semiconductor device according to claim 1, wherein the stepped portion has a concave shape. 5. A third conductive layer having the same conductivity type as the semiconductor substrate and higher conductivity than the semiconductor substrate is formed on a surface portion of the semiconductor substrate corresponding to the bottom surface of the stepped portion. 5. The semiconductor device according to claim 4. 6. A semiconductor substrate having a step portion formed on its surface, a pair of first conductive layers of a conductivity type opposite to that of the semiconductor substrate formed on sidewalls of the step portion, and excluding the step portion. A pair of conductive layers having the same conductivity type as the first conductive layer and higher conductivity than the first conductive layer, which are formed on the surface portion of the semiconductor substrate so as to be connected to the pair of first conductive layers, respectively. a second conductive layer, an insulating film formed on the surface of the stepped portion, and a control formed to face the first conductive layer via the insulating film and to cover the stepped portion. a field effect transistor comprising a second electrode of the pair;
a capacitor connected to one of the conductive layers of the semiconductor device. 7. A step forming step of forming a step on a semiconductor substrate of one conductivity type; and a step of forming a pair of first conductive layers of opposite conductivity to the substrate facing the sidewall of the step. a pair of second conductive layers connected to each of the first conductive layers and having higher conductivity than the first conductive layer on the substrate surface on both sides of the stepped portion; a second conductive layer forming step, an insulating film forming step of forming an insulating film on the stepped portion and the substrate surface on which the second conductive layer is formed, and an insulating film formed on the stepped portion; A method for manufacturing a semiconductor device, including a control electrode forming step of forming a control electrode covering the stepped portion. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the step forming step is a step of forming a convex step. 9. The method of manufacturing a semiconductor device according to claim 7, wherein the step forming step is a step of forming a concave step. 10. The step of forming the first conductive layer is a step of introducing impurities into the sidewall of the stepped portion by rotational ion implantation or thermal diffusion.
A method of manufacturing the semiconductor device described above. 11. The first conductive layer forming step includes, after the step forming the recessed step, a step of selectively forming an insulating mask on the side wall of the recessed step, and forming a conductive layer through the insulating mask. A selective oxidation process that forms an oxide film at the bottom of the step,
10. The method of manufacturing a semiconductor device according to claim 9, further comprising the step of forming a diffusion layer using the oxide film as a mask after removing the insulating mask.