JPH042137U - - Google Patents
Info
- Publication number
- JPH042137U JPH042137U JP4137890U JP4137890U JPH042137U JP H042137 U JPH042137 U JP H042137U JP 4137890 U JP4137890 U JP 4137890U JP 4137890 U JP4137890 U JP 4137890U JP H042137 U JPH042137 U JP H042137U
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- level
- signal
- high frequency
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 230000010355 oscillation Effects 0.000 claims description 2
- 230000003321 amplification Effects 0.000 claims 3
- 238000003199 nucleic acid amplification method Methods 0.000 claims 3
- 238000011144 upstream manufacturing Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
- Noise Elimination (AREA)
Description
第１図は本考案の一実施例を示す図、第２図は
その要部動作を示すフローチヤートである。
２……アツテネータ（レベル減衰手段）、４…
…局部発振回路、５……ＶＣＯ、６……プログラ
マブル分周器、７……基準発振器、８……位相比
較器、９……ＬＰＦ、１４……レベル検出回路、
１５……制御回路。
FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a flowchart showing the operation of its main parts. 2...attenuator (level attenuation means), 4...
... Local oscillation circuit, 5 ... VCO, 6 ... Programmable frequency divider, 7 ... Reference oscillator, 8 ... Phase comparator, 9 ... LPF, 14 ... Level detection circuit,
15...Control circuit.
Claims (1)
にて構成されたシンセサイザ受信機であつて、制
御信号に応じて受信高周波信号のレベルを減衰す
るレベル減衰手段と、所定レベル以上の受信信号
が検出された時、検出信号を出力するレベル検出
手段と、選局指令に応じて選局された同調周波数
における高周波増幅帯域内を前記ＰＬＬ回路の分
周比を可変することにより探索する探索手段と、
この探索手段による探索時に検出された所定レベ
ル以上の放送周波数と前記選局された同調周波数
とが混変調妨害を生じる周波数関係にあるか否か
を判定し、当該周波数関係が混変調妨害を生じる
周波数関係にあるとき、前記レベル減衰手段に前
記制御信号を出力する制御手段とを具備したこと
を特徴とするシンセサイザ受信機。 (2) 前記レベル減衰手段が、アンテナからの高
周波信号を増幅する高周波増幅回路の前段に配置
されたアツテネータであることを特徴とする請求
項１記載のシンセサイザ受信機。 (3) 前記レベル減衰手段が、アンテナからの高
周波信号を増幅する高周波増幅回路の利得を低減
する回路であることを特徴とする請求項１記載の
シンセサイザ受信機。[Claims for Utility Model Registration] (1) A synthesizer receiver whose local oscillation circuit is constituted by a phase-locked loop PLL circuit, comprising level attenuation means for attenuating the level of a received high-frequency signal in accordance with a control signal; level detection means for outputting a detection signal when a received signal of a predetermined level or higher is detected; and a frequency division ratio of the PLL circuit is varied within a high frequency amplification band at a tuning frequency selected in accordance with a tuning command. a search means for searching by
It is determined whether or not the broadcasting frequency of a predetermined level or higher detected during the search by the search means and the selected tuning frequency have a frequency relationship that causes cross-modulation interference, and the frequency relationship causes cross-modulation interference. A synthesizer receiver comprising: control means for outputting the control signal to the level attenuation means when there is a frequency relationship. (2) The synthesizer receiver according to claim 1, wherein the level attenuation means is an attenuator placed upstream of a high frequency amplification circuit that amplifies the high frequency signal from the antenna. (3) The synthesizer receiver according to claim 1, wherein the level attenuation means is a circuit that reduces the gain of a high frequency amplification circuit that amplifies the high frequency signal from the antenna.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4137890U JPH042137U (en) | 1990-04-18 | 1990-04-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4137890U JPH042137U (en) | 1990-04-18 | 1990-04-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH042137U true JPH042137U (en) | 1992-01-09 |
Family
ID=31551995
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4137890U Pending JPH042137U (en) | 1990-04-18 | 1990-04-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH042137U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5778231A (en) * | 1980-11-04 | 1982-05-15 | Hitachi Ltd | Automatic gain control device |
-
1990
- 1990-04-18 JP JP4137890U patent/JPH042137U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5778231A (en) * | 1980-11-04 | 1982-05-15 | Hitachi Ltd | Automatic gain control device |
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