JPH04213968A - Parallel processing compatible image encoding device - Google Patents

Abstract

PURPOSE:To execute image encoding processings in parallel with one unit and to enable a user to assign the priority of the arbitrary encoding processing by time dividedly executing the respectively independent plural encoding processings with each of the processings. CONSTITUTION:A time division setting section 11 determines the timing for switching the encoding processings of a time divided processing control section 10 and the allotment to the respective encoding processings of serial/parallel conversion registers 7, 8 in accordance with the user's instruction inputted via a host system bus. The time divided processing control section 10 executes the selection of the output destination of the encoded picture information from the shift register 6 and the selection of a multiplexer 9 by each of the respective encoding processings in correspondence to the processings to be encoded inputted by an input section 1.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to an encoding device for encoding image signals in facsimiles, electronic files, etc. using a variable length encoding method, and in particular to an encoding device for efficiently performing multiple types of encoding processing. The present invention relates to an encoding device suitable for.

0002

[Prior Art] Conventionally, image processing devices such as facsimiles and electronic file devices encode image signals using encoding devices for the purpose of efficiently transmitting and recording image information. .

[0003] As a conventional technique for efficiently performing such image signal encoding processing, for example, Japanese Patent Laid-Open No. 62
As described in Publication No. 237868, encoded data obtained by compressing and converting an image signal is stored using a plurality of output buffers and a series of encoding processing units. There is a method that performs encoding processing at high speed by operating in parallel.

However, in facsimile systems, for example, there are cases where it is desired to encode different unrelated image information processes at the same time. In other words, two or more independent single operations such as sending, receiving, storing sent documents in memory, outputting various reports, and copying can be performed simultaneously to the extent possible based on system resource allocation. This is an operation mode called multi-access, which has become popular in recent years with the aim of improving the serviceability of devices.

[0005] For example, when using a facsimile machine that transmits image information stored in a memory, if a user wants to give priority to receiving the original that he or she is transmitting during memory transmission, there is a multi-access form that makes this possible. , it is necessary to store the transmitted original in memory during memory transmission.

[0006] Here, in the memory transmission operation, the transmission document image information stored in the memory in a compressed and encoded state is taken out from the memory, decoded once, and re-encoded using an encoding method that can be received by the destination facsimile machine. , which is the operating mode for subsequent transmission. In addition, the memory storage operation for sending originals is the operation of reading the sending original with a scanner and storing its image information in memory. Normally, in order to increase the number of originals that can be stored, the image information is compressed and encoded. It is accumulated after In this way, in this multi-access mode, two types of encoding processing are performed simultaneously.

[0007] In order to support such multi-access, two encoding devices are required in the conventional encoding device based on a single encoding process. However, one of them is not always used and is very uneconomical.

[0008]

[Problem to be solved by the invention] JP-A-62-2378
The conventional encoding device described in Publication No. 68 that performs encoding processing in parallel processes image information in a series of units, for example, parallel encoding processing of image information for one page. Image information processing, for example, encoding processing of multiple pages, is not performed sequentially for each page. Therefore, when performing parallel encoding processing between pages, which is required in a multi-access mode, the number of encoding devices corresponding to the number of parallel processings is required.

An object of the present invention is to solve the problems of the prior art, to perform a plurality of independent encoding processes in a time-sharing manner for each process, and to execute multiple encoding processes in parallel on a single machine. An object of the present invention is to provide an efficient image encoding device that makes it possible.

0010

[Means for Solving the Problems] In order to achieve the above object, the image encoding device of the present invention has the following features: (1) A code obtained by encoding image information inputted line by line using a variable length encoding method, in parallel. In an image encoding device that performs serial conversion, and then converts the parallel-to-serial converted image information into serial-to-parallel data using a serial-to-parallel conversion register in accordance with the bus width of the system bus,・A parallel conversion register, a multiplexer that selects one of the outputs of the plurality of serial/parallel conversion registers, and multiple types of encoding processing that are sequentially switched in a time-sharing manner on a line-by-line basis. , and each of the multiple types of encoding processing time-divided in line units is assigned to each of the multiple serial/parallel conversion registers, and the selection operation of the multiplexer is determined by the switching timing of the multiple types of encoding processing. The present invention is characterized in that it is provided with a time-sharing processing control section that performs control according to the timing.

[0011]

According to the present invention, a plurality of serial-to-parallel conversion registers are provided, and a plurality of types of encoding processing are performed in a time-division manner on a line-by-line basis via the respective serial-to-parallel conversion registers. Then, in accordance with the switching timing of the encoding process, output selection from the serial/parallel conversion register is switched, and multiple types of encoding processes are processed in parallel. In this way, in order to perform multiple types of encoding processing in a time-sharing manner line by line, when switching between multiple types of encoding processing, the serial/parallel conversion register converts the code between serial and parallel signals corresponding to the bus width of the system bus.
Parallel conversion produces odd words. However, in each of the multiple serial/parallel conversion registers,
This incomplete word can be saved, and when control returns to the own encoding process, a code can be added to the end of the incomplete word. Furthermore, the timing for switching between multiple types of encoding processing and the allocation to each of the serial/parallel conversion registers are set based on instructions input from the user. This allows the user to freely switch between encoding processes. In this way, a single encoding device can freely perform a plurality of encoding processes in parallel.

0012

Embodiments Hereinafter, embodiments of the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the configuration of an image encoding apparatus according to the present invention.

The image encoding device of this embodiment is installed in a facsimile machine, and includes an input unit 1 that controls the input of binarized original image information from the host system bus, and a A parallel-to-serial converter (denoted as a parallel-to-serial converter in the figure) 2 that converts the data into serial data, a change point detector 3 that detects the change point of black and white binarization from the serial data, and a change point A run length/mode signal detection unit 4 detects the run length during one-dimensional encoding and the mode signal during two-dimensional encoding based on the detected run length, mode signal, etc. A code generator 5 extracts the code and code length information corresponding to the input signal, a shift register 6 sequentially outputs the code extracted by the code generator 5, and a shift register 6 that sequentially outputs the code extracted by the code generator 5. At the same time as converting and outputting, there are two serial/parallel conversion shift registers (denoted as serial/parallel conversion shift registers in the figure) 7 and 8 that store odd words of encoded image information that occur when switching the processing of the encoding target. , a multiplexer 9 that selects the output from either of the serial/parallel conversion shift registers 7 and 8 and sends it to the host system bus, and a time-sharing process that controls the time-sharing processing operation of the encoding process according to the present invention. Consisting of a control unit 10 and a time division setting unit 11, the control unit 12 controls the operation of the entire device, including the operation according to the present invention, based on instructions from the user input via the host system bus. has been done.

[0015] For example, as a variable-length encoding system for image information in a facsimile, MH (Mo
divided Huffmann) method, MR (M
odified Relative Element
tAddress Design) method,
Encoding methods such as the MMR (Modified MR) method are widely used, and this embodiment is also based on encoding using these methods.

With such a configuration, the image encoding device of this embodiment performs multiple encoding processes required in a multi-access format in parallel in a time-sharing manner, thereby solving the problems of the prior art. be able to. Below, the control unit 12
The processing operations according to the present invention of each processing unit based on the control will be explained.

First, the input unit 1 takes in a plurality of binarized image information of black and white level to be encoded, which is sent alternately from the host system bus line by line, and inputs it to the parallel/serial converter 2. Output. The parallel/serial converter 2 converts the input binary information into serial data and sends it to the change point detector 3. The change point detection unit 3 is
From this serial data, the point of change in the binarization of white and black is detected.

When the change point detecting section 3 detects a change point, the run length mode signal detecting section 4 at that point detects the run length in the one-dimensional encoding mode, and the run length in the two-dimensional encoding mode. A mode signal indicating the relative positional relationship between the nearest change point on the reference line and the target change point on the encoded line is determined, and the resulting signals are sent to the code generation section 5. That is, one-dimensional encoding mode (M
(occurs in H encoding method and MR encoding method)
In the case of 2D encoding mode (generated in MR encoding method and MMR encoding method), a mode signal is sent to the code generating section 5, respectively. Sent.

The code generator 5 generates a code corresponding to the input signal into a ROM (Read
The encoded image information is retrieved from a code table stored in a read-only memory, etc., and the retrieved coded image information is loaded in parallel to the shift register 6 at the next stage. Note that the shift register 6 needs to have a width of 13 bits or more, which is the maximum code length. In addition, the code generation section 5
At the same time as the parallel loading to the shift register 6, the code length information retrieved from the code table is sent to the time division processing control unit 10. Based on this code length information, the time division processing control unit 10 adjusts the timing so as to suppress generation of the next code by the code generation unit 5 until the searched code is discharged from the shift register 6 to the next stage. do.

Next, the coded image information serially output from the shift register 6 must be divided into sections according to the parallel width of the bus and converted from serial to parallel before being sent to the host system bus (parallel bus). Must be. However, in this embodiment, since the encoding process is switched, it is necessary to pay attention to the problems that occur at this time. In other words, when switching the encoding process, it is easy to do it on a line-by-line basis in raster scanning, but regardless of the unit in which the encoding process is switched, either encoding method is a variable-length encoding method. Because of this, the last coded image information word of one encoding process is not necessarily filled with just the code. If such a word is transferred, it will not be possible to decode it at the receiving end. To solve this problem, serial
Parallel conversion shift registers 7 and 8 were provided. In other words, the serial-to-parallel conversion shift registers 7 and 8 continue to process such incomplete words at the end when the encoding process is switched again and control returns to the original encoding process. and save it so that the code is packed. The multiplexer 9 then selects the output from either the serial/parallel conversion shift registers 7 or 8 and sends this coded image information to the host system bus.

The time division setting unit 11 determines the switching timing of the encoding process of the time division processing control unit 10 and the serial/parallel conversion register based on an instruction signal from the facsimile user input via the host system bus. 7
, 8 to each encoding process. Based on the settings, the time division processing control unit 10 selects the output destination of the coded image information from the shift register 6 (either serial/parallel conversion shift register 7 or 8) for each encoding process. , the selection of the multiplexer 9 (selection of either the serial/parallel conversion shift registers 7 or 8) is performed in accordance with the processing of the encoding target input at the input section 1.

In this way, the image encoding apparatus of this embodiment includes the time division processing control section 10, the time division setting section 11, and the two serial/parallel conversion shift registers 7,
8, and by providing a multiplexer 9, two different encoding processes can be performed in parallel. Additionally, by specifying which serial/parallel conversion register to use, the user can easily switch the encoding process at will. In such a case, priority can be given to encoding processing for document reading.

[0023] In this embodiment, the explanation has been made on the premise that encoding methods such as MH encoding method, MR encoding method, MMR encoding method, etc. are used in facsimile. However, if the variable length encoding method is used, the present invention can be applied to image processing systems other than facsimile. In addition, in this embodiment, two types of encoding processing are operated in parallel at the same time, but in order to operate even more encoding processing at the same time, the number of serial-parallel conversion registers is equal to the number of encoding processings. Just prepare it.

[0024]

[Effects of the Invention] According to the present invention, it is possible to perform a plurality of independent encoding processes in a time-sharing manner for each process, and to perform a plurality of encoding processes in parallel with one machine. Image processing systems such as facsimiles can be configured more economically.

[0025]

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the configuration of an image encoding device according to the present invention.

[Explanation of symbols]

1 Input section 2 Parallel/serial conversion section 3 Change point detection section 4 Run length/mode signal detection section 45 Code generation section 6 Shift registers 7, 8 Serial/parallel conversion shift register 9
Multiplexer 10 Time division processing control section 11 Time division setting section 12 Control section

Claims (1)

[Claims] Claim 1: Parallel-to-serial conversion is performed on a code obtained by encoding image information input for each line using a variable-length encoding method, and further, the parallel-to-serial converted image information is processed in a serial-to-parallel conversion register. In an image encoding device that performs serial-to-parallel conversion and sends data according to the bus width of a system bus, one of the plurality of serial-to-parallel conversion registers and the output of the plurality of serial-to-parallel conversion registers. a multiplexer that selects a plurality of types of encoding processing in a time-divided line unit and sequentially switches and inputs the plurality of types of encoding processing, and inputs each of the plurality of types of encoding processing time-divided in line units to The present invention is characterized by further comprising time-sharing processing control means for controlling the selection operation of the multiplexer in accordance with switching timing of the plurality of types of encoding processing. Image encoding device.