JPH04214293A - Semiconductor memory device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] This invention relates to semiconductor memory devices such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory), and particularly relates to bit line equalization and precharging processes. The present invention relates to a semiconductor memory device that achieves reduction in current consumption, reduction in chip area, and improvement in reliability during data read by providing a time difference between the two.

0002

[Prior Art] Conventionally, as a semiconductor memory device, as shown in FIG.
There are some things shown below. This semiconductor memory device includes differential sense amplifiers 61 arranged in one direction, and a pair of bit lines BL and BL# extending from the sense amplifiers 61.
A word line WL extending in a direction crossing the bit lines BL, BL#, a memory cell 62 connected to the bit lines BL, BL# and the word line WL, and a pair of bit lines BL, BL#. A connected equalize/precharge circuit 63 is provided.

A circuit diagram of the equalize/precharge circuit 63 is shown in FIG. This equalize/precharge circuit 63 includes a transistor TR51 connected between a pair of bit lines BL and BL#, a transistor TR52 connected between the bit line BL and a precharge power supply P, and a transistor TR52 connected between a pair of bit lines BL# and BL#. It includes a transistor TR53 connected between the charging power source P and the charging power source P. The precharge power supply P generates a potential intermediate between the power supply potential and zero potential. In addition, the transistor TR51 and the transistor TR52
The gates of the transistor TR53 and the transistor TR53 are connected to a signal line φEQ extending from a timing circuit (not shown).

In the equalize/precharge circuit 63, the timing circuit connects the signal line φ at the end of the data input/output operation cycle of the memory cell 62.
By raising EQ from a low potential to a high potential, the bit line pair BL and BL# are equalized and precharged simultaneously. At this time, the bit line BL is at a high potential,
When bit line BL# is at a low potential, transistors TR51 and TR53 are turned on first, and then transistor TR52 is turned on. In this way, the potentials of the bit line pair BL and BL# are equalized, and
The bit line pair BL, BL# is precharged to the intermediate potential.

[0005]

However, in the conventional semiconductor memory device, as described above, the transistor TR51 connected between the pair of bit lines BL and BL# and the connection between the bit line BL and the precharge power supply P are Since the transistor TR52 connected between them is turned on at the same time, current flows from both the bit line BL at a high potential and the precharge power supply P to the bit line BL# at a low potential. At this time, a relatively large current of about 1/3 of the current flowing through the bit line BL# is the current from the precharge power supply P. The current from the precharge power supply P is the current consumed by the equalize/precharge circuit 63, and is the current consumed by the semiconductor memory device. Therefore, especially in a large capacity semiconductor memory device, there is a problem in that the large current consumption of the precharge power supply increases the current consumption of the semiconductor memory device.

Furthermore, since the current from the precharge power source P is large, the precharge power source P is required to supply a large amount of power, and there is a problem in that the precharge power source P needs to be large.

Furthermore, at the start of the data input/output operation cycle of the memory cell 62, the bit line pair BL, BL# is equalized and precharged by lowering the signal line φEQ from a high potential to a low potential. When finished at the same time, the transistors TR51 and TR5
2. If there is a variation in the threshold voltage of TR53, a potential difference is generated between the pair of bit lines BL and BL# due to the capacitance between the gate and source of the transistor TR52 or TR53, and the pair of bit lines Equalization of the potentials of BL and BL# may become insufficient. That is, among transistors TR51, TR52, TR53,
The threshold voltage of transistor TR53 is
1, when the voltage is smaller than the threshold voltage of TR52, transistors TR51 and TR52 are first turned off when the potential of the signal line φEQ is lowered. At this time,
Since the transistor TR53 is turned on, the potential of the bit line BL# slightly decreases due to capacitive coupling between the gate electrode of the transistor TR53 and the bit line BL#. Therefore, a slight potential difference occurs between the pair of bit lines BL and BL#. Thereafter, even after the transistor TR53 is turned off, this potential difference causes a decrease in the sense sensitivity of the sense amplifier 61, resulting in a problem that the reliability of the data read from the memory cell 62 decreases.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to reduce the current consumption during equalization and precharging of a bit line pair, thereby making it possible to miniaturize the precharge power supply and reduce the current consumption. An object of the present invention is to provide a semiconductor memory device that can prevent the occurrence of a potential difference between bit lines and improve the reliability of read data.

[0009]

Means for Solving the Problems In order to achieve the above object, a semiconductor memory device of a first invention includes differential sense amplifiers arranged in one direction, and a pair of bit lines extending from the sense amplifiers. and a word line extending in a direction intersecting the bit line, and a memory cell connected to the bit line and the word line,
A first switching element connected between a precharge power supply and the pair of bit lines, and a second switching element connected between one bit line of the pair of bit lines and the precharge power supply. and a switching element control circuit that turns on the first switching element and then turns on the second switching element at the end of the data input/output operation cycle of the memory cell.

[0010] Furthermore, the switching element control circuit includes:
At the start of the data input/output operation cycle of the memory cell, after turning off the second switching element,
It is characterized in that the first switching element is turned off.

Further, the semiconductor memory device of the second invention includes:
A differential sense amplifier arranged in one direction, a pair of bit lines extending from the sense amplifier, a word line extending in a direction crossing the bit line, and connected to the bit line and the word line. A semiconductor memory device having a precharge power supply, a first switching element connected between the pair of bit lines, one of the bit lines of the pair of bit lines, and a memory cell having the precharge voltage. a second switching element connected between the power source;
The third switching element connected between the other bit line and the precharge power supply turns on the first switching element at the end of the data input/output operation cycle of the memory cell. The device is characterized in that it includes a switching element control circuit that turns on the second switching element and the third switching element.

[0012] Furthermore, the switching element control circuit includes:
At the start of a data input/output operation cycle of the memory cell, the second switching element and the third switching element are turned off, and then the first switching element is turned off.

[0013]

[Operation] In the semiconductor memory device of the first invention, when equalizing and precharging the pair of bit lines at the end of the data input/output operation cycle of the memory cell,
The switching element control circuit first turns on a first switching element connected between the pair of bit lines, and then connects one of the bit lines of the pair of bit lines to the precharge power supply. Since the connected second switching element is turned on, the potentials of the pair of bit lines are equalized when the first switching element is turned on, and the potentials of the pair of bit lines are both approximately equal to each other. It becomes a precharge potential (a potential intermediate between the power supply potential and zero potential). Therefore, when the second switching element is turned on and the one bit line is electrically connected to the precharge power supply, almost no current flows from the precharge power supply to the one bit line. Therefore, current consumption is reduced and the precharge power supply can be made smaller.

[0014] Furthermore, at the start of the data input/output operation cycle of the memory cell, the switching element control circuit first controls the second switching element when finishing the equalization/precharging of the pair of bit lines. After turning off and disconnecting the one bit line from the precharge power supply, the first switching element is turned off to finish equalizing and precharging the pair of bit lines. Therefore, even if there are variations in the on/off threshold voltages of the first and second switching elements,
The second switching element connected to only one bit line of the pair of bit lines is turned off first, and then the first switching element connected to both of the pair of bit lines is turned off.
switching element is turned off. Therefore, at the end of the equalization/precharge, no potential difference is generated between the pair of bit lines, improving the sense sensitivity of the sense amplifier and improving the reliability of data read from the memory cell. .

Furthermore, compared to the case where three transistors TR51, TR52, and TR53 are used as switching elements for equalizing and precharging the pair of bit lines as in the conventional example, in the first invention, the pair of bit lines Since only two switching elements are used for line equalization and precharging operations, the number of switching elements is reduced and the chip area is reduced.

In the semiconductor memory device of the second aspect of the invention, at the end of the data input/output operation cycle of the memory cell,
When equalizing and precharging the pair of bit lines, the switching element control circuit first turns on the first switching element connected between the pair of bit lines, and then turns on the first switching element connected between the pair of bit lines. a second switching element connected between one bit line of the pair of bit lines and the precharge power supply, and a third switching element connected between the other bit line of the pair of bit lines and the precharge power supply. When the first switching element is turned on, the potentials of the pair of bit lines are equalized, and the potentials of the pair of bit lines are both approximately equal to the precharge potential (power supply voltage). (potential between the potential and zero potential). Therefore, when the second switching element and the third switching element are turned on to connect the one bit line and the other bit line to the precharge power supply, the pair of bit lines are connected from the precharge power supply to the precharge power supply. Almost no current flows through. Therefore, current consumption is reduced and the precharge power supply can be made smaller.

[0017] Furthermore, at the start of the data input/output operation cycle of the memory cell, when finishing the equalization/precharging of the pair of bit lines, the switching element control circuit first connects the second switching element to the second switching element. After the third switching element is turned off to disconnect the pair of bit lines from the precharge power supply, the first switching element is turned off to finish equalizing and precharging the pair of bit lines. Therefore, even if there are variations in the on/off threshold voltages of the first, second, and third switching elements, the second and third switching elements are always connected to only one of the pair of bit lines. First, the first switching element is turned off, and finally, the first switching element connected to both of the pair of bit lines is turned off. Therefore, at the end of the equalization/precharge, no potential difference is generated between the pair of bit lines, improving the sense sensitivity of the sense amplifier and improving the reliability of data read from the memory cell. .

Furthermore, since both of the pair of bit lines are connected to the precharge power supply using the second and third switching elements, there is no connection between the pair of bit lines and the precharge power supply. The circuit becomes completely symmetrical, and variations in the potentials of the pair of bit lines during data reading are reduced.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The semiconductor memory device of the present invention will be explained in detail below with reference to the illustrated embodiments. FIG. 1 is a circuit diagram of an embodiment of the semiconductor memory device of the first invention. This semiconductor memory device includes differential sense amplifiers 1 arranged in one direction.
..., a pair of bit lines B, B# extending from this sense amplifier 1, a word line W extending in a direction crossing the bit lines B, B#, and a pair of bit lines B, B# and the above It includes a memory cell 2 connected to a word line W, and an equalize/precharge circuit 3 connected to the pair of bit lines B and B#.

A circuit diagram of the equalize/precharge circuit 3 is shown in FIG. The equalize/precharge circuit 3 includes an equalize transistor TR1 connected between a pair of bit lines B and B#, and a precharge transistor TR2 connected between the bit line B and a precharge power supply P1. It is equipped with The above precharge power supply P1
generates a precharge potential intermediate between the power supply potential and zero potential. The gate of the transistor TR1 is
It is connected to a signal line φEQ1 extending from a timing circuit (not shown). The gate of the transistor TR2 is connected to a signal line φEQ2 extending from the timing circuit. The above timing circuit and signal lines φEQ1, φEQ2
and constitute a switching element control circuit.

At the end of the data input/output operation cycle of the memory cell 2, the pair of bit lines B, B#
One of them is at power supply potential, and the other is at zero potential. Here, it is assumed that bit line B is at power supply potential and bit line B# is at zero potential. At this time, as shown in FIG. 4, the timing circuit first raises the potential of the signal line φEQ1, turns on the equalizing transistor TR1, and then raises the potential of the signal line φEQ2. Turn on the precharge transistor TR2. In this way, since the equalizing transistor TR1 is turned on before the precharging transistor TR2, at the stage when the equalizing transistor TR1 is turned on, the bit line B which is at the power supply potential is changed from the bit line B which is at zero potential. A current flows through #, and the bit lines B and B# become equal potential (approximately a precharge potential). After that, the precharge transistor TR2 is turned on, and the precharge power supply P1 is turned on.
conducts to bit line B, and completely sets the potentials of bit lines B and B# to the precharge potential. At this time, the current flowing from the precharge power supply P1 to the bit line B compensates for the slight deviation of the potential of the bit lines B and B# from the precharge potential when the bit lines B and B# are equalized. This is a very small amount of current. The current flowing from the precharge power supply P1 directly becomes part of the current consumption of the semiconductor memory device.
By making the current flowing from the precharge power supply P1 extremely small as described above, the current consumption of the semiconductor memory device can be reduced. Moreover, since the current flowing from the precharge power supply P1 can be made very small,
The current supply capacity of the precharge power source P1 can be reduced, and the precharge power source P1 can be downsized.

Furthermore, at the start of the data input/output operation cycle of the memory cell 2, the bit lines B and B#
are both at the precharge potential, and at this time, the timing circuit firstly connects the signal line φ to the precharge potential, as shown in FIG.
After lowering the potential of EQ2 and turning off the precharge transistor TR2, the potential of the signal line φEQ1 is lowered and the equalizing transistor TR1 is turned off. In this way, when the potential of the signal line φEQ2 falls, the equalizing transistor TR1
Since only bit lines B and B# are turned on, no potential difference occurs between bit lines B and B#. After that, even when the potential of the signal line φEQ1 falls, the potential change due to the capacitance between the gate electrode of the transistor TR1 and the bit lines B and B# is the same, so the potential change between the bit lines B and B# is equal. There is no potential difference between the two. Therefore, immediately before the subsequent data read operation, the pair of bit lines B and B# become completely equal in potential, so that the sense sensitivity of the sense amplifier 1 can be improved, and the read data from the memory cell 2 can be improved. reliability can be improved.

Furthermore, since the equalize/precharge circuit 3 of the semiconductor memory device according to the first aspect of the invention has only two transistors TR1 and TR2 as switching elements, it does not function as a switching element as in the conventional example. Compared to using three transistors, equalization
The number of transistors in the precharge circuit can be reduced, and the chip area can be reduced.

Next, an embodiment of the semiconductor memory device according to the second invention will be described with reference to FIG. This embodiment is used as a third switching element between the precharge power supply P1 and the bit line B# in the equalize/precharge circuit shown in FIG. 2 of the embodiment of the semiconductor memory device of the first invention described above. This embodiment differs from the embodiment of the first invention only in that a precharging transistor TR3 is connected. Therefore, the same parts are given the same numbers, and the parts different from the above-described first embodiment will be explained with emphasis.

FIG. 3 shows a circuit diagram of the equalize/precharge circuit of the embodiment of the semiconductor memory device of the second invention. In this embodiment, in addition to an equalizing transistor TR1 connected between bit lines B and B# and a precharging transistor TR2 connected between bit line B and precharge power supply P1, bit line B Since the precharge transistor TR3 connected between # and the precharge power supply P1 is provided, the current consumption can be reduced and the precharge power supply P1 can be made smaller, as in the embodiment of the first invention described above. In addition to improving the reliability of read data, the circuit between the pair of bit lines B and B# and the precharge power supply P1 is completely symmetrical, causing imbalance between the pair of bit lines. Instead, the pair of bit lines B, B
At the end of equalization/precharge of #, it is possible to eliminate any potential difference caused by the equalization/precharge circuit between the pair of bit lines B and B#.

Next, the current consumption of the equalize/precharge circuit shown in FIG. 3 of the semiconductor memory device according to the embodiment of the second invention will be compared with the equalize/precharge circuit shown in FIG. 10 of the conventional semiconductor memory device. I will explain while doing so. FIG. 6 shows simulation results of current values flowing through the equalizing transistor TR1 and the precharging transistors TR2 and TR3 of the equalizing/precharging circuit of the semiconductor memory device according to the embodiment of the second invention at the time of equalizing/precharging. shows. In FIG. 6, the solid line shows the current flowing through the equalizing transistor TR1, and the broken line shows the current flowing through the precharging transistor TR1.
The current value flowing through 2 is shown. Moreover, the dotted line indicates the current value flowing through the precharge transistor TR3. As shown in FIG. 6, precharging transistors TR2 and TR
Almost no current flows through 3. Figure 7 shows the equalization
During precharging, the conventional semiconductor memory device shown in FIG.
2 shows simulation results of current values flowing through transistors TR51, TR52, and TR53 of the equalize/precharge circuit 63 shown in FIG. In FIG. 7, the solid line indicates the current value flowing through the transistor TR51, and the broken line indicates the current value flowing through the transistor TR52. Furthermore, the dotted line indicates the value of the current flowing through the transistor TR53. As shown in FIG. 7, a large amount of current flows not only through transistor TR51 but also through transistor TR52 and transistor TR53.

FIG. 8 shows simulation results of the current value flowing through the precharge power supply during equalization and precharge. In FIG. 8, the solid line indicates the current value flowing through the precharge power supply P1 of the equalize/precharge circuit shown in FIG. 3 in the embodiment of the second invention. Furthermore, the broken line indicates the precharge power supply P of the equalize/precharge circuit shown in FIG. 10 of the conventional semiconductor memory device.
Indicates the value of the current flowing through the As shown in FIG. 8, the current flowing from the precharge power supply in the embodiment of the second invention is 1/10 or less compared to the conventional example. Calculating this using the circuit scale of 64MDRAM, if the conventional equalize/precharge circuit is used,
Current consumption during equalization/precharge is approximately 13mA.
On the other hand, when the equalize/precharge circuit of the embodiment of the second invention is adopted, the equalize/precharge circuit becomes
Current consumption during precharging is approximately 1.0 mA. Therefore, by employing the equalize/precharge circuit of the embodiment of the second invention, the current consumption can be reduced by approximately 12 mA compared to the case where the conventional equalize/precharge circuit is employed. In this case, the current consumption of the entire chip of the 64M DRAM is expected to be about 150 mA. Therefore, the amount of reduction in the current consumption described above occupies a considerably large proportion compared to the current consumption of the entire chip, and is worthy of attention.

The embodiment of the first invention can also achieve the above-described effect of reducing current consumption, similar to the embodiment of the second invention.

[0029]

As is clear from the above description, in the semiconductor memory device of the first invention, when equalizing and precharging the pair of bit lines at the end of the data input/output operation cycle of the memory cell, The switching element control circuit first turns on a first switching element connected between the pair of bit lines, and then connects one bit line of the pair of bit lines to the precharge power supply. Since the second switching element connected between them is turned on, the potentials of the pair of bit lines are equalized when the first switching element is turned on, and the potentials of the pair of bit lines are both equalized. , becomes almost the precharge potential (a potential intermediate between the power supply potential and zero potential). Therefore, when the second switching element is turned on and the one bit line is electrically connected to the precharge power supply, almost no current flows from the precharge power supply to the one bit line. Therefore, current consumption can be reduced and the precharge power supply can be downsized.

Further, at the start of the data input/output operation cycle of the memory cell, the switching element control circuit first controls the second switching element when equalizing and precharging the pair of bit lines. After turning off and disconnecting the one bit line from the precharge power supply, the first switching element is turned off to finish equalizing and precharging the pair of bit lines. Therefore, even if there are variations in the on/off threshold voltages of the first and second switching elements,
The second switching element connected to only one of the pair of bit lines is turned off first, and then the first switching element connected to both of the pair of bit lines is turned off. The switching element turns off. Therefore, at the end of the equalization/precharge, no potential difference is generated between the pair of bit lines, which improves the sense sensitivity of the sense amplifier and improves the reliability of data read from the memory cell. .

Furthermore, in the first aspect of the invention, only two switching elements are used for equalizing and precharging the pair of bit lines. Compared to using three transistors as elements,
The number of switching elements is reduced, making it possible to reduce the chip area.

In the semiconductor memory device of the second invention, at the end of the data input/output operation cycle of the memory cell,
When equalizing and precharging the pair of bit lines, the switching element control circuit first turns on the first switching element connected between the pair of bit lines, and then turns on the first switching element connected between the pair of bit lines. a second switching element connected between one bit line of the pair of bit lines and the precharge power supply, and a third switching element connected between the other bit line of the pair of bit lines and the precharge power supply. When the first switching element is turned on, the potentials of the pair of bit lines are equalized, and the potentials of the pair of bit lines are both approximately equal to the precharge potential (power supply voltage). (potential between the potential and zero potential). Therefore, when the second switching element and the third switching element are turned on and the one bit line and the other bit line are connected to the precharge power supply, almost no current flows through the pair of bit lines. Not flowing. Therefore, current consumption can be reduced and the precharge power supply can be downsized.

[0033] Furthermore, at the start of the data input/output operation cycle of the memory cell, when finishing the equalization/precharging of the pair of bit lines, the switching element control circuit first connects the second switching element to the second switching element. After the third switching element is turned off to disconnect the pair of bit lines from the precharge power supply, the first switching element is turned off to finish equalizing and precharging the pair of bit lines. Therefore, even if there are variations in the on/off threshold voltages of the first, second, and third switching elements, the second and third switching elements are always connected to only one of the pair of bit lines. First, the first switching element is turned off, and finally, the first switching element connected to both of the pair of bit lines is turned off. Therefore, at the end of the equalization/precharge, no potential difference occurs between the pair of bit lines, and the sense sensitivity of the sense amplifier can be improved.
The reliability of data read from the memory cell can be improved.

Furthermore, since both of the pair of bit lines are connected to the precharge power supply using the second and third switching elements, there is no connection between the pair of bit lines and the precharge power supply. The circuit becomes completely symmetrical, and variations in the potentials of the pair of bit lines during data reading can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of a semiconductor memory device of a first invention.

FIG. 2 is a circuit diagram of an equalize/precharge circuit of the embodiment of the semiconductor memory device of the first invention.

FIG. 3 is a circuit diagram of an equalize/precharge circuit of an embodiment of the semiconductor memory device of the second invention.

FIG. 4 is a diagram showing the operation timing at the start of the equalize/precharge operation of the equalize/precharge circuit of the embodiment of the semiconductor memory device of the first invention;

FIG. 5 is a diagram showing the operation timing at the end of the equalize/precharge operation of the equalize/precharge circuit of the embodiment of the semiconductor memory device of the first invention.

FIG. 6 is a diagram showing simulation results of current values flowing through each transistor of the equalize/precharge circuit of the embodiment of the semiconductor memory device of the second invention.

FIG. 7 is a diagram showing simulation results of current values flowing through each transistor of an equalize/precharge circuit of a conventional semiconductor memory device.

FIG. 8: Current values flowing in the precharge power supply of the equalize/precharge circuit of the embodiment of the semiconductor memory device of the second invention and the current flowing in the precharge power supply of the equalize/precharge circuit of the conventional semiconductor memory device. It is a figure which shows the simulation result of a current value.

FIG. 9 is a circuit diagram of a conventional semiconductor memory device.

[Figure 10] Equalization of conventional semiconductor memory device
FIG. 3 is a circuit diagram of a precharge circuit.

[Explanation of symbols]

1,61 sense amplifier 2,62 memory cell 3,
63 Equalize/precharge circuit TR1 Equalize transistors TR2, TR3 Precharge transistors P, P1 Precharge power supply φEQ,
φEQ1, φEQ2 signal line

Claims (4)

[Claims] 1. A differential sense amplifier arranged in one direction, a pair of bit lines extending from the sense amplifier, and a word line extending in a direction intersecting the bit line.
In a semiconductor memory device having a memory cell connected to the bit line and the word line, a precharge power source, a first switching element connected between the pair of bit lines, and a first switching element connected between the pair of bit lines, A second switching element connected between one bit line and the precharge power supply turns on the first switching element at the end of the data input/output operation cycle of the memory cell. 1. A semiconductor memory device comprising a switching element control circuit that turns on two switching elements. 2. The switching element control circuit turns off the second switching element and then turns off the first switching element at the start of a data input/output operation cycle of the memory cell. 2. The semiconductor memory device according to claim 1. 3. A differential sense amplifier arranged in one direction, a pair of bit lines extending from the sense amplifier, and a word line extending in a direction intersecting the bit line.
In a semiconductor memory device having a memory cell connected to the bit line and the word line, a precharge power source, a first switching element connected between the pair of bit lines, and a first switching element connected between the pair of bit lines, a second switching element connected between one bit line and the precharge power supply; a third switching element connected between the other bit line and the precharge power supply; and data in the memory cell. At the end of the input/output operation cycle of
A semiconductor memory device comprising a switching element control circuit that turns on the second switching element and the third switching element after turning on the first switching element. 4. At the start of a data input/output operation cycle of the memory cell, the switching element control circuit turns off the second switching element and the third switching element, and then turns off the first switching element. 4. The semiconductor memory device according to claim 3, wherein the semiconductor memory device is turned off.