JPH04214300A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To improve the yield of chips by selecting all word lines at the time of writing to a memory cell before erasing and selecting the redundancy word lines substd. with the normal and defective word lines at the time of impressing an erasing pulse. CONSTITUTION:The ordinary memory cell and the memory cell connecting to the word line including defective bits are subjected to the writing before erasing by a 1st word line selecting means which is constituted of an automatic erasing circuit M1, an address counter M2, a shift register M3, a switching circuit M6, and a low decoder M7. The ordinary memory cell and the substd. spare memory cell are selected at the time of erasing by a 2nd word line selecting means which is constituted of the circuit M1, the counter M2, an address buffer M8, a predecoder M9, and the low decoder M7. Overerasing of the memory cell including the defective bits and the memory cell which is not used is prevented even if the spare is put into the low side in this way and the overerasing of the defective word lines which do not execute erasing verification is prevented.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] This invention relates to non-volatile semiconductor memory devices, particularly flash EEP devices that can be electrically erased all at once.
It is related to ROM.

0002

[Prior Art] Figure 7 shows "ISSCC Digest of Technical Papers (1990) pp. 60-6.
1 is a block diagram of a conventional flash EEPROM (electrically erasable programmable ROM) shown in FIG. As shown in the figure, Y gates 2,
A source line switch 3, a row decoder 4, and a column decoder 5 are provided. The output of the address buffer 6 is input to the row decoder 4 and column decoder 5. Further, a write circuit 7 and a sense amplifier 8 are connected to the memory array 1 via the Y gate 2. The write circuit 7 and sense amplifier 8 are connected to an input/output buffer 9. The address buffer 6 has an address signal A0.
or Ak is input. On the other hand, input/output data signals I/O0 to I/O7 are connected to the input/output buffer 9. Furthermore, a mode control circuit 10 and an erase control circuit 11 are provided. The mode control circuit 10 has a control signal/
EE, /CE, /OE, /PGM are input.

FIG. 8 is a block diagram of an EEPROM showing the erase control circuit 11 in detail. Broadly speaking, the erase control circuit 11 is composed of a command signal latch 12, a sequence control circuit 13, a verify voltage generation circuit 14, and a voltage switch 15, and the sequence control circuit 13 further includes an address counter 16 and an erase/erase verify control circuit. 17, a decoder control circuit 10, and an erase pulse generator 19.

FIG. 9 shows a cross-sectional view of a memory cell. The memory cell has two gate layers consisting of a control gate 20 and a floating gate 21, and a drain diffusion region 2.
2 and a source diffusion region 23. Although the cross-sectional shape is the same as that of a general EPROM, the oxide film between the floating gate 21 and the substrate is thinner than that of the EPROM, and is approximately 100 ohms thick.

FIG. 10 shows a circuit diagram of a memory array. In the memory array, the memory cells shown in FIG. 9 are arranged in the row direction,
They are arranged in an array in the column direction, and the drains 22 are connected to the bit lines 24.
(BL1, BL2...), the control gate 20 is connected to the word line 25 (WL1, WL2...), and the word line 25 is further connected to the row decoder 4. The bit line 24 is connected to the output of the column decoder 5 (Y1, Y2
) is connected to the I/O line 27 via the Y-gate transistor 26 whose gate is input. Also, I/O line 27
A sense amplifier 8 and a write circuit 7 are connected to. The source 23 of the memory cell is connected to a source line 28,
The source line 28 is connected to the source line switch 3.

Next, the operation will be explained. First, the write operation will be explained. When writing to the memory cell surrounded by the dashed line in FIG. 10, the write circuit 7 is activated and a high voltage (Vpp) is applied to the I/O line 27. Output Y1 is selected by column decoder 5, and the level of output Y1 is boosted to high voltage (Vpp). At this time, outputs Y2 and Y3 are kept at "L" level. moreover,
The row decoder 4 selects WL1 among the word lines 25 and boosts the level of the word line WL1 to a high voltage (Vpp). The source line 28 is grounded by the source line switch 3. As a result, a high voltage is applied to the drain 22 and control gate 20 of the memory cell, and the source 23 is grounded. Hot electrons generated by avalanche collapse near the drain 22 are injected into the floating gate 21, increasing the threshold of the memory transistor (the transistor whose gate is the control gate of the memory cell). It is assumed that information "0" is written in this state.

Erasing is performed by applying a high voltage (Vpp) to the source 23 of the memory cell using the source line switch 3, grounding the control gate 20, and keeping the drain 22 floating. floating gate 2
A strong electric field is induced in the oxide film between the floating gate 21 and the source 23, and electrons are extracted from the floating gate 21 to the source 23 due to a tunneling phenomenon, thereby lowering the threshold value of the memory transistor. That is, column decoder 5, row decoder 4
This is done by setting all outputs to "L". Furthermore, since the source line 28 is common, erasure is performed in the memory array all at once. It is assumed that information "1" is stored in the memory cell by erasure. In the above description, the "H" level indicates approximately the power supply voltage (5V), and the "L" level indicates the ground potential.

Next, reading will be explained. When reading the memory cells surrounded by the dashed line in FIG. 10, the column decoder 5 sets the level of Y1 to “H”.
” and the output of other column decoders 5 (Y2, Y3...)
is kept at "L". The row decoder 4 sets the level of WL1 to "H" and keeps the other word lines at "L" level. The source line 28 is grounded by the source line switch 3. If the memory cell is in a write state and the threshold value of the memory transistor is high, even if an "H" level is applied to the control gate 20, the memory transistor will not conduct, and no current will flow from the bit line 24 to the source line 28. On the other hand, if the memory cell is in an erased state and the threshold value of the memory transistor is low, the memory transistor becomes conductive and current flows from the bit line 24 to the source line 28 through the memory cell. The sense amplifier 8 detects whether or not current flows through the memory cell, and determines whether the information stored in the memory cell is "1" or "0".

By the way, since erasing in EPROM is done by irradiation with ultraviolet rays, once the floating gate becomes electrically neutral, no more electrons are extracted from the floating gate, and the threshold value of the memory transistor drops to about 1V or less. Must not be. On the other hand, flash EEPRO uses tunneling phenomenon to extract electrons.
In M, electrons may be excessively extracted from the floating gate, and the floating gate may become positively charged. (Hereinafter, this phenomenon will be referred to as over-erasing or over-erasing.) In other words, the threshold value of the memory transistor becomes negative, causing trouble in subsequent reading and writing.

Specifically, even if the word line is unselected and the level of the word line is "L" at the time of reading, and the level applied to the control gate of the memory transistor is "L", the bit line is not selected through the memory transistor. Therefore, even if the memory cell on the same bit line that is about to be read is in the write state and the threshold value is high,
Furthermore, even during writing, leakage current flows through over-erased memory cells, resulting in deterioration of write characteristics and furthermore, making writing impossible.

[0011] In order to prevent this over-erasing, an automatic erasing function is provided. It applies a short erase pulse to the source of a memory cell, then performs a read and checks whether the threshold of the memory transistor has become lower than a predetermined value. By repeating this process until becomes lower than a predetermined value, the threshold value of the memory transistor, which is easily erased, is prevented from becoming negative. A read operation for checking this threshold value is called an erase verify operation.

The erase operation will be explained in detail below. In the erase control circuit 11 of FIGS. 7 and 8, the command signal latch 12 latches the input control signal and releases the system bus during the erase operation. The sequence control circuit 13 is for controlling generation of erase pulses and erase verify operations. Furthermore, Figure 1
1 shows a clock timing diagram during erasing. The erase operation starts when the control signal /EE is kept at "L" for a certain period of time when the control signal /CE is "L" (tEW=50ns
). At this time, control signals /OE and /PGM need to be at "H". When the erase mode is entered, the application of the erase pulse and the erase verify operation are automatically repeated, and there is no need to apply a control signal. Whether or not the internal operation, that is, the erase operation is being continued, can be determined by the status polling mode of the input/output pin I/O7. This means that when the control signals /CE, /OE, /EE are set to "L" and /PGM is set to "H", if the erase operation is in progress, the I/O
“L” is output to 7, and when erasing is completed, “H” is output.
is output. Command signal latch 1
2 does not accept control signals other than status polling commands and address signals.

In the erase mode, first, all memory cells are written and their threshold values are raised. If an erase pulse is applied to a memory cell with a low threshold without performing this operation, over-erasing will occur. An address signal generated by address counter 16 is input to address buffer 6. Row decoder 4, column decoder 5, and write circuit 7 are erase/erase verify control circuit 1
7. Next, an erase/erase verify operation is started. Chip erasure is performed by applying high voltage to the sources of all memory cells and grounding all word lines.

After applying the 10 ms erase pulse, erase verify is performed. The sequence control circuit 13 sequentially reads out memory cells selected by the address signal generated by the address counter 16. Erase verify continues until a memory cell with a high threshold is found. Here, if memory cells with high threshold values remain, the verify operation is stopped and the above erase operation is repeated. This erase/erase verify operation is repeated until it is determined that the threshold values of all memory cells have become low. Finally, the status polling signal becomes "H" and all erasing operations are completed.

By the way, in order to ensure an operational margin during reading, the erase verify operation must be performed under a low power supply voltage condition. This is because the power supply voltage or a voltage lower than the power supply voltage by the threshold value of the N-channel transistor is applied to the selected word line, that is, the control gate of the memory transistor. This is because even if it is determined that there is conduction and the threshold value is low, there is a possibility that there is no conduction when the power supply voltage is low. Further, even if conduction occurs, the amount of current that flows is small and may cause a delay in read access. For this purpose, a verify voltage generator 14 is provided. The verify voltage generator 14 is 3
．． 4V is supplied to the row decoder 4 and sense amplifier 8. That is, reading at a power supply voltage of 3.4V is possible. The voltage switch 15 is a circuit that switches between a power supply voltage of 5V, a high voltage of 12V used during writing, and a verify voltage of 3.4V. It supplies 12V, 5V, and 3.4V to the row decoder 4 and column decoder 5, and supplies 12V, 5V, and 3.4V to the sense amplifier. Supply 5V or 3.4V to.

Flash EEP configured as above
Consider the case where redundant memory cells are included in the ROM. Redundant memory cells are a technique that allows a defective memory cell to be replaced with a defective memory cell in a memory array so that it can be made into a good chip even if the memory cell is defective, and is an effective method for increasing yield. Redundant memory cells are usually provided not on a bit-by-bit basis but on a word-line or bit-line basis. Here, we will consider the case where each word line is provided. In order to replace a word line containing a defective bit with a spare word line, it is necessary to store address data for selecting the defective word line in the chip. As this storage means, a method is usually used in which a polyfuse is blown out using a laser. If a circuit is normally constructed using this method, a spare word line will always be selected when an address for selecting a defective word line is input. In the conventional example, all memory cells are written to before erasing to avoid over-erasing, but as mentioned above, when writing to the address of a defective word line, a spare word line is uniquely selected. As a result, no writing is performed to the defective word line. Further, although a plurality of spare word lines are usually prepared, not all spare word lines are necessarily used. When only a portion of the spare word lines are used, pre-erase writing is not performed on the unused spare word lines as described above. Since the threshold voltage of the memory cells connected to the word line to which no pre-erase writing is performed remains low, they will be over-erased when an erase pulse is applied.

[0017]

[Problems to be Solved by the Invention] Conventional nonvolatile semiconductor memory devices are configured as described above, so it is not possible to insert a spare word line on the row side, making it difficult to increase the yield of chips. there were.

The present invention has been made to solve the above-mentioned problems, and even if a spare word line is inserted on the row side, over-erasing will not occur, and the yield of chips can be improved. The purpose is to obtain a nonvolatile semiconductor memory device.

[0019]

[Means for Solving the Problems] A nonvolatile semiconductor memory device according to the present invention includes a first word line selection means for selecting all word lines including a redundant word line when writing to a memory cell before erasing. and second word line selection means for selecting a normal word line and a redundant word line replaced by a defective word line when an erase pulse is applied.

[0020]

According to the present invention, the first word line selection means performs pre-erase programming on normal memory cells, memory cells connected to a word line containing a defective bit, and memory cells connected to all spare word lines. At the same time, when erasing, the second word line selection means is used to erase only normal memory cells and replaced spare memory cells, so spares are placed on the row side. It also ensures that memory cells connected to word lines containing defective bits and memory cells connected to unused spare word lines are not over-erased, and that defective word lines that are not erase-verified are not over-erased. It can be prevented.

[0021]

Embodiment FIG. 1 is a block diagram showing the chip peripheral part of a nonvolatile semiconductor memory device according to an embodiment of the present invention. In the figure, M1 is an automatic erase control circuit, M2 is an address counter, and M3 is a shifter. register, M4 is a spare activation circuit, M5 is a spare decoder, M6 is a switching circuit, M7 is a row decoder, M8 is an address buffer, M9
is a pre-decoder, and the automatic erase control circuit M1, address counter M2, shift register M3, switching circuit M6, and row decoder M7 realize the function of the first word line selection means, and the automatic erase control circuit M1, address counter M2, address buffer M8, predecoder M9, and row decoder M7 realize the function of the second word line selection means.

FIG. 2 is a circuit diagram of the spare activation circuit M4 of FIG. 1, which is of the type that blows out a polyfuse. Figure 3 shows spare decoder M5 that selects the spare row in Figure 1.
FIG. 4 shows a configuration diagram of the address counter M2 and shift register M3 of FIG. 1, where the address counter M2 automatically counts up addresses during automatic erasure, and the shift register M3 sequentially selects spare rows.

More specifically, in FIG.
2 is a P-channel transistor, 33 is a polyfuse, 3
4 is an N-channel transistor, 35 and 37 are 2-input NA
ND gates, 36 and 38 are inverters, 39 is a signal that becomes "H" when activating the address, 40 is a signal that becomes "L" when writing before erasing, and 41 is "H" when using spare rows. This is a signal that becomes . In Figure 3, 4
2, 45, 46 are P-channel transistors, 43, 44
is a polyfuse, 47, 48, 49 are N-channel transistors, 50, 51 are address predecode signals, 5
2 is an inverter, 53 is a spare row when selected.
This is a signal that goes high.

Next, the operation will be explained. Here, the spare word line selection operation will be described in detail, and the explanation of operations that are the same as in the conventional example will be omitted. First, a method for storing the address of a word line containing a defective bit will be described. There is one spare activation circuit M4 for each spare row in FIG. 2, and by blowing out the polyfuse 33 of the spare activation circuit corresponding to the desired spare row with a laser, that spare row can be activated. Next, in the spare decoder shown in FIG. 3, all the other polyfuses 44 are blown out, leaving only the polyfuse 43 connected to the outputs of the P-channel transistors 45 and 47 to which the predecode signal corresponding to the defective address, for example PRD1, is input. . The address can be stored in the manner described above.

Next, write and read operations will be explained. In FIG. 2, in the initial state, the SPS signal 3
9 is “L” and the /PRPRO signal 40 is “H”, the NAND 37 output is “H” and the inverter 38 output is “H”.
”, the P-channel transistor 31 is turned on, and the N-channel transistor 34 is turned off. Therefore, the node N
1 is charged to “H” by the P-channel transistor 31. Since the inputs of the NAND 35 are "H" and "L", its output is "H" and the SPE 41 is "L".

Next, when writing and reading start, SP
The S, /PRPRO signal becomes "H", the output of the NAND gate 35 becomes "L", and the output of the inverter 36 becomes "H". When the polyfuse 33 is blown, the N-channel transistor 34 is disconnected from the node N1, so that even if the output of the inverter 38 becomes "H", the node N1 remains "H". Therefore, the output of NAND35 becomes "L" and the output of SPE41 becomes "H". In Figure 3, S
When PE411 is "H" and all the fuses except polyfuse 43 are blown, the PR of 50
Only when D1 is “H”, node N2 becomes “L” and SP
R1E becomes "H" and a spare row is selected.

On the other hand, when the polyfuse 33 is not blown in FIG. 2, the N-channel transistor 34 is turned on by the "H" output of the inverter 38, and the node N1 is "L".
, the output of NAND35 is “H” and the output of SPE41 is “
When the SPE41 is "L", the node N2 remains "L" in FIG. 3 regardless of whether or not the polyfuse is blown.
While it remains at "H", SPE1E becomes "L" and the spare row is not selected.

Next, the operation at the time of writing before erasing will be explained. The initial state is the same as above, but when entering pre-erase programming, /PRPRO40 becomes "L", the output of NAND37 becomes "H", and the output of inverter 38 becomes "L", so the polyfuse Even if SPE 33 is fused, SPE 41 becomes "L". SPE41 is “
In the case of "L", the operation of the circuit in FIG. 3 is the same as above, and the spare row is not selected. In other words, the defective word line is selected and the spare word line is not selected. The pre-erase write is controlled by the automatic erase control circuit M1. The address counter M2 sequentially counts up the address to be written.When the address counter M2 selects a defective word line, the spare word line is not selected for the above-mentioned reason, and writing is performed to the defective word line. Further, as shown in FIG. 4, shift registers M3 corresponding to the spare word lines are provided at the final stage of the address counter M2, so that writing is also performed on the spare word lines after counting all addresses.

By the above-described operation, pre-erase programming is performed on normal memory cells, memory cells connected to word lines containing defective bits, and memory cells connected to all spare word lines. This operation makes it extremely unlikely that a memory cell will be overerased. However, it cannot be denied that some memory cells may be overerased under the following circumstances.

That is, when applying an erase pulse, all word lines are set to "L" and a high voltage is applied to the source line.
After that, when performing erase verification, use the /PRPRO4
0 becomes "H" and the SPE41 becomes "H", so the defective word line is not selected, but the spare word line is selected. Since the defective word line had a memory cell with an erase defect and was replaced with a spare word line, the erase verify of the defective word line does not pass. For this reason, during erase verification, the defective word line is not selected, but the replaced spare word line is selected. In other words, after the memory cells connected to the defective word line are given an erase pulse, erase verification is not performed. Therefore, over-erasing may occur in memory cells connected to the defective word line.

Therefore, the following configuration requirements are added. That is, FIG. 5 is a circuit diagram showing address buffer M8, and FIG. 6 is a circuit diagram showing row decoder M7. More specifically, in FIG. 5, 54, 57, 58 are 2-input NOR gates, 55
, 56, 59, and 60 are inverters, 61 is an address input from the outside, 62 is a chip enable signal, 63 is a signal that becomes "H" when an erase pulse is applied, and 64 is a positive logic signal output from the address buffer. , 65 are negative logic signals output from the address buffer. 66, 67 in Figure 6,
70, 71 are inverters, 68 is a NAND gate, 69
, 77, 78 are P-channel transistors, 72, 73,
74, 75, 76, 79 are N-channel transistors, 8
3 is a /NED signal that deactivates the normal word line when a spare word line is selected; 84 is a signal obtained by predecoding the output of the address buffer; 85 and 86 are signals that activate the spare word line; 87 is a latch reset signal, 88 is a signal that becomes “H” during a dummy read cycle before applying an erase pulse, and 90 is a signal that becomes “H” when an erase pulse is applied.
89 is a negative logic signal of 90, 91 is a predecode signal, 92 is a negative logic signal of 91, 93 and 94 are spare word lines, 95 is a word line, 80 and 81 are the parts indicated by 82. It is the same circuit.

Next, the operation will be explained. For read, write, write before erase, and erase verify, see A in Figure 5.
Since AH63 is "L", A64 and /A65 output positive logic and negative logic signals, respectively. If all of the predecode signals 84 become "H" in a certain combination and the address is not replaced with a spare, /NED8
3 also becomes "H", so the output of NAND68 becomes "L". Since /ERP89 is "H" and ERP90 is "L", the output of NAND68 is transmitted to the next stage. If the predecode signal 91 is “H”, the transistor 75
is turned on and the gates of 78 and 79 are pulled to "L" by the output of NAND 68, so that the word line 95 outputs "H". In addition, when the above word line is replaced with a spare word line, /NED83 becomes “L” and NAND
Since the output of the word line 68 becomes "H", the word line 95 becomes "L" with the logic opposite to the above. At this time, SPE1, SPE
Either one of 2 is activated, and the spare word line 93,
Either one of 94 becomes "H".

Next, the operation of applying an erase pulse will be explained. A dummy read cycle is performed before the operation of applying the erase pulse. When entering the dummy read cycle operation, RST87 outputs a one-shot pulse, 70,
71 is reset, and node N1 becomes “
Next, DUMRE88 is set to "H" and a read operation is performed for all addresses.During this read period, if the normal row decoder 82 is not replaced with a spare, the output of NAND68 is In order to output “L”, transistor 69 is turned on and node N1
Set to “H”. In the row decoder replaced with a spare, even if all 84 become “H”, /NED
83 becomes "L", the output of NAND 68 never becomes "L" and transistor 69 is not turned on, so node N1 remains "L". Also, for spare row decoders, only those replaced by spares (for example, SPE1
) becomes "H", so only the output of the NAND 68 of 80 becomes "L", and the node N1 becomes "H". When this dummy read cycle ends, the node N1 of the normal row decoder that has not been replaced with a spare and the node N1 of the spare row decoder that has been replaced with a spare are latching "H", and The node N1 of the row decoder and the node N1 of the unused spare row decoder are latched at "L".

Next, in the operation of applying an erase pulse, ERP9
0 becomes "H", /ERP89 becomes "L", and all Z addresses become "H". Therefore, if node N1 is "H", word line 95 is "L", and node N1 is "L". If so, the word line 95 outputs "H". The same applies to the spare word line. When a high voltage for erasing is applied to the source line in this state, the electric field between the floating gate and the source of the memory cell increases only when the word line is at "L", electrons are extracted from the floating gate, and the data is erased. Where the word line is at "H", the electric field is lower than above and the data is not erased.

Through the above operations, the memory cells connected to the normal word line and the spare word line that replaced the defective word line are erased, and the memory cells connected to the defective word line and the unused spare word line are erased. No erasure is performed for .

As described above, according to this embodiment, pre-erase programming is performed on normal memory cells, memory cells connected to word lines containing defective bits, and memory cells connected to all spare word lines. Therefore, defective word lines and unused spare word lines are not over-erased.

In addition, erasing operations are performed only on normal memory cells and replaced spare memory cells, and memory cells connected to word lines containing defective bits,
Also, since the memory cells connected to unused spare word lines are not over-erased, even if the verify operation is not performed on a defective word line during erase verification, it will not be over-erased.

[0038]

As described above, according to the nonvolatile semiconductor memory device of the present invention, pre-erase programming can be performed on normal memory cells, memory cells connected to word lines containing defective bits, and all spare word lines. In addition to erasing memory cells, erase is performed only on normal memory cells and replaced spare memory cells, and erases memory cells connected to word lines containing defective bits and unused spare word lines. Since this is not done for memory cells connected to the row side, even if a spare is inserted on the row side, memory cells connected to a word line containing a defective bit or memory cells connected to an unused spare word line will not be over-erased. As a result, the yield can be improved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a spare activation circuit for activating a spare of a nonvolatile semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a spare decoder that selects a spare row of a nonvolatile semiconductor memory device according to an embodiment of the present invention.

FIG. 3 is a block diagram showing an address counter and a shift register of a nonvolatile semiconductor memory device according to an embodiment of the present invention.

FIG. 4 is a block diagram showing a part of a chip of a nonvolatile semiconductor memory device according to an embodiment of the present invention.

FIG. 5 is a circuit diagram showing an address buffer of a nonvolatile semiconductor memory device according to an embodiment of the present invention.

FIG. 6 is a circuit diagram showing a row decoder of a nonvolatile semiconductor memory device according to an embodiment of the present invention.

FIG. 7 is a block configuration diagram of a conventional nonvolatile semiconductor memory device.

FIG. 8 is a block configuration diagram of a conventional nonvolatile semiconductor memory device showing the erase control circuit in detail.

FIG. 9 is a cross-sectional view of a memory cell of a general nonvolatile semiconductor memory device.

FIG. 10 is a circuit configuration diagram of a memory cell array of a general nonvolatile semiconductor memory device.

FIG. 11 is a diagram for explaining clock timing during erasing of the present invention and a conventional nonvolatile semiconductor memory device.

[Explanation of symbols]

M1 Automatic erase control circuit M2 Address counter M3 Shift register M4 Spare activation circuit M5 Svere decoder M6 switching circuit M7 Row decoder M8 Address buffer M9 Pre-decoder

Claims (1)

[Claims] 1. An erase operation consisting of writing to a memory cell, applying a short erase pulse to the memory cell, and detecting a threshold value of a memory transistor is performed until the threshold value becomes lower than a predetermined value. In a nonvolatile semiconductor memory device having an automatic erasing function and capable of electrically erasing at once, a first word line selection means selects all word lines including a redundant word line when writing to the memory cell; , a second word line that selects a normal word line and a redundant word line replaced with a defective word line when the erase pulse is applied.
1. A nonvolatile semiconductor memory device comprising: word line selection means.