JPH042169A - Horizontal type conductivity modulation semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lateral conductivity modulation type semiconductor device, and more specifically, to a device structure used as a semiconductor switching element such as a power supply device, particularly an anode short structure. The present invention relates to an improvement of a horizontal IGBT having a lateral IGBT.

[Prior art] Conventional horizontal IGB with this type of anode short structure
The general configuration of T is shown in Figure 4.

In the conventional structure shown in FIG. 4, reference numeral 01 is a p-type semiconductor substrate, 102 is an n-type semiconductor layer epitaxially grown on the p-type semiconductor substrate 101, 103 is a p9-type buried layer, and 104 is the p-type semiconductor substrate 101. p4 type buried layer 10
3 is an isolation region for isolation between elements.

Further, 105 is a p-type base region selectively formed on a part of the surface of the n-type semiconductor layer 102, and 106 is the p-type base region selectively formed on a part of the surface of the n-type semiconductor layer 102;
n′″ selectively formed in a part of the mold base region 105
107 is a base region 107 provided on the surface of the p-type base region 105 sandwiched between the n-type semiconductor layer 102 and the n-type semiconductor layer 102 with a gate insulating film 108 interposed therebetween. The gate electrode 109 is the n゛゛source region 1
This is a source electrode that is ohmically connected to the surface of 06.

Further, reference numeral 110 denotes an n-type buffer region 111.11 selectively formed in a part of the surface of the n-type semiconductor layer 102 at a position spaced apart from the p-type base region 105.
1 is located in a part of the n-type buffer region 110, and is a 00-type contact region 11 for ohmic contact.
2 and 2 are p4 type drain regions selectively formed in parallel, and 113 is a drain electrode provided on the surface of the n' contact region 112, including between the p' type drain regions 11 and 111. It is.

Therefore, in the case of the lateral IGBT having the anode short structure of the above configuration, when compared with a normal lateral MOSFET, it is possible to lower the on-voltage by injecting holes into the p'' type doridrain region 111, and to reduce the on-state voltage. By short-circuiting the n-type buffer region 110 and the p9-type drain region 111, electrons are extracted from the n-type buffer region 110, and switching is performed faster than in a lateral IGBT that does not have an anode short structure. It can be done.

[Problem to be solved by the invention]

However, in the lateral IGBT with the above-described anode short structure, the n-type buffer region 110 is
As a stopper for the depletion layer when a high voltage is applied, it has the function of preventing punch-through of the pnp junction structure composed of the p-type base region 105, the n-type semiconductor layer 102, and the p''-type doridrain region 111. Therefore, it needs to have a relatively low resistivity.

On the other hand, conductivity modulation in a lateral IGBT configuration having this kind of anode short structure is caused by a voltage drop in the p'' type drain region 110 due to a voltage drop caused by a current flowing through the n type buffer region 110 directly under the p'' type drain region 111. n
Since the junction of the type buffer region 110 is forward biased, if the resistance of the mouth type buffer region 210 directly under the p4 type drain region 111 is low, conductivity modulation will not occur in the low current region.

Here, as shown in FIG. 5, the V-I in a horizontal IGBT with such an anode short structure is
Characteristic 50 shows that when compared with V-I characteristic 51 of a normal lateral IGBT with a non-anode shorted structure, the on-voltage in the low current region is very high, and the on-voltage is not sufficiently turned on even in the normally used current region. As the voltage stops dropping, a negative resistance characteristic occurs as shown in the figure, and this negative resistance increases losses such as transient on-loss and causes noise generation. There's a problem.

Therefore, even in the low current region, in order to generate conductivity modulation, p'
n-type buffer region 1 directly under the ″-type drain region 111
However, in order to obtain a constant device breakdown voltage, the distance between the p-type base region 105 and the n-type buffer region 110 cannot be easily shortened. Increasing the length occupied by the n-type buffer region 110 simply means an increase in the device area, which is a disadvantage in that it impedes high integration of the device.

On the other hand, as a countermeasure for this, the n-type buffer region 1
For the part near the p3 type drain region 111 in 10,
By diffusing impurities of opposite conductivity type, p
N-type buffer region 11 directly under 0-type drain region 111
Although it is possible to consider means such as increasing the specific resistance of the n-type buffer region 110, such means will unnecessarily increase the variation in device characteristics and, if the n-type buffer region 110 is shallow, the current will Because it flows through the low-resistance region of the anode short-circuit region, no significant effect could be expected.

Therefore, the object of the present invention is to improve this kind of lateral conductivity modulation type semiconductor that can effectively generate conductivity modulation even in a low current region by improving the conventional problems. The purpose is to provide equipment.

[Means for Solving the Problems] In order to solve the above problems, the lateral conductivity modulation type semiconductor devices according to the present invention each have the following device configuration.

a) By forming a first conductivity type drain region and a second conductivity type buffer region surrounding it in a bent shape within a specific range on the surface of the second conductivity type high resistivity semiconductor layer. , substantially increasing the length of the second conductivity type buffer region immediately below the first conductivity type drain region without significantly increasing the required area.

b) By forming the drain electrode connected to both the first conductivity type drain region and the second conductivity type buffer region into a Schottky junction, the potential of the second conductivity type buffer region itself is lowered, and the potential in the low current region is reduced. This also facilitates hole injection from the first conductivity type drain region.

C) By connecting the first conductivity type drain region and the second conductivity type buffer region through a resistor, the potential of the second conductivity type buffer region itself is lowered, and even in a low current region, the first conductivity type drain region is connected to the second conductivity type buffer region. Facilitates hole injection from the mold drain region.

That is, the first invention of the present invention includes a first or second conductivity type semiconductor substrate and a second conductivity type semiconductor substrate formed on the semiconductor substrate.
A conductive type high resistivity semiconductor layer, a first conductive type base region selectively formed on a part of the surface of the second conductive type semiconductor layer, and a first conductive type base region selectively formed on a part of the surface of the base region. a second conductivity type source region; a gate electrode provided on the surface of the first conductivity type base region sandwiched between the source region and the second conductivity type semiconductor layer via an insulating layer; and an ohmic electrode in the source region. a second conductivity type buffer located away from the connected source electrode and the base region on the surface of the second conductivity type semiconductor layer and selectively formed so that at least both side portions form a series of bent shapes; a first region selectively formed in a curved shape within the buffer region;
A lateral conductivity modulation type semiconductor device comprising a conductivity type drain region and a drain electrode ohmically connected to both the drain region and the buffer region.

Further, a second aspect of the present invention provides a first or second conductive type semiconductor substrate, a second conductive type high specific resistance semiconductor layer formed on the semiconductor substrate, and a surface of the second conductive type semiconductor layer. a first conductivity type base region selectively formed in a part of the base region;
A second plate selectively formed on a part of the surface of the base region.
a conductive type source region, a gate electrode provided on a surface of a first conductive type base region sandwiched between the source region and the second conductive type semiconductor layer via an insulating layer, and ohmically connected to the source region. a source electrode, a second conductivity type buffer region selectively formed on the surface of the second conductivity type semiconductor layer at a position away from the base region, and a first conductivity type buffer region selectively formed within the buffer region. A lateral conductivity modulation type semiconductor device comprising a drain region and a drain electrode made of a metal electrode provided to form a Schottky junction with the second conductivity type buffer region.

Furthermore, a third aspect of the present invention provides a first or second conductivity type semiconductor substrate, a second conductivity type high specific resistance semiconductor layer formed on the semiconductor substrate, and a surface of the second conductivity type semiconductor layer. a first conductivity type base region selectively formed in a part of the base region, a second conductivity type source region selectively formed in a part of the surface of the base region, and a first conductivity type base region selectively formed in a part of the surface of the base region; A gate electrode provided on the surface of the first conductivity type base region sandwiched between semiconductor layers via an insulating layer, a source electrode ohmically connected to the source region, and a base on the surface of the second conductivity type semiconductor layer. a second conductivity type buffer region selectively formed at a position away from the region; a first conductivity type drain region selectively formed within the buffer region;
A lateral conductivity modulation type semiconductor device comprising a drain electrode provided with a resistance layer interposed between the semiconductor device and the second conductivity type buffer region.

[For production]

Therefore, in the first aspect of the present invention, the first conductivity type drain region and the second conductivity type buffer region surrounding the first conductivity type drain region are arranged within a specific range on the surface portion of the second conductivity type high resistivity semiconductor layer. Since it was formed into a bent shape,
The length of the second conductivity type buffer region immediately below the first conductivity type drain region is substantially increased without significantly increasing the required area, and thus a large voltage drop can be obtained with a small current. , conductivity modulation may occur even in the low current region, reducing the on-state voltage.

Further, in the second aspect of the present invention, a second conductivity type buffer region and a first conductivity type drain region selectively formed within the buffer region are provided, and the second conductivity type buffer region and a Schottky type are provided. Since the drain electrode made of a metal electrode that forms a junction is provided, the potential of the second conductivity type buffer region increases by an amount equivalent to the Schottky voltage, and even in a low current region, holes from the first conductivity type drain region are Injection starts, conductivity modulation occurs, and it becomes possible to lower the on-state voltage in the normally used current range.

Furthermore, in the third aspect of the present invention, a second conductivity type buffer region and a first conductivity type drain region selectively formed within the buffer region are provided, and the second conductivity type buffer region and the second conductivity type buffer region are provided. Since a drain electrode is provided in between with a resistive layer in between, an electron current flows from the second conductive type buffer region through the resistive layer, and in addition to the voltage drop in the second conductive type buffer region, there is also a voltage drop in the resistive layer. A voltage drop occurs, making conductivity modulation more likely to occur in a low current region, and here too, it becomes possible to lower the on-state voltage in a normally used current region.

[Embodiments] Hereinafter, various embodiments of the lateral conductivity modulation type semiconductor device according to the present invention will be described in detail with reference to FIGS. 1 to 3.

FIG. 1(a) is a cross-sectional view schematically showing the general structure of a horizontal IGBT with an anode short structure to which the first embodiment of the present invention is applied, and FIG. FIG. 3 is a plan pattern diagram showing regions.

That is, in the configuration of the first embodiment shown in FIGS. 1(a) and 1(b), reference numeral 11 denotes a p- (or n-) type semiconductor substrate, and reference numeral 2 denotes a semiconductor substrate epitaxially grown on the p-type semiconductor substrate 11. 13 is a p-type buried layer, and 14 is an isolation region formed on the p4-type buried layer 13 for isolation between elements.

Further, 15 is a p-type base region selectively formed in a part of the surface of the n-type semiconductor layer 12, and 16 is an n0-type source region selectively formed in a part of the p-type base region 15. and 17 is the n′″′″-space area 16 and the n′″′″-space area 16 and the n
a gate electrode provided on the surface of the p-type base region 15 sandwiched between the −-type semiconductor layer 12 and the gate insulating film 18;
Reference numeral 19 denotes a source electrode provided on the surface of the n0 type source region 16.

Further, 20 is located at a distance from the p-type base region 15 on the surface of the n-type semiconductor layer 12,
21.21 indicates an n-type buffer region selectively formed such that at least both sides thereof form a series of curves within a specified area range of the surface portion;
Similarly, within the mold buffer area 20, at least both sides are
There is a p+ type drain region formed having region portions 21a, 21a parallel to each other and following the bent shape, and each of these p''''' drain regions 21.2
Between the parallel region portions 21a and 21a in 1, there is an n゛゛ contact region 22 for ohmic contact.
The drain electrode 23 is connected through the drain electrode 23.

Therefore, in the horizontal IGBT with the anode short structure of the first embodiment configured as described above, with respect to the gate electrode 17,
By applying a voltage equal to or higher than the threshold value, electrons flowing from the n-type source region 16 into the n-type semiconductor layer 12 through the inversion layer formed on the surface of the p-type base region 15 have a low resistance. The liquid flows through the n-type buffer region 20 while keeping the given curved shape,
Here, the p''''' rain region 21 and the n-type buffer region 20 surrounding it immediately below are formed in a series of curved shapes within a specified area range. Without a significant increase, substantially the same effect as in the case where the n-type buffer region 20 and the p4-type drain region 21 are lengthened is achieved, and a large voltage drop is obtained with a small current, resulting in a low current region. Also, conductivity modulation occurs and the on-voltage can be lowered.Then, the conductivity modulation becomes even larger and the n-type semiconductor layer 1
2 is lowered in resistance, current no longer flows along the n-type buffer region 20, making it difficult for positive feedback of the conductivity modulation to occur, resulting in negative characteristics such as the characteristic 50 shown in FIG. Furthermore, during turn-off, a large amount of current flows through the n-type semiconductor layer 12, which has a sufficiently low resistance due to this conductivity modulation, making it difficult for re-injection to occur. This allows high-speed turn-off.

Next, FIG. 2 is a sectional view schematically showing the general structure of a horizontal IGBT with an anode short structure to which a second embodiment of the present invention is applied.

In the case of the configuration of the second embodiment shown in FIG. 2, in the configuration of the first embodiment described above, an n-type buffer region 31 is provided at a position spaced apart from the p-type base region 15 on the surface of the low-type semiconductor layer 12. and p0 type drain regions 32.3 arranged in parallel with each other within the n type buffer region 31.
2, and each of these p-type drain regions 2
．． 32, a drain electrode 33 made of a metal electrode for forming a Schottky junction with the n-type buffer region 31 is provided. That is, the difference from the configuration of the first embodiment is that the n-type buffer region 31 and each p
After forming the "type drain regions 32 and 32 in the conventional manner, an n'' type stiff contact region for ohmic contact is omitted, and an n type buffer region 32 is formed instead.
1 and a drain electrode 33 as a metal electrode forming a Schottky junction.

Therefore, in the horizontal IGBT with the anode short structure of the second embodiment configured as described above, the n-type buffer region 31
Because the potential of increases by an amount equivalent to the Schottky voltage,
Even in the low current region, each p0 type drain region 32.32
The injection of holes from the 1st embodiment is started, conductivity modulation is more likely to occur, and the on-state voltage is lowered in the normally used current range. You can get it.

Next, FIG. 3 is a sectional view schematically showing the general structure of a horizontal IGBT with an anode short structure to which a third embodiment of the present invention is applied.

In the case of the configuration of the third embodiment shown in FIG. 3, in the configuration of the first embodiment described above, the p-type base region 15 is selectively formed on a part of the surface of the n-type semiconductor layer 12, and An n0 type source region 16 and a p0 type contact region 41 for ohmic contact are selectively formed in a part of the p type base region 15, and as in the case of the configuration of the second embodiment, n at a position spaced apart from the p-type base region 15 on the surface of the n-type semiconductor layer 12.
The n-type buffer region 31 is formed, and the n-type drain regions 3232 are formed in parallel with each other in the n-type buffer region 31. A drain electrode 43 with a polysilicon resistance layer 42 interposed between it and the type buffer region 31
This is what I connected it to. That is, the difference from the configuration of the first embodiment is that the n-type buffer region 31 and each p-type drain region 2.32 are formed in the conventional manner, and then
The 01 type contact region for ohmic contact is omitted, and a polysilicon resistance layer 42 is used instead.
A drain electrode 33 is connected to an n-type buffer region 31 via.

Therefore, in the lateral IGBT with the anode short structure of the third embodiment configured as described above, when an electron current flows from the n-type buffer region 31 through the polysilicon resistance layer 42, in addition to the voltage drop in the n-type buffer region 31, Due to the voltage drop occurring in the polysilicon resistance layer 42,
Conductivity modulation is more likely to occur even in the low current range, and the on-state voltage is lowered in the normally used current range.
Here, too, the same functions and effects as in the first embodiment can be obtained.

〔Effect of the invention〕

As detailed above, according to the first aspect of the present invention,
A first conductivity type drain region and a second conductivity type buffer region surrounding the first conductivity type drain region are formed in a bent shape within a specific range on the surface of the second conductivity type high resistivity semiconductor layer. As a result, the length of the second conductivity type buffer region directly under the first conductivity type drain region can be substantially sufficiently increased without significantly increasing the required area. Since a voltage drop can be obtained, conductivity modulation can easily occur as desired even in a low current range, and the on-state voltage can be easily lowered in a normally used current range.

Further, according to the second aspect of the present invention, a second conductivity type buffer region and a first conductivity type drain region selectively formed within the buffer region are provided, and a second conductivity type buffer region and a first conductivity type drain region are selectively formed within the buffer region. Since the drain electrode made of a metal electrode for forming a Schottky junction is provided, the potential of the second conductivity type buffer region increases by an amount equivalent to the Schottky voltage, and even in a low current region, the potential of the second conductivity type buffer region rises from the first conductivity type drain region. The injection of holes starts, and conductivity modulation occurs, making it possible to lower the on-state voltage in the normally used current range.

Furthermore, according to the third aspect of the present invention, a second conductivity type buffer region and a first conductivity type drain region selectively formed within the buffer region are provided, and the second conductivity type buffer region and the first conductivity type drain region are selectively formed within the buffer region. Since the drain electrode is provided through the resistive layer between the buffer regions, an electron current flows from the second conductive type buffer region through the resistive layer, and in addition to the voltage drop in the second conductive type buffer region, the voltage in the resistive layer decreases. As a result, conductivity modulation is likely to occur in the low current range (this also makes it possible to lower the on-voltage in the normally used current range).

That is, in the present invention, by employing each of the constituent means described above, it is possible to easily generate conductivity modulation even in a low current region without significantly increasing the element area. It has excellent features such as low on-voltage in the normally used current range, less negative resistance characteristics that cause noise generation, and useful for highly integrated device configurations. be.

[Brief explanation of drawings]

FIG. 1(a) is a cross-sectional view schematically showing the general configuration of a horizontal IGBT with an anode short structure to which the first embodiment of the present invention is applied, and FIG. 1(b) is a plane view showing the buffer region and drain region of the same. Pattern diagram, Figure 2 is the same as above.
Horizontal IG with anode short structure to which the embodiment is applied
A sectional view schematically showing the general configuration of BT, FIG. 3 is a horizontal type I with an anode short structure to which the third embodiment of the above is applied
It is a sectional view schematically showing the general configuration of GBT, and also
Figure 4 shows a horizontal IGB with a conventional anode short structure.
FIG. 5 is a graph showing a comparison of the V-■ characteristics of a horizontal IGBT with an anode short structure and a horizontal IGBT with a non-anode short structure;
FIG. 6 is a cross-sectional view schematically showing the general structure of a horizontal IGBT with a conventional improved anode short structure. 11... p- (or n+) type semiconductor substrate, 12.
...n-type semiconductor layer, 13...p+ type buried layer, 14...element isolation region, 15...p-type base region, 16...n0-type source region, 17 ... Gate electrode, 18... Gate insulating film, 19... Source electrode, 20... N-type buffer region having a bent shape, 21...
...p-type drain region 21a having a bent shape...
...Parallel portion of p9 type drain region, 22...n°
type contact region, 23... drain electrode, 31... n type buffer region, 32... p4 type drain region, 33... drain electrode of Schottky junction using metal electrode, 41...・P4 type contact region, 42...polysilicon resistance layer, 50...horizontal IGBT with anode short structure
V-I characteristics of

Claims (3)

[Claims] (1) A first or second conductivity type semiconductor substrate, a second conductivity type high specific resistance semiconductor layer formed on this semiconductor substrate, and selectively formed on a part of the surface of the second conductivity type semiconductor layer. a base region of a first conductivity type, a source region of a second conductivity type selectively formed on a part of the surface of the base region, and a source region of a first conductivity type sandwiched between the source region and the semiconductor layer of the second conductivity type. a gate electrode provided on the surface of the conductive type base region via an insulating layer; a source electrode ohmically connected to the source region; and a source electrode located on the surface of the second conductive type semiconductor layer at a position away from the base region. , a second conductivity type buffer region selectively formed so that at least both side portions form a series of bent shapes; and a first conductivity type drain region selectively formed in the buffer region following the bent shape. A lateral conductivity modulation type semiconductor device comprising: a drain electrode which is ohmically connected to both the drain region and the buffer region. (2) A first or second conductivity type semiconductor substrate, a second conductivity type high specific resistance semiconductor layer formed on this semiconductor substrate, and selectively formed on a part of the surface of the second conductivity type semiconductor layer. a base region of a first conductivity type, a source region of a second conductivity type selectively formed on a part of the surface of the base region, and a source region of a first conductivity type sandwiched between the source region and the semiconductor layer of the second conductivity type. A gate electrode provided on the surface of the conductive type base region via an insulating layer, a source electrode ohmically connected to the source region, and a selective electrode provided on the surface of the second conductive type semiconductor layer at a position away from the base region. a second conductivity type buffer region formed in the buffer region, a first conductivity type drain region selectively formed within the buffer region, and a metal electrode provided to form a Schottky junction with the second conductivity type buffer region. 1. A lateral conductivity modulation type semiconductor device comprising: a drain electrode consisting of a drain electrode; (3) A first or second conductivity type semiconductor substrate, a second conductivity type high specific resistance semiconductor layer formed on this semiconductor substrate, and selectively formed on a part of the surface of the second conductivity type semiconductor layer. a base region of a first conductivity type, a source region of a second conductivity type selectively formed on a part of the surface of the base region, and a source region of a first conductivity type sandwiched between the source region and the semiconductor layer of the second conductivity type. A gate electrode provided on the surface of the conductive type base region via an insulating layer, a source electrode ohmically connected to the source region, and a selective electrode provided on the surface of the second conductive type semiconductor layer at a position away from the base region. a second conductivity type buffer region formed in the buffer region, a first conductivity type drain region selectively formed within the buffer region, and a drain provided through a resistance layer between the second conductivity type buffer region; 1. A lateral conductivity modulation semiconductor device comprising: an electrode;