JPH04217322A - Gate wiring of thin film transistor circuit - Google Patents

Abstract

PURPOSE:To provide the gate wiring of a film transistor circuit, where favorable ohmic contact can be gotten even if the gate wiring is put in the three-layer structure of Ta/Cu/Ta. CONSTITUTION:The gate wiring of a film transistor is constituted of, from the side of the lower layer, the first metallic layer 12, the second metallic layer 13, which has copper for its main ingredient, and the third metallic layer 14, and the third metallic layer 14 is made of metal such as molybdenum (Mo), chromium (Cr), or the like, where favorable ohmic contact can be gotten between connection layers.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to gate wiring for thin film transistor circuits.

0002

[Prior Art] In an array of thin film transistors (hereinafter referred to as a thin film transistor array),
Some devices use copper (Cu) for the gate electrode and gate wiring in order to reduce the resistance value of the gate electrode and gate wiring. Usually, tantalum (Ta) layers are formed above and below the copper layer to protect the copper layer, and Ta/Cu/T
It has a three-layer structure.

0003

However, in the conventional gate wiring structure described above, since the upper layer is formed using tantalum, the surface thereof is easily oxidized to form tantalum oxide. Therefore, there was a problem in that it was difficult to obtain good ohmic contact with the connection layer connected on the tantalum layer.

SUMMARY OF THE INVENTION An object of the present invention is to provide a gate wiring for a thin film transistor circuit in which good ohmic contact can be obtained even if the gate wiring has a three-layer structure.

[0005]

[Means for Solving the Problems] The gate wiring of the thin film transistor circuit according to the present invention has a three-layer structure, and the gate wiring has a good electrical connection between the upper layer of the gate wiring and the connection layer connected thereon.
It is formed of a metal layer (for example, a metal layer whose main component is a metal such as molybdenum (Mo 2 ) or chromium (Cr 2 )) that can provide microcontact.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 to 3 are cross-sectional views showing the manufacturing process of gate electrodes and gate wiring of a thin film transistor array.

Glass is used for the insulating substrate 11. A titanium (Ti) layer is used for the first metal layer 12, and the layer thickness is 50 to 100 nm. A copper (Cu) layer is used for the second metal layer 13, and the layer thickness is 200 nm. A molybdenum (Mo 2 ) layer or a chromium (Cr 2 ) layer is used for the third metal layer 14, and the layer thickness is 50 nm.

Next, the manufacturing process will be explained using FIGS. 1 to 3.

(A) A titanium layer that will become the first metal layer 12 is formed on the insulating substrate 11 by sputtering. The titanium layer has strong adhesion to the glass substrate 11 and is unlikely to peel off. Subsequently, a copper layer that will become the second metal layer 13 is formed on the first metal layer 12 by sputtering. Continue with the second metal 13
A molybdenum layer or a chromium layer, which will become the third metal layer 14, is formed thereon by sputtering. A mask layer 15 having a planar shape of a gate electrode and a gate wiring is formed on the third metal layer 14 using a photoresist (see FIG. 1).

(B) Using the mask layer 15 as a mask, the first metal layer 12,
The second metal layer 13 and the third metal layer 14 are etched. The third metal layer 14 and the second metal layer 13 are wet-etched using the same wet etching solution. As the etching solution, a mixed aqueous solution of nitric acid + acetic acid + ceric ammonium nitrate (Ce (NH4) 2 (NO3) 6 ) is used. Note that when a molybdenum layer is used as the third metal layer 14, it is not necessarily necessary to mix nitric acid. The side walls of the third metal layer 14 and the second metal layer 13 are tapered.
In order to form the third metal layer 14, the mixing ratio of the oxidizing agent (acetic acid, nitric acid) contained in the etching solution is appropriately selected so that the etching rate of the third metal layer 14 is higher than that of the second metal layer 13. Just make it bigger. After etching the third metal layer 14 and the second metal layer 13, the first metal layer 12 is etched using dilute hydrofluoric acid boiling or phosphoric acid aqueous solution boiling. Note that the first step is performed using a dry etching method using CF4 gas, etc.
The metal layer 12 may also be etched (see FIG. 2).

(C) Mask layer 15 is removed, and a gate electrode and gate wiring having a tapered shape are formed (see FIG. 3).

FIG. 4 is a cross-sectional view of a thin film transistor in a thin film transistor array.

This thin film transistor is manufactured by forming a silicon nitride layer 15 (thickness: 100-150 mm) to serve as a gate insulating layer after forming a gate electrode and a gate wiring in the steps shown in FIGS. 1 to 3.
nm) and silicon oxide layer 16 (layer thickness 400-500 nm)
nm), an amorphous silicon layer 17, an n+ amorphous silicon layer 18, and an ITO (indium tin oxide) layer 19 serving as a source electrode and a drain electrode.

FIG. 5 is a cross-sectional view showing the vicinity of the terminal end of the gate wiring in the thin film transistor array, which is produced at the same time as the formation of the thin film transistor shown in FIG. Therefore, silicon nitride layer 15, silicon oxide layer 16, and ITO layer 19 are formed at the same time as those labeled with the same numbers in FIG. The ITO layer 19 (connection layer) shown in FIG. 5 serves as a connection terminal for connecting the gate wiring to an external circuit.

In the embodiments described above, the metal forming the third metal layer 14 is molybdenum or chromium, but it may be made of other metals as the main component. As for the gate electrode, it may be one whose main component is a metal that can be easily wet-etched. In particular, it is preferable that the third metal layer (copper layer) 14 and the second metal layer 13 can be etched using the same wet etching solution. As for the gate wiring, any material may be used as long as the main component is a metal that can provide good ohmic contact with the conductive connection layer using the ITO layer 19 or the like.

[0016]

According to the present invention, good ohmic contact can be obtained between the upper layer of the three-layered gate wiring and the connection layer connected thereon.

[Brief explanation of the drawing]

FIG. 1 is an embodiment of the present invention, and is a cross-sectional view showing the manufacturing process of a gate electrode and gate wiring of a thin film transistor array.

FIG. 2 is an embodiment of the present invention, and is a cross-sectional view showing the manufacturing process of a gate electrode and gate wiring of a thin film transistor array.

FIG. 3 is an embodiment of the present invention, and is a cross-sectional view showing the manufacturing process of a gate electrode and gate wiring of a thin film transistor array.

FIG. 4 is an embodiment of the present invention, and is a cross-sectional view of a thin film transistor in a thin film transistor array.

FIG. 5 is an embodiment of the present invention, and is a cross-sectional view showing the vicinity of the terminal end of a gate wiring in a thin film transistor array.

[Explanation of symbols]

11...Insulating substrate 12...first metal layer 13...Second metal layer 14...Third metal layer

Claims (2)

[Claims] Claim 1: A first plate formed on the main surface side of an insulating substrate.
a metal layer, a second metal layer formed on the first metal layer in substantially the same shape as the first metal layer and mainly containing copper (Cu), and a second metal layer on the second metal layer, A gate wiring for a thin film transistor circuit comprising a third metal layer which is formed in substantially the same shape as the third metal layer and which provides good ohmic contact with a connection layer connected thereon. 2. The third metal layer is molybdenum (Mo
) or chromium (Cr) as a main component.
wiring.