JPH04218096A - Modulation signal generator - Google Patents

Abstract

PURPOSE:To generate fresh modulation signals by setting the channels to be synthesized and synthesizing the waveform signals for modulation of the plural channels and to allow the modulation control deviated in phase between the channels by setting the initial phase of the modulation signals for the plural channels. CONSTITUTION:The waveform signals for modulation are read out of a waveform table 2 time-dividedly by each of the respective channels according to the frequencies set by every channel. The channels to be synthesized are set by a synthesis control table 14 and the computation to synthesize the waveform signals of the respective channels according to this output MXD. The initial phase of each of the respective channels is set by a phase shift table 11 and the reading out address of the waveform table 2 is shifted by the output thereof. The waveform signals to be read out are the signals shifted in phase by as much as the set initial phase.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for generating a modulation signal for imparting a modulation effect to a musical tone signal in an electronic musical instrument, a musical tone effect imparting device, or the like.

0002

2. Description of the Related Art Many modulation waveform generators are used in electronic musical instruments to provide various modulation effects such as vibrato, tremolo, and ensemble. For example, Japanese Patent Laid-Open No. 52-112313 discloses providing separate modulation waveform generators for each modulation effect of frequency modulation, timbre modulation, and amplitude modulation. Also, Utsukko Sho 53-1338
No. 2 is equipped with multiple series of modulated waveform generators separately, and shifts the phase of the modulated waveform signal generated by each by a predetermined amount,
It has been shown to synthesize a plurality of modulated waveform signals having different frequencies or phases to obtain a special modulated waveform signal. Further, Japanese Utility Model Application No. 57-88193 discloses providing a separate modulation waveform generator for each of a plurality of tone generation sequences.

Furthermore, Japanese Patent Laid-Open No. 58-83894 discloses that a plurality of modulation signals are generated in a time-division manner, and different modulations are applied to a plurality of input signals in a time-division manner. Japanese Patent Laid-Open No. 57-99696 discloses forcibly synchronizing the phases of independently generated modulation signals in a plurality of sequences. Japanese Patent Laid-Open No. 58-25696 discloses that a plurality of modulation signal waveforms stored in a storage device can be selectively selected and read out.

0004

[Problems to be Solved by the Invention] In all of the above-mentioned conventional modulation signal generation devices, it is difficult to combine modulation signals generated in multiple channels to create a new modulation signal, or to arbitrarily select a combination channel for that purpose. Nothing is shown about freely synthesizing modulated signals by changing settings. In addition, the initial phase of the modulation signal generated in multiple channels can be freely set to create a polyphase modulation waveform (multiple modulation waveforms with different phases), making it possible to control modulation with a phase shift between channels. Nothing is shown about freely setting the initial phase for each channel.

The present invention has been made in view of the above-mentioned points, and enables formation of a modulation waveform by synthesis or multiphase modulation waveform when modulation signals are generated independently in each channel. By making it possible to freely set the synthesis channel for this purpose and to freely set the initial phase of the generated modulation waveform for each channel, we have developed a modulation signal generation device that can freely synthesize modulation signals. This is what we are trying to provide.

[0006]

[Means for Solving the Problems] A modulation signal generation device of the present invention includes a waveform table storing predetermined waveforms and a time division channel for setting time division timing of a plurality of channels for generating a modulation waveform signal. a setting means, a frequency setting means for setting the frequency of a modulation waveform signal to be generated in each channel, and setting by the time division channel setting means in accordance with the frequency set corresponding to each channel by the frequency setting means. reading means for reading out the waveform signals for each channel from the waveform table at the time division timing determined by the waveform table; a combination channel setting means for setting a channel to which the modulation waveform signal is to be combined; A first feature of the present invention is that it further comprises a combining means for performing a computation to combine the waveform signals of the channels set by the combining channel setting means among the waveform signals of the respective channels.

The modulation signal generation device of the present invention also includes a waveform table storing predetermined waveforms, and time division channel setting means for setting time division timing of a plurality of channels for generating a modulation waveform signal. a frequency setting means for setting the frequency of a modulation waveform signal to be generated in each channel; and a time-sharing method set by the time-division channel setting means in accordance with the frequency set corresponding to each channel by the frequency setting means. readout means for reading out the waveform signals for each channel from the waveform table at timing, phase shift setting means for setting for each channel an initial phase of the waveform signal for each channel to be read out from the waveform table; A second feature is that the device further comprises phase shift means for shifting the phase address for reading out the waveform table in the reading means in accordance with the initial phase of each channel set by the phase setting means.

[0008]

[Operation] The modulation waveform signal is read out from the waveform table in a time-division manner for each channel according to the frequency set for each channel. According to the first feature, the synthesis channel setting means arbitrarily sets the channels on which the modulation waveform signals are to be synthesized, and the synthesis means sets the channels among the waveform signals of each read channel by the synthesis channel setting means. Performs computation to synthesize waveform signals of the channels. Therefore, it is possible to create a new modulation waveform by synthesizing the modulation waveform signals generated in any channel.
It is possible to freely synthesize modulated signals.

According to the second feature, the phase shift setting means:
Set the initial phase of the waveform signal for each channel arbitrarily,
Under the control of the phase shift means, the waveform signal of each channel is read out from the waveform table with the phase shifted by the set initial phase. Therefore, modulation control can be performed with an arbitrary phase shift between channels depending on the settings of the initial phase of the generated modulation waveform for each channel, and the degree of freedom in modulation control can be increased.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the accompanying drawings. In FIG. 1, the channel counter 1 corresponds to a time division channel setting means for setting the time division timing of a plurality of channels, and if the number of channels is 16, it consists of a modulo 16 counter, and the master clock pulse φM is Count to 0
Channel number data CHD from 1 to 15 are generated sequentially in a time-division manner. FIG. 2 is a diagram showing how channel number data CHD changes in response to master clock pulse φM. 16 time-divided from 0 to 15
In each channel, 16 modulated signals are generated independently.

The waveform table 2 stores one or more different waveforms (for example, sine waves, triangular waves, etc.).
If a plurality of waveforms are stored, one waveform to be read out is selected according to waveform selection data WSEL from the waveform selection table 3, as will be described later.

A reading means for reading out the waveform table 2 is a random access memory (hereinafter referred to as RAM) 4.
and an adder 5. The RAM 4 has as many addresses as the number of channels for storing phase address data qF for reading the waveform table, and the write address input WA is given the channel number data CHD output from the channel counter 1, and the read address The output of a synchronization channel table 6, which will be described later, is applied to the input RA.

The readout output of the RAM 4 is applied to an adder 5, and the output of the adder 5 is applied to the phase address input of the waveform table 2 via an adder 7 for phase shifting, and is also applied to the data write input of the RAM 4. It will be done. The other input of the adder 5 receives frequency data F, which is an increment value (change value) of the phase address data qF per calculation unit time.
It is given from the frequency data table 8 via the gate 9.

The frequency data table 8 stores frequency data F for each channel, which sets the frequency of the waveform signal to be read from the waveform table 2, and the frequency data F for each channel corresponds to the channel number data CH.
D is read out in a time-division manner. Gate 9 is provided for synchronous control, as will be described later, and is normally open (when synchronous control is not performed), and sends frequency data F read from table 8 to adder 5. The frequency data F is repeatedly added (or subtracted) in the phase accumulator constituted by the RAM 4 and the adder 5. That is, normal read control of the waveform table 2 specifies a certain channel as the read address of RAM 4 in the time slot of the channel, reads out the previous phase address data (q-1) F regarding the channel from RAM 4, and adds it. In the unit 5, frequency data F is added to this to create new phase address data qF (however, q is changed by 1 or 2 for each calculation unit time).
, 3, etc., indicating the cumulative number of F)
On the other hand, the corresponding channel is specified as the write address of the RAM 4, and the obtained phase address data qF is stored in the address of the corresponding channel. In this way, the frequency data F is independently accumulated in a time-division manner for each channel, and a phase address qF that successively changes at a rate of change corresponding to the set frequency is obtained in a time-division manner for each channel. As is well known, the accumulator consisting of the RAM 4 and the adder 5 has a predetermined modulo number, and the phase address data qF changes repeatedly using this modulo number as one cycle.

The synchronization channel table 6 stores, for each channel, the number data (synchronization channel data SCHD) of the channel to which the waveform signal of that channel should be synchronized. Synchronous channel data CHD for each channel is read out in a time-division manner. An example of the setting contents of this table 6 is shown in the following table. Of course, the setting is not limited to this and can be set in any manner.

Table 1 Input (CHD) │ 0 1 2 3 4
5 6 7 8 9 10 11 12 1
3 14 15──────┼────────────
───────────── Output (SCHD) │ 0
6 6 15 14 5 6 7 8
9 10 12 12 13 14 15

0017
]Channel in which synchronized channel data SCHD with the same value as its own channel number data CHD is stored (
0, 5, 6, 7, 8, 9, 10, 12, 13 in the above table,
14, 15) means that the waveform table 2 should be read out by the above-mentioned normal readout control without performing synchronous readout control. Channels with different data CHD and SCHD values (1, 2, 3, 4, 11 in the above table) mean that synchronous read control should be performed. Synchronous channel data S read from the synchronized channel table 6
CHD is applied to one input of the comparator 10, and is also applied to the read address input RA of the RAM 4 as described above. Channel number data CHD from the counter 1 is applied to the other input of the comparator 10. When the values of both inputs match, the comparator 10 generates a match signal EQ of "1", thereby opening the gate 9. If there is no match, match signal EQ
is "1" and gate 9 is not opened.

To explain normal read control using channel 6 in Table 1 as an example, the value of synchronous channel data SCHD read from synchronous channel table 6 in the time-division time slot of channel 6 is the channel number data at that time. Since the value is "6", which is the same as the value of CHD, the match signal EQ is output from the comparator 10, the gate 9 is opened, and the frequency data F of channel 6 is sent to the adder 5.
given to. At this time, the same channel 6 is used for the write address input WA and read address input RA of RAM4.
Channel number data CHD and synchronization channel data SCHD specifying this are input. Therefore, as described above, in the time-division time slot of channel 6, the frequency data F of channel 6 is repeatedly added, and phase address data qF corresponding to the frequency set for channel 6 is generated.

Synchronous read control will be explained using channel 1 in Table 1 as an example. The value "6" of the synchronized channel data SCHD read from table 6 in the time-division time slot of channel 1 is the channel number at that time. Because it is different from the data CHD value "1",
No match signal EQ is output, gate 9 is closed, and frequency data F is not provided to adder 5. On the other hand, since the data SCHD indicating channel "6" is given to the read address input RA of RAM4, the phase address data qF of channel 6 is read out from RAM4 even though it is the time division timing of channel 1. , this is input to the waveform table 2 via adders 5 and 7 as phase address data of channel 1. thus,
The phase address data qF for reading the wave number table of channel 1 is forcibly synchronized with the phase address data qF of channel 6, and the frequencies of both channels become the same.

The phase shift table 11 stores initial phase data θ for each channel, which sets the initial phase of the waveform signal of each channel, and stores the initial phase data θ of each channel according to the channel number data CHD from the counter 1. Read out θ in a time-division manner. This initial phase data θ
is given to the adder 7 and added to the phase address data qF from the adder 5. The output qF+θ of the adder 7 is applied to the phase address input of the waveform table 2. In this way, the phase address data qF for reading out the waveform table 2 is phase-shifted independently for each channel according to the initial phase data θ for each channel, and independent phase shift control is realized for each channel.

The waveform selection table 3 is provided when a plurality of different waveforms are stored in the waveform table 2, and stores waveform selection data WSEL for each channel for selecting a waveform to be read out. , which are read out in a time-division manner according to channel number data CHD. If there is only one type of wave number stored in waveform table 2, this waveform is used as the phase address data q for each channel.
It is read out in a time-division manner according to F+θ (qF when θ is 0). If multiple types of waveforms are stored in waveform table 2, waveform selection data WSE for each channel
A waveform is time-divisionally selected by L, and the selected waveform is used as the phase address data qF+ corresponding to the channel.
It is read out according to θ (or qF).

The waveform signals of each channel read out in a time-division manner from the waveform table 2 are input to an adder 12 for waveform synthesis. The output of the adder 12 is supplied to an appropriate modulation effect imparting circuit (not shown) as an output signal (that is, a modulation signal) of the modulation signal generator, and is also input to the register 13. The register 13 is for delaying the waveform signal of each channel by the time slot length of one channel, and captures the waveform signal related to that channel at the end of the time slot of each channel according to the master clock pulse φM. Output the waveform signal during the time slot of the next channel. This register 1
The output of the synthesis control table 14 is given to the clear input of No. 3, and this clear input signal is "1".
When it is "0", the waveform signal of the previous channel is given to the adder 12 from the register 13 without clearing the contents of the register 13, but when it is "0", the contents of the register 13 are cleared and the waveform signal of the previous channel is given to the adder 12. The waveform signal is prevented from being applied to the adder 12.

The synthesis control table 14 stores synthesis control data MXD for each channel indicating whether or not to add and synthesize the waveform signal of the previous channel and the waveform signal of its own channel, and stores the synthesis control data MXD for each channel according to the channel number data CHD. The composite control data MXD of each channel is read out in a time-division manner. This data MXD is "1" when the waveform signal of the previous channel and the waveform signal of the own channel should be added together, and is "0" otherwise. An example of the setting contents of the table 14 is shown in the following table.

Table 2 Input (CHD) │ 0 1 2 3 4
5 6 7 8 9 10 11 12 1
3 14 15──────┼────────────
───────────── Output (MXD) │ 1
0 1 1 0 0 0 0 0
0 0 1 0 0 0 1

0025
] Taking channels 1, 2, and 3 in the above table as an example, the synthesis control will be explained. In the time slot of channel 1, the synthesis control data MXD read from the table 14 is "0", and the synthesis control data MXD of the previous channel 0 is "0". The waveform signal is cleared in register 13, so channel 1
The waveform signal is output from the adder 12 as it is without being mixed with the waveform signals of other channels. next channel 2
In the time slot, the composite control data MXD is “1”
Therefore, the immediately preceding waveform signal of channel 1 is not cleared by the register 13 but is given to the adder 12. Therefore, a signal obtained by adding the waveform signals read from the waveform table 2 on channels 1 and 2 is output from the adder 12 in the channel 2 time slot, and this is finally output as the channel 2 modulation signal. next channel 3
In the time slot, the composite control data MXD is “1”
Therefore, the signal output from the adder 12 in the immediately preceding channel 2 time slot, that is, the summed combined waveform signal of channels 1 and 2, is not cleared by the register 13 and is given to the adder 12 as is. Therefore, a signal obtained by adding the three waveform signals read from the waveform table 2 on channels 1, 2, and 3 is output from the adder 12 in the time slot of channel 3, and this is finally output as the modulation signal of channel 3. be done.

In the example of FIG. 1, the output of the adder 12 is delayed by the register 13, but the readout output of the waveform memory 2 is delayed by the register 13, and this delayed output and the readout output of the waveform memory 2 are It may be added. Also, instead of the register 13, the adder 1 is operated by a delay circuit whose delay is controlled by the master clock pulse φM.
The output of waveform table 2 or the output of waveform table 2 may be delayed, and a gate circuit may control whether or not this delayed output is provided to adder 12 in accordance with synthesis control data MXD.

Furthermore, in the example shown in FIG. 1, the channels that can be combined are limited to adjacent channels, but the delay time in the delay means (register 13) may be set to two or more time slots, in which case the channels that can be combined are Synthesis can also be performed between. Furthermore, in order to perform waveform synthesis between arbitrary channels, the register 13 (ie, delay means) may be modified as shown in FIG. 3. In FIG. 3, the shift register 15 which has 15 stages, one less than the number of channels, has an adder 12.
The output signal of (FIG. 1) is input and sequentially shifted according to master clock pulse φM. Therefore, each stage of the shift register 15 holds the latest sample point amplitude data of the waveform signal of each channel. The outputs of each stage of the shift register 15 are inputted in parallel to the selector 16 and selected according to the synthesis control data MXD' given from the synthesis control table 14. The selected signal is applied to adder 12. In this case, in the synthesis control table 14, data indicating the stage number of the shift register 15 in which the waveform signals of the channels to be synthesized are stored is stored for each channel as synthesis control data MXD', and this data MXD ' is read out corresponding to the time division timing of each channel. The selector 16 selects the output of the stage designated by the synthesis control data MXD'. Therefore, waveform synthesis with any channel is possible by arbitrarily setting the contents of the synthesis control data MXD' corresponding to each channel. Note that the input signal of the shift register 15 is based on the waveform table 2.
It may be the output signal of

The configuration for generating phase address data is not limited to the one using the RAM 4 as shown in the figure, but other configurations can be used as desired based on the design. Further, the configuration for synchronous control is not limited to the one using the comparator 10 and gate 9 as shown in the figure, but any configuration may be used as long as it can achieve the desired synchronous control. For example, Figure 4
As shown in FIG. 2, the comparator 10 and the gate 9 may be omitted, the output F of the frequency data table 8 may be directly input to the adder 5, and the read output of the RAM 4 may be provided to the adder 7. Further, the adder 7 for phase shift or the adder 12 for waveform synthesis is not limited to addition, but may be configured to perform subtraction or other operations. In particular, adder 12 may be a multiplier.

Each table 3, 6, 8, 11, 14 may be composed of an electronic storage circuit, or may be composed of data setting means such as a switch. In the case of an electronic storage circuit, a ROM (read only memory) in which desired settings are stored in advance may be used, or a rewritable one such as a RAM (random access memory) may be used. When a RAM is used, as shown in FIG.
It is preferable that the settings for each of channels 6, 8, 11, and 14 can be changed.

Furthermore, the waveform table 2 may have any configuration such as ROM, RAM, or a combination of a plurality of ROMs and RAMs. Note that the modulation signal generating device of the present invention is not limited to the hard-wired circuit as shown in the drawings, but can also be implemented by software processing using a microcomputer, and such implementation is also included in the scope of the present invention. .

[0031]

As described above, according to the present invention, when generating modulation waveform signals independently for each channel, channels to be combined are set and the modulation waveform signals of the plurality of set channels are generated. Since a new modulation signal can be created by combining, the excellent effect of freely combining modulation signals is achieved. Further, by setting the initial phase of the modulation waveform signals of a plurality of channels, it is possible to perform modulation control with a phase shift between the channels, which has the excellent effect of increasing the degree of freedom in modulation control.

[Brief explanation of the drawing]

FIG. 1 is an electrical block diagram showing one embodiment of a modulated signal generator according to the present invention.

FIG. 2 is a timing chart diagram showing the state of time-division time slots of each channel in the same embodiment.

FIG. 3 is a block diagram showing a modification example of the delay means for waveform synthesis in the same embodiment.

FIG. 4 is a block diagram showing a modification example of the synchronous control circuit portion in FIG. 1;

[Explanation of symbols]

1...Channel counter, 2...Waveform table, 3...Waveform selection table, 4, 5...RAM and adder for generating phase address data for reading the waveform table, 6...Synchronization channel table, 7...Addition for phase shift Vessel, 8...
Frequency data table, 9, 10... Gate and comparator for synchronization control, 11... Phase table, 12, 13... Adder and register as delay means for waveform synthesis, 14... Synthesis control table, 15... Shift register, 16...Selector, 17...Table setting device.

Claims (8)

[Claims] 1. A waveform table storing predetermined waveforms, a time division channel setting means for setting time division timings of a plurality of channels for generating waveform signals for modulation, and a waveform table for generating modulation waveform signals to be generated in each channel. A frequency setting means for setting the frequency of a waveform signal, and each channel is selected from the waveform table at the time division timing set by the time division channel setting means, according to the frequency set corresponding to each channel by the frequency setting means. reading means for reading out the waveform signals of each channel; a combination channel setting means for setting a channel to which the modulation waveform signal is to be combined; 1. A modulation signal generating device, comprising a combining means for performing an operation for combining waveform signals of channels set by the setting means. 2. The combining means includes a delay means for delaying the waveform signal of each channel read from the waveform table, and a delay means for delaying the waveform signal of each channel read from the waveform table, and a delay means for delaying the waveform signal of each channel read from the waveform table, and a delay means for delaying the waveform signal of each channel read from the waveform table, and using the output of the delay means to delay the waveform signal of the channel set by the synthesis channel setting means. 2. The modulated signal generating device according to claim 1, further comprising a calculation means for performing a calculation to combine the waveform signals. 3. The combination channel setting means comprises a readable and writable combination control table in which data indicating whether or not to combine is stored for each channel, and table setting means for rewriting and setting the stored contents of this table. The synthesis control table is read out according to the time division timing of each channel, the delay means delays the output of the calculation means by a predetermined number of time division time slots, and the calculation means 3. The waveform signal read from the waveform table and the output of the delay means are synthesized when the data read from the synthesis control table is data indicating that synthesis is to be performed. modulation signal generator. 4. The combination channel setting means comprises a readable and writable combination control table storing data specifying channels to be combined with each channel for each channel, and a table for rewriting and setting the stored contents of this table. the synthesis control table is read out according to the time division timing of each channel, and the delay means selects a shift register having a plurality of stages and an output of each stage of the shift register. 3. The modulated signal according to claim 2, further comprising a selection circuit, wherein the selection of the selection circuit is controlled according to the data read from the synthesis control table, and the selected output is provided to the calculation means. Generator. 5. The waveform table stores a plurality of different waveforms, and the reading means independently selects a waveform to be read from the waveform table for each channel, and reads each selected waveform signal. The modulated signal generating device according to claim 1, wherein the modulated signal generating device is configured as follows. 6. A waveform table storing predetermined waveforms, a time division channel setting means for setting time division timing of a plurality of channels for generating a modulation waveform signal, and a time division channel setting means for setting time division timing of a plurality of channels for generating a modulation waveform signal, and a waveform table storing a waveform signal for modulation to be generated in each channel. A frequency setting means for setting the frequency of a waveform signal, and each channel is selected from the waveform table at the time division timing set by the time division channel setting means, according to the frequency set corresponding to each channel by the frequency setting means. reading means for reading out the waveform signals of each channel, phase shift setting means for setting for each channel the initial phase of the waveform signal of each channel to be read from the waveform table, and each channel set by the phase shift setting means. and a phase shifter for shifting a phase address for reading out the waveform table in the readout means according to an initial phase of the modulation signal generator. 7. The phase shift setting means includes a readable and writable phase shift table storing initial phase data for each channel, and table setting means for rewriting and setting the stored contents of this table. 7. The modulated signal generating device according to claim 6, wherein the phase shift table is read out according to time division timing of each channel. 8. The waveform table stores a plurality of different waveforms, and the reading means independently selects a waveform to be read from the waveform table for each channel, and reads each selected waveform signal. 7. The modulated signal generating device according to claim 6.