JPH04218925A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable distributions of impurity concentrations in a source/drain region to be controlled suitably, by forming sidewall spacers with a predetermined number of the layers of oxide insulation films through depositing insulation films on the respective sidewalls of gate electrodes and applying anisotropic etchings thereto. CONSTITUTION:After gate electrodes 17, 18 are formed, sidewall spacers 21, 22 of a first layer are formed. Thereafter, after sidewall spacers 27, 28 of a second layer are formed, sidewall spacers 41, 42 are formed. That is, the sidewall spacers comprising a plurality of layers are formed by repeating the depositions of oxide insulation films through CVD and anisotropic etchings plural times in succession, and even during those formations, the formations of resist films and the implantations of impurity ions are performed selectively too. Further, the resist films are removed, and the heat treatment of a predetermined condition, in which respective diffusion layers are activated, is performed, and then, the state shown in the figure is brought. Thereby, at need, every sidewall spacer, its width can be made different from others.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device including a field effect transistor and a method for manufacturing the same, and particularly to a method for suppressing hot carrier effects by reducing the peak electric field strength of a drain depletion layer that occurs in a pinch-off state. L.D.
MOS (Metal Oxide Se) having D (Lightly Doped Drain) structure
The present invention relates to a structure of a semiconductor device including a microconductor type field effect transistor and a method of manufacturing the same.

0002

[Prior Art] The basic structure of a MOS field effect transistor is that a so-called MOS capacitor has a metal electrode provided on a Si substrate with a thin oxide film interposed therebetween, and a source serving as a carrier supply source and a carrier supply source on both sides of the MOS capacitor. A drain for taking out the water is arranged. The metal electrode on the oxide film has a function of controlling the conductance between the source and drain, and is called a gate electrode. The gate electrode is often made of polysilicon doped with impurities or metal silicide formed by heat-treating a high-melting point metal such as tungsten deposited on polysilicon in an inert gas.

[0003] When the voltage of the gate electrode (gate voltage) is lower than the threshold voltage Vth required to invert the conductivity type near the Si substrate surface (channel) between the source and drain, both the source and drain are pn. They are separated by a junction and no current flows through them. When a gate voltage equal to or higher than Vth is applied, the conductivity type of the channel surface is reversed, a layer of the same conductivity type as the source/drain is formed in this portion, and a current flows between the source/drain.

By the way, if the impurity concentration distribution at the boundary between the source/drain and the channel changes rapidly, the electric field strength at this portion increases. This electric field gives carriers energy and generates so-called hot carriers. Then, these carriers are injected into the gate insulating film and generate an interface level at the interface between the gate insulating film and the semiconductor substrate, or are trapped in the gate insulating film. Therefore, the threshold voltage and transconductance of the MOS transistor deteriorate during operation. This is a phenomenon in which MOS transistors deteriorate due to hot carriers. Moreover, the so-called avalanche breakdown voltage against avalanche breakdown between the source and drain is also degraded by hot carriers. Therefore, by lowering the n-type impurity concentration near the source/drain and making the change in concentration distribution gentle, the electric field strength is alleviated. This suppresses deterioration of the MOS transistor due to hot carriers, and also reduces the avalanche breakdown voltage of the source/drain. MOS is designed to improve
This is a type LDD structure field effect transistor.

As a conventional method for manufacturing a MOS type LDD structure field effect transistor, for example, FIGS.
There are some things shown below. In this manufacturing method, first, a gate insulating film 3 is formed on a p-type semiconductor substrate 1 by a so-called LOCOS method in an element formation region surrounded by an element isolation insulating film 2 (FIG. 37). Next, in order to control the threshold voltage, a p-type impurity such as boron ions is implanted into the entire surface of the semiconductor substrate 1 as necessary to form an ion implantation region 4 (
Figure 38). Thereafter, a polysilicon film is deposited over the entire surface of the gate insulating film 3 by low pressure CVD, and a gate electrode 5 is formed by photolithography and reactive ion etching (FIG. 39). As the gate electrode 5, instead of polysilicon, a high-melting point metal such as tungsten, molybdenum, or titanium, or a silicided version of these metals is used.
It may be formed with a two-layer film of polysilicon. This gate electrode 5 is doped with, for example, phosphorus ions to improve conductivity.

Next, using the gate electrode 5 as a mask, n-type impurities such as phosphorus ions and arsenic ions are applied to the semiconductor substrate 1.
An n-type ion implantation layer 6 is formed by implanting perpendicularly to the surface (FIG. 40). Thereafter, an insulating film such as silicon dioxide is deposited on the entire surface of the semiconductor substrate 1 by low pressure CVD or normal pressure CVD, and anisotropic etching is performed on this to form sidewall spacers 7 (FIG. 41). Next, using both the gate electrode 5 and the sidewall spacer 7 as masks, n-type impurities such as phosphorus ions and arsenic ions are irradiated perpendicularly to the surface of the semiconductor substrate 1, and the ion-implanted layer 6 is
An n-type injection layer 8 having a higher concentration than the above is formed (FIG. 42). Thereafter, a heat treatment is performed to activate the implanted impurity ions, and a MOS type LDD structure field effect transistor is completed.

In the above conventional example, a p-type semiconductor substrate is used as the substrate, but a p-well, which is a region in which p-type impurities are implanted at least near the substrate surface, may also be used. Further, as the substrate, an n-type semiconductor substrate or a substrate in which an n-well, which is a region in which n-type impurities are implanted at least near the surface, is formed may be used. In this case, the gate electrode 5 is of a p-type, and the p-type ion implantation layers 6 and 8 are formed in the source/drain regions.

MO obtained by the above conventional manufacturing method
According to the S-type LDD structure field effect transistor, since the lower concentration ion implantation region 6 is provided on the side of the source/drain region adjacent to the channel, changes in the impurity concentration distribution in the source/drain region are alleviated. The electric field strength in this portion is reduced, and deterioration of the transistor due to hot carriers is prevented.

[0009]

[Problem to be solved by the invention] However, the conventional M
In the OS type LDD structure, the low concentration impurity diffusion layer (ion implantation layer 6) of the source/drain is diffused below the gate electrode 5 through high-temperature heat treatment in a subsequent process, and the source/drain and low concentration impurity diffusion layers are diffused below the gate electrode 5 and the source/drain. There is a problem in that parasitic capacitance is added between the drain region and the integrated circuit, which impedes the speeding up of integrated circuits and also impedes miniaturization of transistors.

Furthermore, when forming a field effect transistor having not only a channel of one conductivity type but also both n-type and p-type channels, such as in a complementary MOS type integrated circuit, the above-mentioned conventional method can be used. When an LDD structure is formed using this method, the diffusion coefficient of the impurity element implanted into the source/drain region differs depending on the type of impurity, so the width of the sidewall spacer that is optimal for the channel of one conductivity type is different from the width of the sidewall spacer that is optimal for the channel of the other conductivity type. There was a problem in that it was not necessarily optimal in the area of .

[0011] Furthermore, even in the case of field effect transistors with channels of the same conductivity type, even if it is desired to change the concentration profile of the impurity diffusion layer of the source/drain depending on the required performance, There is also the problem that it is not possible to obtain the optimum width of the sidewall spacer required for each transistor.

[0012] As prior art for solving the above problems, Japanese Patent Application Laid-Open No. 61-5571 and Japanese Patent Application Laid-Open No. 63-226055 are disclosed.
The manufacturing method described in Japanese Patent Application Laid-Open No. 63-24686 can be mentioned. The manufacturing methods described in these publications separately form sidewall spacers for an n-channel MOS transistor and a p-channel MOS transistor formed on the same semiconductor substrate, that is, sidewall spacers for a channel of one conductivity type are formed. In some cases, the active region of the channel of the other conductivity type is covered with a silicon nitride film or the like.

Typical examples of such conventional manufacturing methods are shown in FIGS. 43 to 50. In this manufacturing process, first, a gate electrode 5 is formed on each surface of a p-type region and an n-type region of a semiconductor substrate 1 separated by an element isolation insulating film 2, with a gate insulating film 3 interposed therebetween. . Next, after depositing a silicon nitride film 9a on the front surface of the semiconductor substrate 1 (FIG. 43), only the n-type region is covered with a resist mask (not shown), so that only the silicon nitride film 9a on the p-type region is deposited. remove. After removing the resist mask on the n-type region (FIG. 44), an insulating film 7a is deposited all over the semiconductor substrate 1 (FIG. 45). Thereafter, by performing reactive ion etching on the insulating film 7a, sidewall spacers 7b are formed.
, 7c (Fig. 46). Next, after removing the silicon nitride film 9a and sidewall spacers 7c on the n-type region (FIG. 47), only the silicon nitride film 9b on the p-type region is removed.
In this state, the insulating film 7 is again covered over the entire surface of the semiconductor substrate 1.
d (Figure 48). Thereafter, this insulating film 7d is subjected to reactive ion etching to form sidewall spacers 7e and 7f (FIG. 49). Thereafter, by removing silicon nitride film 9b and sidewall spacer 7e on the p-type region, sidewall spacers 7b and 7f are formed on the p-type region and the n-type region, respectively (FIG. 50).

According to the techniques described in these publications, the widths of the sidewall spacers of the p-type channel and the n-type channel can be made different as necessary. However, in this method, the resist film formation process only needs to be performed once for each channel region of one conductivity type;
Since only the sidewall spacers of the channel region of one conductivity type are formed, the CVD time for forming all the sidewall spacers becomes long. This poses a problem because the CVD processing time is relatively long compared to forming a resist film.

In view of the above-mentioned conventional problems, the present invention provides a field effect transistor having a MOS type LDD structure, which requires a relatively short CVD processing time and can vary the width of each sidewall spacer as required. The purpose is to provide a structure and a method for manufacturing the same.

[0016]

[Means for Solving the Problems] A semiconductor device of the present invention includes:
A semiconductor substrate having first and second field effect transistors is provided, and each field effect transistor has a gate electrode formed on the semiconductor substrate with a gate insulating film interposed therebetween, and sidewall surfaces on both left and right sides of the gate electrode. a first sidewall spacer made of a single layer of insulating film formed thereon;
It includes source/drain regions having high concentration and/or low concentration impurities, which are formed on the surface of the semiconductor substrate from the vicinity immediately below the right and left sides of the gate electrode to the outside. Further, at least the second field effect transistor includes another field effect transistor formed on at least one side wall surface of the gate electrode.
The second sidewall spacer of the second field effect transistor is for impurity implantation to form a high concentration impurity region on at least one sidewall side of the gate electrode. forming a mask.

In another aspect, the semiconductor device of the present invention includes a field effect transistor, which includes a semiconductor substrate having a first conductivity type region at least near the surface, and a gate on the semiconductor substrate. a gate electrode formed with an insulating film interposed therebetween; a first sidewall spacer formed on one side wall surface of the gate electrode and made of a predetermined number of layers of insulating films and having a predetermined width; A second sidewall spacer formed on the other sidewall surface of the electrode is made of a predetermined number of layers of an insulating film larger than the first sidewall spacer, and has a predetermined width larger than the first sidewall spacer. The semiconductor device includes a sidewall spacer and a second conductivity type source/drain region formed on the surface of the semiconductor substrate from just below the left and right side walls of the gate electrode to the outside.

The method of manufacturing a semiconductor device of the present invention is a method of manufacturing a semiconductor device including first and second field effect transistors having an LDD structure formed on the main surface of a semiconductor substrate of a first conductivity type. be. In this manufacturing method, first, a gate insulating film is interposed on the main surface of a semiconductor substrate, and a gate electrode is formed for each field effect transistor. Next, an oxide insulating film is deposited on both left and right side wall surfaces of the gate electrode, and is subjected to anisotropic etching to form first sidewall spacers. Thereafter, using the first sidewall spacer of the first field effect transistor as a mask, a second conductivity type impurity is implanted into the semiconductor substrate to form a high concentration impurity layer. Next, an oxide insulating film is deposited on at least the gate electrode of the second field effect transistor and the first sidewall spacer, and is anisotropically etched to form a second sidewall spacer. Furthermore, using the second sidewall spacer of at least the second field effect transistor as a mask, a second conductivity type impurity is implanted into the semiconductor substrate to form a high concentration impurity region.

The method of manufacturing a semiconductor device of the present invention also includes the following steps.

First, a gate electrode is formed on the main surface of a semiconductor substrate having a first conductivity type region at least near the main surface, with a gate insulating film interposed therebetween. Next, an oxide insulating film is deposited on both left and right sidewall surfaces of this gate electrode, and anisotropic etching is performed on this to form sidewall spacers. Before or after this step of forming sidewall spacers, impurities of the second conductivity type are implanted into the semiconductor substrate using only the gate electrode or the gate electrode and either sidewall spacer as a mask to form source/drain regions. . Furthermore, by repeating the step of forming the sidewall spacer and the step of forming the source/drain region at least once, and covering a specific sidewall of the gate electrode determined each time with a mask, each sidewall is A sidewall spacer made of an insulating film having a predetermined width and a predetermined number of layers is formed on.

In another aspect of the method for manufacturing a semiconductor device of the present invention, a gate insulating film is interposed on each surface of a plurality of active regions of a semiconductor substrate in which p-type and n-type wells are formed. A step of forming a plurality of gate electrodes, a step of forming a sidewall spacer by depositing an insulating film on each sidewall of the plurality of gate electrodes and performing anisotropic etching, and a step of forming a sidewall spacer by depositing an insulating film on each sidewall of the plurality of gate electrodes, and forming a sidewall spacer by depositing an insulating film on each sidewall of the plurality of gate electrodes. Using both the sidewall spacer and the sidewall spacer as masks, n-type impurity ions are added to the p-type well region.
The method includes a step of implanting p-type impurity ions into the type well region to form source/drain regions. A feature of this manufacturing method is that the step of forming the sidewall spacer is performed by depositing an oxide insulating film multiple times and performing anisotropic etching, and the step of depositing the oxide insulating film multiple times includes at least In one or more of these steps, by covering the gate electrode in the p-type well region with a resist, the width of the sidewall spacer formed in the p-type well region is the same as that of the sidewall spacer formed in the n-type well region. It is characterized by being smaller than the width of the spacer.

[0022]

[Function] According to the semiconductor device of the present invention, a sidewall spacer is formed of a predetermined number of layers of oxide insulating film for each sidewall of the gate electrode, so that the source/drain region is formed according to the channel conductivity type or desired MOS type L, which has a concentration distribution according to its characteristics and has an appropriately controlled impurity concentration distribution in the source/drain region.
A field effect transistor with a DD structure can be obtained.

Furthermore, according to the method of manufacturing a semiconductor device of the present invention, instead of forming sidewall spacers of different widths separately, the deposition of the oxide insulating film and the anisotropic etching are sequentially repeated multiple times to form sidewall spacers of different widths. Since this is done by covering the position where the width should be made smaller with resist as necessary, the efficiency of forming sidewall spacers is improved compared to the case where sidewall spacers having different widths are formed separately. This is because in the present invention, although it is necessary to pattern the resist film a number of times according to the number of widths of the sidewall spacers, the CVD method requires a longer processing time than the resist film forming process. This is because, in the oxide insulating film deposition step, the oxide insulating film is deposited on the sidewall spacers of each width simultaneously and is completed sequentially.

Furthermore, in another method of manufacturing a semiconductor device of the present invention, the above manufacturing method of the present invention is applied to a p-channel MOS transistor formed in an n-type well region and a p-type well region on the same semiconductor substrate. n-channel M formed in
It is applied when forming an OS type transistor. In this manufacturing method, the sidewall spacer of the p-channel MOS transistor is formed to have a larger width than that of the n-channel MOS transistor. As a result, the amount of offset of a p-channel MOS transistor becomes larger than that of an n-channel MOS transistor, so the appropriate You can get the sidewall width.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS. 1 to 10. In this embodiment, n channel M
A complementary MOS type integrated circuit is manufactured that employs an LDD structure for both the OSFET and the p-channel MOSFET.

In this embodiment, first, in order to isolate the semiconductor substrate 11 into a plurality of active regions, so-called LOCO
The element isolation insulating film 12 is formed by the S method. Thereafter, p-type impurity ions such as boron or n-type impurity ions such as phosphorus or arsenic are implanted into each separated region, thereby forming both the p-well region 13 and the n-well region 14. Thereafter, by interposing gate insulating films 15 and 16 in each active region and depositing impurity-doped polycrystalline silicon, or by processing a conductive material such as a high melting point metal by a known method, Gate electrode 17
, 18 (Fig. 1).

Next, the entire surface of the active region in which the n-type well has been formed is covered with a resist film 20, and n-type impurity ions such as phosphorus or arsenic are applied at 10 12 /cm 2 to 10 14 /cm 2 only in the region where the n-channel MOSFET is to be formed. By implanting at an irradiation density of , low concentration n-type diffusion layers 19 are formed on both sides of the gate electrode 17 in a self-aligned manner using the gate electrode 17 as a mask (FIG. 2).

Next, after removing the resist film 20, the entire surface of the active region where the p-type well is formed is covered with a resist film 31, and p-type impurity ions such as boron are injected at 10 12 / cm2 ~101
By implanting at an irradiation density of 4/cm2, a low concentration p-type diffusion layer 26 is formed in a self-aligned manner using the gate electrode 18 as a mask (FIG. 3).

Next, after removing the resist film 31, an oxide film 32 is deposited on the entire surface of the semiconductor substrate 11 by CVD or the like (FIG. 4), and this is subjected to reactive ion etching to form the sidewall spacers 21. , 22 (Fig. 5). The width of the sidewall spacer 21 on the surface of the semiconductor substrate 11 is approximately proportional to the thickness of the oxide film 32.

Next, the entire surface of only the n-type well region 14 is covered with a resist film 33, and in this state, the n-channel MOS
By implanting n-type impurity ions such as phosphorus or arsenic into the active region of the FET at a radiation density of 1015/cm2 to 1017/cm2, the highly concentrated n-type diffusion layer 24 forms a gate electrode 17 and a sidewall spacer 21. Formed as a mask in a self-aligned manner on both sides (Figure 6)
.

Next, an oxide film 34 is deposited on the entire surface of the semiconductor substrate 11 by the CVD method, and the entire surface only on the p-well region 13 is covered with a resist film 35 (FIG. 7). By applying ion etching,
A second layer of sidewall spacers 28 is formed on the n-well region 14 (FIG. 8). In this state, the p-channel MO
By implanting p-type impurity ions such as boron into the active region of the SFET at an irradiation density of 1015/cm2 to 1017/cm2, the highly concentrated p-type diffusion layer 30 forms the gate electrode 18 and the sidewall spacers 22, 28. Formed as a mask in a self-aligned manner on both sides (Figure 9)
.

After removing the resist film 35, heat treatment is performed under predetermined conditions to form the low concentration n-type diffusion layer 19, the high concentration n-type diffusion layer 24, the low concentration p-type diffusion layer 26, and the high concentration p-type diffusion layer. 30 becomes activated (FIG. 10).

Next, a second embodiment of the present invention will be described with reference to FIGS. 11 to 18. The steps shown in FIGS. 11 and 12 in this embodiment are similar to the steps shown in FIGS. 1 and 2 in the first embodiment. Figure 12
After removing the resist film 20 from the state shown in FIG. side wall spacer 21
, 22 are formed. After that, a resist film 23 is formed on the entire surface of the active region where the n-type well has been formed, and an n-channel MOS is formed.
By again implanting n-type impurities into the region where the FET is to be formed, the gate electrode 17 and sidewall spacer 21 are
Using as a mask, a high concentration n-type diffusion layer 24 is formed in a self-aligned manner (FIG. 13).

Next, after removing the resist film 23, a resist film 25 is formed over the entire active region of the n-channel MOSFET on the p-type well region 13, and in this state, a material such as boron is applied to the active region of the p-channel MOSFET. P-type impurity ions are implanted to form a low concentration p-type diffusion layer 26 in a self-aligned manner using the gate electrode 18 and sidewall spacer 22 as a mask (FIG. 14).

After removing the resist film 25, CVD is performed again.
An insulating film such as a silicon oxide film is formed on the entire surface with a constant thickness by a method, and then anisotropic etching is performed on the entire surface to form sidewall spacers 27 and 28 on the side walls of the gate electrodes 17 and 18 (see FIG. 15).

Next, the entire active region of the n-channel MOSFET is covered with a resist film 29, and in this state, the p-channel MOSFET is
P-type impurity ions such as boron are implanted into the OSFET region to form the gate insulating film 18 and the sidewall spacers 2.
Using 7 and 28 as masks, a heavily doped p-type diffusion layer 30 is formed in a self-aligned manner (FIG. 16).

After removing the resist film 29 (FIG. 17),
By performing heat treatment under predetermined conditions, a low concentration n-type diffusion layer 19, a high concentration n-type diffusion layer 24, a low concentration p-type diffusion layer 26,
The high concentration p-type diffusion layer 30 is in an activated state (Fig. 1
8).

[0038] By going through each of the above steps, the first
, according to the second embodiment, both n-channel and p-channel MOSFETs are mounted on the same semiconductor substrate 11.
A complementary MOSFET with a D structure will be formed.

According to each of the above embodiments, as described above, the sidewall spacers of both the p-channel MOSFET and the n-channel MOSFET are formed by separate CVD processes.
and anisotropic etching steps, but rather at the same time. Moreover, by including an impurity ion implantation step between the steps of forming each of the plurality of layers of sidewall spacers, it is possible to adjust the offset length of the source/drain region depending on the conductivity type of the channel. Therefore, for self-aligned formation of optimal source/drain regions according to the conductivity type of the channel, while maintaining the same possibility as when forming sidewall spacers separately, compared to resist film patterning, The CVD oxide insulating film deposition process, which requires significantly longer processing times, can be utilized efficiently, resulting in improved productivity.

Next, a third embodiment of the present invention will be explained based on FIGS. 19 to 24. In this embodiment, a p-well region 13 and an n-well region 14 are formed in each active region of a semiconductor substrate 11 separated by an element isolation insulating film 12, and gate electrodes 17, 1 are formed with gate insulating films 15, 16 interposed.
The step of forming 8 (FIG. 19) is the same as in the first embodiment. In this embodiment, the gate electrodes 17, 18
After forming, first layer sidewall spacers 21 and 22 are formed by depositing an oxide insulating film by CVD and anisotropic etching. After that, p-channel MOSF
The region where the ET is to be formed is covered with a resist film 20, and n-type impurity ions such as phosphorus or arsenic are implanted to form a low concentration n-type diffusion layer 19 (FIG. 20). After that, after forming the second layer of sidewall spacers 27 and 28, p
The channel MOSFET formation region is covered with a resist film 23, and n-type impurity ions are implanted to form a high concentration n-type diffusion layer 24 (FIG. 21).

Next, after forming a resist film 23, a region where an n-channel MOSFET is to be formed is covered with a resist film 25, and p-type impurity ions such as boron are implanted to form a low concentration p-type diffusion layer 26. (Figure 22). Resist film 25
After removing the third layer sidewall spacer 41,
42 is formed, the region where the n-channel MOSFET is to be formed is covered with a resist film 29, and p-type impurity ions are further implanted to form a highly concentrated p-type diffusion layer 30 (FIG. 2).
3). Thereafter, the resist film 29 is removed and heat treatment is applied under predetermined conditions to activate each diffusion layer.
The state shown in FIG. 24 is reached.

In this example, as described above, the multilayer sidewall spacer is formed by sequentially repeating the deposition of an oxide insulating film by CVD and the anisotropic etching several times.
This embodiment is similar to the first and second embodiments in that a resist film is selectively formed and impurity ions are implanted during this period. This embodiment differs from the first embodiment in that there is no step of implanting impurity ions using only the gate electrodes 17 and 18 as a mask, and that sidewall spacers are formed in three layers. In this embodiment as well, the same effects as in the first embodiment can be obtained in terms of improving the efficiency of the sidewall spacer forming process. Further, in the case of a relatively low current fine transistor having a channel width of 1 micron or less, the diffusion length of impurities in the source/drain region is relatively large with respect to the channel width. Therefore, offset by sidewall spacers is essential. Furthermore, considering that the diffusion coefficient of p-type impurities is larger than that of n-type impurities, the width of the sidewall spacer, which serves as a mask when implanting p-type impurity ions, is different from the width of the sidewall spacer that serves as a mask when implanting n-type impurity ions. The width of the sidewall spacer must be greater than the width of the sidewall spacer. This example satisfies this requirement by increasing the number of sidewall spacer layers when implanting p-type impurity ions than the number of sidewall spacer layers when implanting n-type impurity ions. It turns out.

For reference, an example specifically showing the degree of difference in diffusion coefficients between p-type impurities and n-type impurities will be explained with reference to FIGS. 33 and 34. On the p-well side where the n-channel MOSFET is formed, a width of 10 mm on the surface of the semiconductor substrate 11 is provided.
Phosphorus is implanted using the sidewall spacers 21 with a width of 0.00 angstroms as a mask to form a low concentration n-type diffusion layer 19. Furthermore, sidewall spacers with a width of 2000 angstroms are added as a mask to form a high concentration n-type diffusion layer 24. Form. Boron is implanted into the n-well side where the p-channel MOSFET is formed using sidewall spacers 22 and 28 having a total width of 3000 angstroms as a mask to form a heavily doped p-type diffusion layer 30, and as shown in FIG.
It will be in state 3. Thereafter, when heat treatment is performed at a temperature of 900° C. to 950° C. for about 1 hour, each diffusion layer is activated and the concentration distribution shifts due to thermal diffusion, resulting in the state shown in FIG. 34. That is, when the same heat treatment is applied, n
It can be seen that the thermal diffusion of boron is significantly larger than that of phosphorus and arsenic.

Note that in the third embodiment, the formation of the low concentration p-type diffusion layer 26 in the p-channel MOSFET formation region was performed in the n-channel MOSFET formation region before forming the second layer sidewalls 27 and 28. It is also possible to form a resist film on the surface and use the sidewall spacers 22 as a mask.

Furthermore, in the second embodiment, when only the low concentration n-type diffusion layer 19 is formed in the first layer sidewall spacer 21, 22 formation region, and the low concentration p-type diffusion layer 26 is not formed, , only a heavily doped p-type diffusion layer 30 is formed in the source/drain region of the p-channel MOSFET formation region. In this way, n-channel MOSF
Only the ET formation region can have an LDD structure.

Next, a fourth embodiment of the present invention will be explained based on FIGS. 25 to 32. In this embodiment, first, a gate oxide film 53 is interposed on the surface of a p-type semiconductor substrate 52 separated by an element isolation insulating film 51.
A polycrystalline silicon layer 54 is deposited, and an oxide insulating film 5 is further deposited.
25, the gate insulating film 53 and polycrystalline silicon layer 54 are removed by photo-etching, except for the gate electrode portion 56, resulting in the structure shown in FIG. Subsequently, n-type impurity ions such as phosphorus or arsenic are implanted, and low concentration n-type diffusion layers 57 are formed on both left and right sides of the gate electrode section 56 using it as a mask (FIG. 26). Next, an oxide insulating film such as silicon oxide is deposited on the entire surface of the semiconductor substrate 52 by CVD, and then anisotropic etching is performed to form sidewall spacers 58 (FIG. 27). Thereafter, the right half of the semiconductor substrate 52 from the center of the gate electrode portion 56 is covered with a resist film 59, and n-type impurity ions are implanted to form a heavily doped n-type region 60 in the source region using the sidewall spacer 58 as a mask. (Figure 28).

Next, after removing the resist film 59, an oxide insulating film 61 made of silicon oxide or the like is formed over the entire surface of the p-type semiconductor substrate 52 by CVD (FIG. 29). after that,
A resist film 62 is selectively formed except for the region from the center of the gate electrode section 56 to the drain region (FIG. 30),
By performing anisotropic etching in this state, sidewall spacers 63 and contact holes 64 are formed. Subsequently, by implanting n-type impurity ions using the sidewall spacers 63 as a mask, a high concentration n-type diffusion layer 65 is formed on the drain region side in a self-aligned manner (FIG. 31).

Next, a wiring layer 66 in which a metal layer or a doped polycrystalline silicon layer is selectively formed is formed so as to conduct the high concentration n-type diffusion layer 65 in the contact hole 64.
(Figure 32).

According to this embodiment, as described above, the sidewall spacers 58 and 63 are formed so that the offset on the drain side where the wiring layer 66 is formed is long, and the contact hole 64 is formed at the same time. , it is possible to effectively improve drain breakdown voltage. Furthermore, due to the diffusion of impurities from the wiring layer 66, the low concentration n-type diffusion layer 5
7 can be suppressed.

In this embodiment, the high concentration n-type diffusion layer 65 was formed by performing ion implantation after the etching process for forming the sidewall spacer 63, but instead, the wiring layer It is also possible to form using diffusion from impurities doped into the polysilicon layer formed as 66.

[0051] The above embodiments are all based on LOCOS.
Although a semiconductor device to which the present invention is applied in which an element isolation region is formed by a method has been described, similar effects can be obtained even if the present invention is applied to a semiconductor device in which an element isolation region is formed by a field shield electrode. Needless to say, it can be done.

Furthermore, in each of the above embodiments, when the sidewall spacer is formed from multiple layers, it is difficult to identify the boundaries between the layers even when observing the cross section of the completed sidewall spacer. This is difficult as long as the material is formed by CVD. This is because the CVD film is in a non-crystalline (amorphous) state. However, as shown in FIG.
Steps (A and B in FIG. 35) are generated due to over-etching of the surface of the semiconductor substrate 11 when forming each of the semiconductor substrates 1 and 27. Therefore, by observing the cross section of a completed semiconductor device with an electron microscope and determining whether or not there is a step, it is possible to determine whether the sidewall spacer is composed of a plurality of layers.

Further, the first to third embodiments described above are particularly effective for forming a circuit element of a CMOS structure such as a CMOS inverter having wiring connections as shown in FIG.

[0054]

As described above, according to the field effect transistor of the present invention, by having a sidewall spacer of a predetermined width on which a predetermined number of layers of insulating films are deposited on each sidewall of the gate electrode, The source/drain regions are appropriately controlled, and a field effect transistor having a MOS type LDD structure with good characteristics can be obtained.

Further, according to the method for manufacturing a field effect transistor of the present invention, a plurality of layers of sidewall spacers are formed in a plurality of steps, and a resist film is selectively formed in each step. A sidewall spacer of a predetermined width is formed. As a result, it is possible to easily control the offset length of the impurity diffusion layer in the source/drain region formed using the sidewall spacer as a mask, and compared to the case where sidewall spacers with different widths are formed in separate processes. Therefore, the total time required for depositing the oxide insulating film is shortened.
Productivity improves.

[0056] This manufacturing method can also be applied to complementary MOSFETs.
According to the invention applied to the manufacturing process of a field effect transistor having both p-type and n-type channel regions as in
In a fine MOSFET having a channel length of 1 μm or less, the offset amount of a p-channel MOSFET can be easily controlled to be larger than that of an n-channel MOSFET. This makes it possible to provide a high-performance complementary MOSFET or the like at a relatively low cost, taking into consideration that the diffusion coefficient of p-type impurity ions is larger than that of n-type impurity ions.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a first step of a method for manufacturing a field effect transistor according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing the second step.

FIG. 3 is a sectional view showing the third step.

FIG. 4 is a sectional view showing the fourth step.

FIG. 5 is a sectional view showing the fifth step.

FIG. 6 is a sectional view showing the sixth step.

FIG. 7 is a sectional view showing the seventh step.

FIG. 8 is a sectional view showing the eighth step.

FIG. 9 is a cross-sectional view showing the ninth step.

FIG. 10 is a cross-sectional view showing the tenth step.

FIG. 11 is a sectional view showing a first step of a method for manufacturing a field effect transistor according to a second embodiment of the present invention.

FIG. 12 is a sectional view showing the second step.

FIG. 13 is a sectional view showing the third step.

FIG. 14 is a sectional view showing the fourth step.

FIG. 15 is a sectional view showing the fifth step.

FIG. 16 is a sectional view showing the sixth step.

FIG. 17 is a sectional view showing the seventh step.

FIG. 18 is a sectional view showing the eighth step.

FIG. 19 is a cross-sectional view showing a first step of a method for manufacturing a field effect transistor according to a third embodiment of the present invention.

FIG. 20 is a sectional view showing the second step.

FIG. 21 is a sectional view showing the third step.

FIG. 22 is a sectional view showing the fourth step.

FIG. 23 is a sectional view showing the fifth step.

FIG. 24 is a sectional view showing the sixth step.

FIG. 25 is a cross-sectional view showing a first step of a method for manufacturing a field effect transistor according to a fourth embodiment of the present invention.

FIG. 26 is a sectional view showing the second step.

FIG. 27 is a sectional view showing the third step.

FIG. 28 is a sectional view showing the fourth step.

FIG. 29 is a sectional view showing the fifth step.

FIG. 30 is a sectional view showing the sixth step.

FIG. 31 is a sectional view showing the seventh step.

FIG. 32 is a sectional view showing the eighth step.

FIG. 33 shows an n-type diffusion layer and a p-type diffusion layer in the source/drain region when an n-channel MOS transistor and a p-channel MOS transistor are formed on the same semiconductor substrate.
FIG. 3 is a cross-sectional view showing a profile of a mold diffusion layer before heat treatment due to a difference in diffusion coefficient.

34 is a cross-sectional view showing an impurity profile after a predetermined heat treatment is applied to the state shown in FIG. 33. FIG.

FIG. 35: A sidewall spacer consisting of multiple layers.
FIG. 3 is a cross-sectional view for explaining a step difference that occurs on the surface of a semiconductor substrate depending on the number of layers.

FIG. 36 is a diagram schematically showing the cross-sectional structure and wiring of a CMOS inverter to which the present invention is applied.

FIG. 37 is a cross-sectional view showing the first step in a conventional method for manufacturing a MOS type LDD structure transistor.

FIG. 38 is a sectional view showing the second step.

FIG. 39 is a sectional view showing the third step.

FIG. 40 is a sectional view showing the fourth step.

FIG. 41 is a cross-sectional view showing the fifth step.

FIG. 42 is a cross-sectional view showing the sixth step.

FIG. 43 is a cross-sectional view showing the first step in a conventional manufacturing method when sidewall spacers for an n-channel MOS transistor and a p-channel MOS transistor are formed separately on the same semiconductor substrate.

FIG. 44 is a sectional view showing the second step.

FIG. 45 is a sectional view showing the third step.

FIG. 46 is a sectional view showing the fourth step.

FIG. 47 is a sectional view showing the fifth step.

FIG. 48 is a sectional view showing the sixth step.

FIG. 49 is a sectional view showing the seventh step.

FIG. 50 is a sectional view showing the eighth step.

[Explanation of symbols]

11 Semiconductor substrate 12 Element isolation insulating film 13 P-well region 14 N-well region 15, 16 Gate insulating film 17, 18 Gate electrode 19 Low concentration n-type diffusion layer 20, 23, 25, 29, 33, 35 Resist film 2
1, 22, 27, 28, 41, 42 Sidewall spacer 24 Highly doped n-type diffused layer 26 Lowly doped p-type diffused layer 30 Highly doped p-type diffused layer Note that parts with the same reference numerals in the drawings are the same or equivalent. Indicates the element of

Claims (5)

[Claims] 1. A semiconductor device comprising a semiconductor substrate having first and second field effect transistors, each of the field effect transistors being formed on the semiconductor substrate with a gate insulating film interposed therebetween. a gate electrode; a first sidewall spacer made of a single layer of insulating film formed on the left and right side wall surfaces of the gate electrode; at least the second field effect transistor includes a source/drain region having a high concentration and/or a low concentration impurity region formed over at least one sidewall surface of the gate electrode; The second sidewall spacer of the second field effect transistor includes a second sidewall spacer made of a single layer of insulating film, and the second sidewall spacer of the second field effect transistor includes an impurity that forms a high concentration impurity region on at least one sidewall side of the gate electrode. A semiconductor device that forms a mask for implantation. 2. A semiconductor device having a field effect transistor, wherein the field effect transistor includes a semiconductor substrate having a first conductivity type region at least near the surface;
a gate electrode formed on the semiconductor substrate with a gate insulating film interposed therebetween; and a first gate electrode formed on one side wall surface of the gate electrode, comprising a predetermined number of layers of insulating films and having a predetermined width. A sidewall spacer and an insulating film formed on the other sidewall surface of the gate electrode and having a predetermined number of layers larger than the first sidewall spacer, and a predetermined number of layers larger than the first sidewall spacer. a second sidewall spacer having a width of
A semiconductor device comprising: a second conductivity type source/drain region formed on the surface of the semiconductor substrate from the vicinity immediately below the right and left side walls of the gate electrode to the outside. 3. A method for manufacturing a semiconductor device comprising first and second field effect transistors having an LDD structure formed on a main surface of a semiconductor substrate of a first conductivity type, the method comprising: A step of forming a gate electrode for each field effect transistor by interposing a gate insulating film on the main surface, depositing an oxide insulating film on both left and right side walls of the gate electrode, and subjecting it to anisotropic etching. a step of forming a first sidewall spacer, and implanting a second conductivity type impurity into the semiconductor substrate using the first sidewall spacer of the first field effect transistor as a mask, and implanting a high concentration impurity. depositing an oxide insulating film on at least the gate electrode of the second field effect transistor and the first sidewall spacer, and anisotropically etching the oxide insulating film to form a second field effect transistor.
forming a sidewall spacer, and using at least the second sidewall spacer of the second field effect transistor as a mask, impurities of a second conductivity type are implanted into the semiconductor substrate to form a high concentration impurity region. A method for manufacturing a semiconductor device, comprising a step of: 4. A method for manufacturing a semiconductor device including a field effect transistor, comprising: forming a gate electrode on the main surface of a semiconductor substrate having a first conductivity type region at least near the main surface with a gate insulating film interposed therebetween; a step of depositing an oxide insulating film on both left and right sidewall surfaces of the gate electrode, and performing anisotropic etching on this to form a sidewall spacer; using a wall spacer as a mask, implanting a second conductivity type impurity into the semiconductor substrate to form a source/drain region; By repeating the forming step at least once and covering a specific sidewall of the gate electrode with a mask each time, a sidewall spacer made of an insulating film of a predetermined width and a predetermined source is formed for each sidewall. A method for manufacturing a semiconductor device. 5. Forming a plurality of gate electrodes on each surface of a plurality of active regions of a semiconductor substrate in which p-type and n-type wells are formed, with a gate insulating film interposed therebetween; A step of forming a sidewall spacer by depositing an insulating film on each sidewall of the p-type film and performing anisotropic etching on each sidewall of the p-type A semiconductor including a MOS type field effect transistor, comprising a step of implanting n-type impurity ions into a well region and p-type impurity ions into an n-type well region to form a source/drain region. In the method for manufacturing a device, the step of forming the sidewall spacer is performed by depositing an oxide insulating film multiple times and performing anisotropic etching, and the step of depositing the oxide insulating film multiple times includes: , by covering the gate electrode in the p-type well region with resist at least once, so that the width of the sidewall spacer formed in the p-type well region is equal to the width of the sidewall spacer formed in the n-type well region. A method of manufacturing a semiconductor device, characterized in that the width of the semiconductor device is smaller than the width of a spacer.