JPH04219006A - Limiter/compressor - Google Patents

Abstract

PURPOSE:To eliminate defect due to saturation and to avoid unnatural reproduction sound even with an excess input by providing a word length expansion means, a level intensifying means and a word length reduction means to the limiter/compressor. CONSTITUTION:The limiter/compressor is provided with a word length expansion means 202 expanding a word length 16-bit of an input digital audio signal into 40-bit, a level intensifying means 203 intensifying a level of an output signal and a limiter/compressor means 204, and further a word length reduction means 205 reducing the length of word so that its most significant bit is equal to a mode significant bit of the input digital signal. Then the word length expansion means 202 has a sufficient head margin not saturated at a level able to be intensified by the level intensifying means 203. Thus, a positive threshold generated by a level intensifying means 203 is optionally set with unsaturation thereby eliminating defect of saturation.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a limiter/compressor device that eliminates saturation defects when a digital audio signal such as a PCM audio signal is subjected to limiter processing or compressor processing.

(Prior technology) Conventionally, audio signals were recorded and played back analogously, but in recent years compact discs, 8mm VTRs, and R-D
Devices such as AT have become widespread, and since these devices record and reproduce audio signals digitally, it has become possible to enjoy higher quality sound.

By the way, it is known that when limiter processing or compressing an analog audio signal waveform, a desired limiter/compress characteristic curve can be achieved without causing saturation defects by using a power supply voltage higher than the input level. .

Now, a signal level processing device for processing digital audio signals will be described.

7 to 9 are first to third functional block diagrams of a signal level processing device, FIGS. 10 and 13 are block diagrams of an audio signal processing device to which the signal level processing device is applied, and FIG. 11 ( a) and (b) are flowcharts showing the operation of the CPU 17, which is a main part of the signal level processing device shown in FIG. 10, and FIG. 12 is an input/output characteristic diagram of the signal level processing device shown in FIGS. 7 to 9. It is.

The signal level processing device described here calculates a function related to the difference between the reference level within the device and the input level of the digital audio signal supplied to the device when limiter processing or compressing a digital audio signal. A system configured to obtain a high-quality digital audio signal by dividing the calculation result by the input level to obtain a gain coefficient, and using this to perform each of the above processes to select desired input/output characteristics. It is.

FIG. 10 is a block diagram of an audio signal processing device applying a signal level processing device to be described later. As shown in the figure, a digital signal supplied from an input terminal 11 is demodulated into, for example, an NRZ signal in a receiving section 12. Ru. In the case of the so-called self-clock system, the receiving section 12 extracts a clock component from the received data and supplies it to the PLL circuit 13.

The PLL circuit 13 generates continuous clock pulses in synchronization with this clock and supplies them to the receiving section 12. Receiving section 12
performs demodulation in synchronization with this clock pulse, and sends the demodulated data to a digital signal processor (DSP) 1.
It is supplied to each input terminal a1 of 4L1 and 14R1 (in this case, each input terminal a2 is not used).

The DSP 14L1 performs equalizer processing on the left channel audio signal of the left and right stereo signals, and the DSP 14R1 performs equalizer processing on the right channel audio signal, for example, by performing an FIR digital filter operation, and then outputs them from output terminals b and c.

The data output from each output terminal of DSP14L1 and DSP14R1 is supplied to each input terminal a1 of DSP14L2 and DSP14R2.
The data output from each output terminal c of R1 is
It is supplied to each input terminal a2 of 4L2 and DSP14R2.

The DSP 14L2 and the DSP 14R2 output signals obtained by performing limiter processing or compressor processing on the left and right channel audio signals from output terminals c. These DS
The data output from P14L2 and DSP14R2 is supplied to the transmitter 20, and after being modulated again into a predetermined format suitable for transmission (e.g. bi-phase modulation), the data is sent from the output terminal 21 to a circuit (e.g. digital amplifier) not shown.
is output serially.

The above-mentioned receiving section 12 includes DSP14L1 and DSP14L2.
, DSP14R1, DSP14R2 (hereinafter referred to as DSP14L)
1 to DSP14R2) supply a system clock XCLK, a synchronization signal SYNC, etc. to the transmitter 20, respectively.

The operation section 15 has a plurality of push button switches (not shown), which are operated to obtain desired equalizer characteristics, limiter characteristics, or compressor characteristics. The CPU 17 causes a display corresponding to this operation to be displayed on the display unit 16 consisting of a CRT, a lamp, an LED, etc., and also reads a predetermined program from the ROM 18 and sends various control signals to the DSP 14L1 to DSP 14R2 in order to realize the specified characteristics. output and control them. At this time, RAM19
The data necessary for this is stored and read out.

FIG. 11(a) shows the main routine of the operation of the CPU 17. As shown in the figure, when started, the CPU 17 is initialized (step 101), and then the DSP 14L
1 to DSP14R2 are initialized (step 10
2). Next, the operating states of the plurality of pushbutton switches in the operating section 15 are determined (step 103), and when they are off, the state of waiting for a certain period of time is repeated (step 104).

When the push button switch is on, the value set by the push button switch is read (step 105). Next, among the parameters (used for signal processing) stored in advance in the ROM 18, those corresponding to the operation of the push button switch are selected;
These are sequentially written into parameter memories (not shown) built in the DSPs 14L1 to 14R2 together with the address information (steps 106 to 108).

Subsequently, the CPU 17 generates a switching signal AD (step 1).
09), and further sends data to the display unit 16 (step 110).

FIG. 11(b) shows an interrupt routine for the operation of the CPU 17. When an interrupt occurs, the CPU 17 generates a pulse CSd (step 201) and returns to the above-mentioned main routine. This pulse CSd is sent from the CPU 17 to the receiving section 12 at predetermined time intervals.

Now, the functional block diagrams shown in FIGS. 7 to 9 respectively embody the functions of the limiter processing or compress processing executed in the above-described DSP 14L2 or DSP 14R2. In the following description, this function will be replaced with a circuit or the like.

As shown in FIG. 7, the first functional block of the signal level processing device includes an absolute value circuit 32 and a comparator (COMP).
33, arithmetic circuit 34, difference arithmetic circuit 35, multiplication circuit 36,
It is composed of a delay circuit (DELAY) 37. 31
is an input terminal, and 38 is an output terminal.

The absolute value circuit 32 detects and outputs the absolute value Lin of the level of the input signal (digital data) Xin supplied from the input terminal 31. The comparator 33 described above compares the absolute value Lin supplied from the absolute value circuit 32 with a predetermined threshold level (reference level) Lth=L1.

When the absolute value Lin is smaller than this reference level L1,
The movable contact of switch 41, which will be described later, is located at the lower side of the figure (coefficient 0).
A control signal is output to the switch 41 to switch to the fixed contact of the coefficient circuit 42 (which outputs the coefficient circuit 42). As a result, the output of the arithmetic circuit 34 described above becomes zero, so the delay circuit 34
The input signal Xin supplied to the multiplier circuit 36 via the multiplier 7 is multiplied by a coefficient 1 in a multiplier 49, which will be described later, in the multiplier circuit 36, and then amplified by an amplifier 50 with a gain g and output.

As a result, the input/output characteristics of the signal level processing device become the region β (linear region) in FIG. 12, and no limiter processing or compressing processing is performed.

Further, when the absolute value Lin is larger than the reference level L1, the movable contact of the switch 41 is moved to the upper side in the figure (the subtraction circuit 4
A control signal indicating switching to the fixed contact (output side of 0) is output to the switch 41. As a result, the output of the arithmetic circuit 34 described above becomes the arithmetic result (1/Lin)·(k1
Δ2), the resulting input/output characteristic becomes the region α (nonlinear region) in FIG. 12, and as is clear from this characteristic diagram, the input signal Xin is compressed or limited.

The arithmetic circuit 34 described above is a reference level generation circuit (REF).
39, subtraction circuit 40, switch 41, coefficient circuit 42, 4
3, multipliers 44 and 45, and a divider (DIV) 46.

When the absolute value Lin of the level of the input signal Xin is greater than the reference level L1, the absolute value L of the input signal
The calculation result (1/Li
n)・(k1Δ2) is output.

Specifically, the reference level generation circuit 39 supplies the reference level L1 to the subtraction circuit 40, and the subtraction circuit 40 supplies the absolute value L1.
Difference value between in and reference level L1 (Lin-L1=Δ)
is supplied to the multiplier 44 via the switch 41, and the multiplier 4
4 squares this value Δ, supplies the multiplication output Δ2 to the multiplier 45, and here obtains the multiplication output (k1Δ2) in which the output Δ2 is multiplied by the coefficient k1 supplied from the coefficient circuit 43.

This multiplication output (k1Δ2) is supplied to the divider 46, where the multiplication output (k1Δ2) is divided by the absolute value Lin of the input signal Xin described above to obtain the division output (1/Lin・(
k1Δ2)) can be obtained.

This value becomes the calculation result of the calculation circuit 34 described above.

The above-mentioned difference calculation circuit 35 is a coefficient circuit 4 that outputs a coefficient 1.
7 and a subtraction circuit 48 to which the calculation result of the calculation circuit 34 described above is supplied.
The difference calculation output (1-(1
/Lin)·(k1Δ2)) is output to the multiplication circuit 36 described above.

The multiplication circuit 36 described above is composed of a multiplier (MPY) 49 and an amplifier (AMP) 50, and the multiplier 49 outputs the difference from the difference calculation circuit 35 to the input signal Computation output (1-(1/
Multiply by Lin)・(k1Δ2)).

At this time, assuming that the delay time is zero, Xin
When ≧0, since Lin=Xin, the multiplication output of Xin·(1−(1/Lin)·(k1Δ2)) is obtained, and when Xin<0, the multiplication output of is obtained.

If the delay time is not zero, the above equations (1) and (2) do not hold, so it is possible to change the gain of the delay signal (input signal of the multiplier 49) according to the level of the absolute value Lin of the input signal Xin. Therefore, even if the input signal Xin with rapid level fluctuations passes through the delay circuit 37, the above equation (1) can be satisfied.
, (2) can be compressed or limited while performing subtraction and addition equivalently.

In this way, the input/output characteristic Q1 shown in FIG. 12 is obtained, and this multiplication output is further supplied to the amplifier 50, where it is amplified with a gain g, so that the input/output characteristic Q1 shown in FIG.
2 is output from output terminal 38.

Further, the second functional block of the signal level processing device is the eighth functional block.
As shown in the figure, an absolute value circuit 32, a comparator (CO
MP) 33, an arithmetic circuit 51, a difference arithmetic circuit 52, a delay circuit (DELAY) 53, and an amplifier circuit 54. Components that are the same as those described above are given the same reference numerals, and their explanations will be omitted.

When the absolute value Lin, which is the output of the absolute value circuit 32, is smaller than the reference level L1, the comparator 33 changes the movable contact of the switch 56, which will be described later, to the fixed contact on the left side in the figure (the side of the coefficient circuit 55 that outputs coefficient 0). A control signal indicating switching is output to the switch 56. As a result, the output of the arithmetic circuit 51 described above becomes zero, and the input signal Xin delayed for a predetermined sampling time via the delay circuit 53 is sent to the amplifier circuit 51
4, the signal is amplified by the gain g from the difference calculation circuit 52 and then output. The input/output characteristics obtained thereby are in the region β (linear region) in FIG. 12, and no limiter processing or compressing processing is performed.

Further, when the absolute value Lin is larger than the reference level L1, the comparator 33 sends a control signal to the switch 56 to switch the movable contact of the switch 56 to the fixed contact on the right side in the figure (the side of the coefficient circuit 43 that outputs the coefficient k1). Output(
In this case, the output of the above-mentioned arithmetic circuit 51 will be the value described later, so the input/output characteristics obtained will be in the area α (nonlinear area) shown in FIG. 12, and the input signal Xin will be compressed or limited.

The arithmetic circuit 51 described above is a reference level generation circuit (REF).
39, subtraction circuit 40, coefficient circuits 43, 55, multiplier 44
, 45, 57, a divider (DIV) 46, and a switch 56. Then, when the absolute value Lin is larger than the reference level L1, a function related to the difference between the level of the input signal Xin and the reference level L1 is calculated (Lin-L1=
Δ, k1Δ2), and the signal obtained by dividing this calculation result by the level of the input signal Xin and multiplying this value by the coefficient g (
g(1/Lin)·(k1Δ2)) is output.

The difference calculation circuit 52 described above is a coefficient circuit 5 that outputs the coefficient g.
8 and a subtracting circuit 48, the difference calculation output (g-
(1/Lin)·(k1Δ2)) is output.

The above-mentioned amplifier circuit 54 receives the input signal Xin delayed for a predetermined time by the delay circuit 53 and receives the difference calculation output (
After being amplified using g−(1/Lin)·(k1Δ2)) as a gain, it is output from the output terminal 38.

Further, the third functional block of the signal level processing device includes an absolute value circuit 32, a comparator (C
It consists of an OMP) 33, a delay circuit (DELAY) 45, an amplifier circuit 54, an arithmetic circuit 59, a difference arithmetic circuit 60, and a multiplier circuit 61.

Components that are the same as those described above are given the same reference numerals, and their explanations will be omitted.

When the absolute value Lin, which is the output of the absolute value circuit 32, is smaller than the reference level L1, the comparator 33 closes the switch 4.
A control signal is output to the switch 41 to switch the movable contact No. 1 to the fixed contact on the lower side in the figure (the side of the coefficient circuit 42 that outputs the coefficient 0). As a result, the output of the arithmetic circuit 59 becomes zero, so the input signal Xin delayed for a predetermined time via the delay circuit 45 is amplified by the gain g from the multiplication circuit 61 in the amplifier circuit 54. Output. The input/output characteristics obtained thereby are in the region β (linear region) in FIG. 12, and no limiter processing or compressing processing is performed.

Moreover, when the absolute value Lin is larger than the reference level L1,
The comparator 33 outputs a control signal to the switch 41 to switch the movable contact of the switch 41 to the fixed contact shown on the upper side in the figure. This is the region α (nonlinear region).As is clear from this characteristic diagram, the input signal is compressed or limited in this case).

The arithmetic circuit 59 described above is a reference level generation circuit (REF).
39, subtraction circuit 40, switch 41, coefficient circuit 42, 6
3, multipliers 44 and 45, and a divider (DIV) 62. Then, when the absolute value Lin of the input signal Xin is larger than the reference level L1, a function related to the difference between the level of the input signal Xin and the reference level L1 is calculated (Li
n-L1=Δ, k1Δ2), and the calculation result is input signal
The calculation output obtained by dividing by the level of in (1/Lin)・(
k1Δ2) is output.

The difference calculation circuit 60 described above is a coefficient circuit 4 that outputs a coefficient 1.
7 and a subtraction circuit 48, and the difference calculation output obtained by calculating the difference between this coefficient 1 and the calculation output of the calculation circuit 59
1-(1/Lin)·(k1Δ2)) is output.

The multiplication circuit 61 described above includes a multiplier 64 and a coefficient circuit 65 that outputs a coefficient g, and multiplies this coefficient g by the output of the difference calculation circuit 60.

The amplifying circuit 54 described above amplifies the input signal Xin delayed by a predetermined time in the delay circuit 53 using the output of the multiplier circuit 61 as an amplification gain, and then outputs the signal at the output terminal 38.
is output from.

As an example of the above function, we have explained using a quadratic function of Δ such as (Δ2), but a function of tertiary or higher order of Δ, such as (k1
Δ2+k2Δ3) to obtain free input/output characteristics, or conversely, the compressor ratio may be 100:1.
The function is not limited to Δ2, such as a linear function of Δ.

Furthermore, in the arithmetic circuits 34, 51, and 59, there are various ways to give the coefficient k1, as described above.
In the end, it is sufficient to create a structure that allows .

Furthermore, although the level detection of the input signal Xin has been described using the absolute value Lin, it is not limited to this, and any rectifier circuit may be used, and it goes without saying that a time constant may be added.

Now, the functional block diagrams shown in FIG. 7 to FIG.
It was described that the data (data corresponding to one of the left and right channels of digital audio signals) Xin output from either the output terminal of R1 or the output terminal c is subjected to limiter or compress processing. However, there is no explanation of how to process data according to the other channel.

Therefore, here, DSP14L1 or DSP14R1
The following describes how the two data output from the two output terminals b and c are subjected to limiter or compress processing. Components that are the same as those described above are given the same reference numerals, and their explanations will be omitted.

In FIG. 13, DSP14L1 or DSP14R1
The input signal Xin output from the output terminal of is input to the input terminal 31 (input terminal a of DSP14L2 or
1), and also outputs to DSP14L1 or DS
Input signal X2i output from output terminal c of P14R1
n is output to the input terminal 310 (corresponding to each input terminal a2 of the DSPs 14L2 and 14R2).

The absolute value circuit 32 detects and outputs the absolute value Lin of the level of the input signal (digital data) Xin supplied from the input terminal 31, and the absolute value circuit 320 detects and outputs the absolute value Lin of the level of the input signal (digital data) Xin supplied from the input terminal 310. The absolute value L2in of the level is detected and output. The maximum value selection circuit (MAXSEL) 100 selects the maximum value between the absolute value L2in of the input signal X2in and the absolute value Lin of the input signal After performing the same calculation as described above with the input signal (digital data) Xin delayed by a predetermined time via the delay circuit 45, the output signal from the output terminal is output to the output terminal. 38(
(corresponding to output terminal C of DSP14L2 or DSP14R2).

As a result, the left and right two channel arithmetic circuits 34, 51,
59 outputs match, and the volume balance is kept constant.

In the figure, 35+36 has the functions of the difference calculation circuit 35 and the multiplication circuit 36, and similarly, 52+54 has the functions of the difference calculation circuit 52 and the amplifier circuit 54, and 60+61+
54 has the functions of a difference calculation circuit 60, a multiplication circuit 61, and an amplification circuit 54.

(Problem to be Solved by the Invention) In the above-mentioned signal level processing device, when performing limiter processing or compressing processing on a digital signal waveform, arithmetic overflow occurs. Depending on the type, there was a problem that a desired characteristic curve could not be obtained due to saturation constraints.

For example, when realizing the characteristic curve Q2 shown in FIG. 6, the maximum value of the input level and the maximum value of the output level almost match, so even if the input level exceeds the maximum value, that is, an excessive input occurs, this will not occur. By saturation, the output reaches its maximum value and the output is also saturated, so a 1:1 input/output characteristic curve can be achieved and no saturation failure occurs (corresponding to FIG. 3(a)). The broken line in the figure shows 1:1 input/output characteristics)
. This is an essential characteristic in order to record the input level as high as possible on the recording medium.

However, in the case of an input/output characteristic curve in which the maximum value of the input level and the maximum value of the output level do not match (corresponding to Fig. 3(b), the broken line in the figure shows the input/output characteristic in the form of a broken line), for example, An example characteristic curve is shown in FIG. 3(c),
If an excessive input is saturated at a predetermined level or higher, a saturation failure occurs because the obtained output continues to maintain the maximum value Ym (that is, the input (P1-P2) exceeding the threshold level Vth is (P1-P
There was a problem that the output of 3) could not be obtained (however, saturation failure can be avoided by moving the characteristic curve S3 downward in parallel in the figure so that P3 on the extension line of the characteristic curve S3 is at the position of P2) ).

Therefore, the limiter/compressor device according to the present invention is provided with word length expansion means, level enhancement means, and word length reduction means, which will be described later, so that saturation failure does not occur even if there is an excessive input. ) is translated downward in the figure to form a characteristic curve S7, thereby attempting to obtain an input/output characteristic curve in which saturation failure does not occur. As a result, low-level input, which is essential for signal transmission media such as broadcasting stations, can be reproduced with good clarity.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides the following (1)
) to (6).

(1) Word length extension means for extending the word length of an input digital signal; Level enhancement means for enhancing the level of the output signal from the word length extension means; Limiting or compressing the output signal from the level enhancement means. A limiter/compressor device comprising: limiter/compressor means for reducing an output signal from the limiter/compressor means to an original word length.

(2) The limiter/compressor device according to claim 1, wherein the word length extension means has sufficient head merge that does not saturate at a level that can be increased by the level increase means.

(3) word length extension means for extending the word length of an input digital signal; level enhancement means for enhancing the level of the output signal from the word length extension means; and an extended threshold for the output signal from the level enhancement means. limiter/compressor means for limiting or compressing the level; attenuation means for attenuating the output signal from the limiter/compressor means; and word length reduction means for reducing the output signal from the attenuation means to the original word length. A limiter/compressor device comprising:

(4) attenuation means for attenuating the input digital signal by a predetermined value; level control means for level-shifting the output signal from the attenuation means in the positive direction; limiter/compressor means for limiting or compressing at a threshold level calculated based on the level of the limiter/compressor means, and amplifying the output signal from the limiter/compressor means with an amplification amount complementary to the attenuation amount of the attenuation means. and an amplification means for returning the input digital signal to its original value, the limiter/compressor device being configured such that the threshold level of the limiter/compressor means can be level-shifted in the positive direction. .

(5) a first level variable section that varies the level of the input digital signal; an equalizer section; a limiter/compressor section that limits or compresses the output signal from the first level variable section; A limiter/compressor device comprising a level variable section and a signal switching control section, wherein when the signal switching control section is in a first signal switching control state, the output signal from the first level variable section is The signal is supplied to the equalizer section via the limiter/compressor section, the final level is adjusted by the second level variable section as necessary, and the signal is output when the signal switching control section is in the second signal switching control state. The output signal from the first level variable section is attenuated by a predetermined amount in addition to the level set by the first level variable section, and then supplied to the limiter/compressor section via the equalizer section. In addition to the level set by the second level variable section, the limiter/compressor means A limiter/compressor device characterized in that the threshold level of the limiter/compressor is configured to be variable between the first and second signal switching control states.

(6) a first level variable section that varies the level of the input digital signal; an equalizer section to which the output signal from the first level variable section is supplied; and a limiting or conditioning section for the output signal from the equalizer section. It has a limiter/compressor section for pressing, and a second level variable section to which the output signal from the limiter/compressor section is supplied, and the level setting sections of the first and second level variable sections and the limiter / The limiter / is operated at the first setting value set in the threshold level setting section of the compressor section.
A limiter/compressor device characterized in that the value of each setting section of the first and second level variable sections can be set based on the value set by the threshold level setting section of the compressor section.

(Example) Hereinafter, a limiter/compressor device according to the present invention will be explained with reference to FIGS. 1 to 6. Components that are the same as those described above are given the same reference numerals, and their explanations will be omitted.

1 and 2 are block diagrams of the first and second embodiments of the limiter/compressor device according to the present invention, and FIG. 3(a)
~(d) are input/output characteristic diagrams explaining the present invention, FIG. 4 is a functional block diagram of the limiter/compressor device according to the present invention, and FIGS. 5(a) to (c) are diagrams of FIGS. 1 and 2. FIG. 6 is a diagram for explaining the operation of the limiter/compressor device shown in the figure, and FIG. 6 is a diagram for explaining the positive threshold voltage Vth.

The limiter/compressor device according to the present invention is used for signal processing of the DSP14L2 and DSP14R2 shown in FIG. 10, and its functions are shown in FIG. 4, and its block diagram is shown in FIG. This is shown in FIG.

Now, in the limiter/compressor device according to the present invention, the data (input digital signal) output from each output terminal b of DSP14L1 and DSP14R1 shown in FIG.
It is supplied to each input terminal a1 of SP14L2 and DSP14R2, and each output terminal c of DSP14L1 and DSP14R1
The data (input digital signal) output from the DSP
14L2 and each input terminal a2 of the DSP 14R2.

As shown in Figure 1, the DSP14L2 extends the word length of the left channel input digital audio signal (the 16-bit word length shown in Figure 5(a)) by 24 bits in the direction of the upper bits, creating a 40-bit word. (Fig. 5(b))
a word length extension means 202 for outputting a signal shown in FIG. The limiter/compressor means 204 performs limiting or compressing, and the output signal from the limiter/compressor means 204 is adjusted such that the most significant bit thereof is equal to the most significant bit of the input digital signal of the word length extending means 202 (FIG. 5(c) ), and word length reduction means 205 for reducing the word length.

A signal obtained by subjecting the left channel digital audio signal to limiter processing or compressor processing is output from output terminal c. The controller 206 includes an operating section 15 that has a plurality of pushbutton switches and is operated to obtain desired equalizer characteristics, limiter characteristics, or compressor characteristics, and a display section 1 that includes a CRT, a lamp, an LED, etc.
6. The DSP 14L causes the display unit 16 to display a display corresponding to the operation of the operation unit 15, and reads a predetermined program from the ROM 18 to realize the specified characteristics.
The CPU 17 outputs various control signals to the DSP 1 to DSP 14R2 and controls them.

Further, the word length extension means 202 described above is the level enhancement means 2.
03 has enough head merging that does not saturate at a level that can be increased.

Furthermore, the DSP 14L2 may have a configuration in which attenuation means 209 is inserted between the limiter/compressor means 204 and the word length reduction means 205, as shown in FIG. Here, the attenuation means 209 attenuates the output signal from the limiter/compressor means 204 by a predetermined amount.

Although the above description is for the DSP 14L2, it goes without saying that the DSP 14R2 is also configured in a similar manner.

Next, the functions of the limiter/compressor device of the present invention shown in FIG. 4 will be explained.

As shown in the figure, the functions of the limiter/compressor device according to the present invention include an absolute value circuit 32, a comparator (CO
MP) 33, a difference calculation circuit 35, a multiplication circuit 36, a delay circuit (DELAY) 37, a calculation circuit 208, and a low-pass filter circuit 209. 31 is an input terminal, 3
8 is an output terminal.

The absolute value circuit 32 detects and outputs the absolute value Lin of the level of the input signal (digital data) Xin supplied from the input terminal 31. The comparator 33 described above compares the absolute value Lin supplied from the absolute value circuit 32 with a predetermined threshold level Vth. When the absolute value Lin is smaller than this level Vth, a control signal is output to the switch 41 to switch the movable contact of the switch 41 to the fixed contact on the lower side in the figure (the side of the coefficient circuit 42 that outputs the coefficient 0). As a result, the output of the arithmetic circuit 208 becomes zero, so the input signal Xin supplied to the multiplication circuit 36 via the delay circuit 37 is passed through the low-pass filter 209 at the multiplier 49 in the multiplication circuit 36. After the signal is multiplied by a coefficient 1 obtained by 1, it is amplified by an amplifier 50 with a gain g and output. As a result, the input/output characteristics are not subjected to limiter processing or compression processing.

Also, the absolute value Lin is the threshold level Vth
When it is larger, a control signal is output to the switch 41 to switch the movable contact of the switch 41 to the fixed contact on the upper side in the figure (the output side of the subtraction circuit 40). by this,
The output of the arithmetic circuit 208 described above is the arithmetic result ((1/Li
n)·(pΔ+qΔ2)), the resulting input/output characteristics are compressed or limited.

The arithmetic circuit 208 described above is a reference level generating circuit (REF).
) 39, subtraction circuit 40, switch 41, coefficient circuit 42,
211, 212, multipliers 44, 45, 210, divider (
DIV) 46 and an adder 213.

Then, when the absolute value Lin of the level of the input signal Xin is larger than the threshold level Vth, a function related to the difference between the absolute value Lin level of the input signal This Δ is multiplied by the coefficient p (pΔ), and this qΔ2 and pΔ
The value (pΔ+qΔ2) obtained by adding the above is divided by Lin to output the calculation result ((1/Lin)·(pΔ+qΔ2)).

This value becomes the calculation result of the calculation circuit 208 described above. The above-mentioned difference calculation circuit 35 is a coefficient circuit 47 that outputs a coefficient 1.
and a subtraction circuit 48 to which the result of the arithmetic circuit 208 described above is supplied, and this coefficient 1 and the arithmetic circuit 208
The difference calculation output (1-((1
/Lin)·(pΔ+qΔ2))) is output to the above-mentioned low-pass filter 209, where the above-mentioned difference calculation output below a predetermined cutoff frequency is output to the multiplication circuit 36.

The multiplier circuit 36 is composed of a multiplier 49 and an amplifier 50, and the multiplier 49 multiplies the input signal Xin delayed by a predetermined sampling time in the delay circuit 37 by the above-described difference calculation output from the low-pass filter 209.

At this time, since the delay time is not zero, the delay signal (Xin(t-d)) is supplied from the delay circuit 37 to the multiplier 49, so the input signal Xin, which has a rapid level fluctuation, passes through the delay circuit 37. It also becomes possible to compress or limit.

Although not detailed here, the present invention also includes a limiter/
In addition to the above-described first and second embodiments of the compressor device, third, fourth, and fifth embodiments having the following configurations can be considered.

That is, the third limiter/compressor device according to the present invention
The embodiment includes an attenuation means for attenuating an input digital signal by a predetermined value, a level control means for level-shifting the output signal from the attenuation means in the positive direction, and an output signal from the level control means at the decimal point of the input digital signal. limiter/compressor means for limiting or compressing at a threshold level calculated based on the level of It has an amplification means for returning the input digital signal to its original value, and is configured to be able to shift the threshold level of the limiter/compressor means in the positive direction.

Further, the fourth limiter/compressor device according to the present invention
The embodiment includes a first level variable section that varies the level of an input digital signal, an equalizer section, a limiter/compressor section that limits or compresses the output signal from the first level variable section, and a second level variable section that limits or compresses the output signal from the first level variable section. The limiter/compressor device includes a level variable section and a signal switching control section, and when the signal switching control section is in a first signal switching control state, the output signal from the first level variable section is transferred to the limiter/compressor device. The signal is supplied to the equalizer section via the compressor section, the final level is adjusted by the second level variable section as necessary, and the signal is output. When the signal switching control section is in the second signal switching control state, the first The output signal from the level variable section is added to the level set by the first level variable section,
After being attenuated by a predetermined amount, it is supplied to the limiter/compressor section via the equalizer section, and is amplified by an amplification amount complementary to the attenuation amount in addition to the level set by the second level variable section. The threshold level of the limiter/compressor means is made variable between the first and second signal switching control states by returning the input digital signal to the value of the input digital signal.

Furthermore, the fifth embodiment of the limiter/compressor device according to the present invention has a first embodiment that varies the level of the input digital signal.
a level variable section, an equalizer section to which the output signal from the first level variable section is supplied, a limiter/compressor section that limits or compresses the output signal from the equalizer section, and this limiter/compressor section. a second level variable section to which an output signal of In addition to being operated at the set value of the limiter/compressor section, the value of each setting section of the first and second level variable section can be set based on the value set at the threshold level setting section of the limiter/compressor section. It is something.

(Effects of the Invention) As described above, the limiter/compressor device according to the present invention is particularly equipped with a word length expansion means, a level enhancement means, and a word length reduction means, so that the limiter/compressor device according to the present invention can be configured to operate as a limiter to obtain desired input/output characteristics. / Even if compressor processing is performed, saturation defects will not occur, so even if there is an excessive input, the playback sound will not be audibly unnatural, and even if the input is at a relatively low level, it will be possible to reproduce it with high fidelity. This has the effect of being able to reproduce relatively low-level input with better clarity compared to relatively high-level input. By providing sufficient head merging that does not saturate at a level that allows level enhancement, the positive threshold generated by the level enhancement means can be set arbitrarily without saturation, allowing more flexibility in achieving desired input/output characteristics. Further, saturation defects can be completely eliminated by providing attenuation means for attenuating the output signal from the limiter/compressor means, and furthermore, the threshold level of the limiter/compressor means can be set to an arbitrary value. In order to vary the threshold level, the threshold level can be level shifted in the positive direction, or the threshold level of the limiter/compressor means can be varied between the first and second signal switching control states, and on the other hand, the limiter/compressor means By making it possible to set the values of each setting section of the first and second level variable sections that vary the level of the input digital signal based on the value set in the threshold level setting section of the section, various states can be achieved. This has the effect of providing scalability as a system that can also be used.

[Brief explanation of the drawing]

1 and 2 are block diagrams of the first and second embodiments of the limiter/compressor device according to the present invention, and FIG. 3(a)
~(d) are input/output characteristic diagrams explaining the present invention, FIG. 4 is a functional block diagram of the limiter/compressor device according to the present invention, and FIGS. 5(a) to (c) are diagrams of FIGS. 1 and 2. 6 is a diagram for explaining the positive threshold voltage Vth, and FIGS. 7 to 9 are diagrams for explaining the operation of the limiter/compressor device shown in FIG.
The third functional block diagram, FIG. 10, and FIG. 13 are block diagrams of audio signal processing devices to which the signal level processing device is applied, and FIGS. 11(a) and (b) are the signal level processing devices shown in FIG. 10. FIG. 12 is a flowchart showing the operation of the CPU 17, which is the main part of the system, and is an input/output characteristic diagram of the signal level processing device shown in FIGS. 7 to 9. 32...Absolute value circuit, 33...Comparator, 34, 51,
59, 208... Arithmetic circuit, 35, 52, 60... Difference computing circuit, 36... Multiplication circuit, 37, 45, 53... Delay circuit, 5
4...Amplification circuit, 202...Word length extension means, 203...Level enhancement means, 204...Limiter/compressor means, 20
5... Word length reduction means, 206... Controller, 207... Attenuation means. Patent applicant: Victor Japan Co., Ltd.

Claims (6)

[Claims] 1. Word length extension means for extending the word length of an input digital signal; Level enhancement means for enhancing the level of the output signal from the word length extension means; Limiting or limiting the output signal from the level enhancement means. A limiter/compressor device comprising: a limiter/compressor means for compressing; and a word length reduction means for reducing the output signal from the limiter/compressor means to the original word length. 2. The limiter/limiter according to claim 1, wherein the word length extension means has sufficient head merging that does not saturate at a level that can be increased by the level enhancement means.
compressor equipment. 3. Word length extension means for extending the word length of an input digital signal; level enhancement means for enhancing the level of the output signal from the word length extension means; limiter/compressor means for limiting or compressing at a threshold level; attenuation means for attenuating the output signal from the limiter/compressor means; word length for reducing the output signal from the attenuation means to the original word length. A limiter/compressor device comprising: reduction means. 4. Attenuation means for attenuating an input digital signal by a predetermined value; level control means for level-shifting an output signal from the attenuation means in the positive direction; limiter/compressor means for limiting or compressing at a threshold level calculated based on the level of the decimal point, and an amplification amount complementary to the attenuation amount of the attenuation means for the output signal from the limiter/compressor means and amplifying means to return the input digital signal to its original value by amplifying the input digital signal, the limiter being configured to be able to shift the threshold level of the limiter/compressor means in the positive direction. /Compressor equipment. 5. A first device that varies the level of the input digital signal.
a level variable section, an equalizer section, a limiter/compressor section that limits or compresses the output signal from the first level variable section, a second level variable section, and a signal switching control section. In the limiter/compressor device, when the signal switching control section is in a first signal switching control state, the output signal from the first level variable section is supplied to the equalizer section via the limiter/compressor section. , the final level is adjusted by the second level variable section as necessary and outputted, and when the signal switching control section is in the second signal switching control state, the first
The output signal from the level variable section is attenuated by a predetermined amount in addition to the level set by the first level variable section, and then supplied to the limiter/compressor section via the equalizer section. In addition to the level set in the level variable section 2, the threshold of the limiter/compressor means is amplified by an amplification amount complementary to the attenuation amount and returned to the original value of the input digital signal. A limiter/limiter characterized in that the level is made variable between the first and second signal switching control states.
compressor equipment. 6. A first device that varies the level of the input digital signal.
an equalizer section to which the output signal from the first level variable section is supplied; a limiter/compressor section that limits or compresses the output signal from the equalizer section; and a limiter/compressor section. a second level variable section to which an output signal of It is operated at the first setting value, and the limiter/
A limiter/compressor device characterized in that the value of each setting section of the first and second level variable sections can be set based on the value set by the threshold level setting section of the compressor section.